JPS62198292A - Display device - Google Patents

Abstract

PURPOSE:To confirm easily an external synchronizing frequency by displaying an external synchronizing signal frequency on a picture of a display being in the course of a convergence adjustment. CONSTITUTION:For instance, when a horizontal oscillating circuit 15 is oscillated by 31.5Hz, it is shaped by a pulse shaping circuit 1 and formed to a pulse whose width is about 30ns, and by the leading edge of this pulse, a 12 bit output of a counter 3 is loaded. The counter 3 counts an output of a crystal oscillator 2 for one period of an output of the horizontal oscillating circuit 15, namely, for 1/31500-31.746mus. An output '454' of the counter is latched by a latch memory 4, converted to (31.50) by a conversion ROM, a pattern of (31.50) is outputted from a character generator 6, an output of the character generator 6 is selected in accordance with a horizontal scan by a selector 7, the address of the character generator 6 is varied at every 1H, and a pattern of (31.50) is formed. It is converted to a series signal by a shift register 8, and an oscillation frequency is displayed on a picture.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display device equipped with a signal generator for convergence adjustment of a high-definition display, such as a projection television receiver, in particular.

Conventional technology For example, when the input synchronization signal is horizontal, it is 31.5KHz.

If they are different, such as 33Kllz and 28KIIz, the input cable is used to confirm which frequency the input synchronization signal is. Also with digital convergence.

When writing misconvergence correction values for each point on the screen into a nonvolatile memory, an address in the nonvolatile memory corresponding to the input is selected and written.

Problems to be Solved by the Invention When adjusting convergence using a crosshatch synchronized with an external synchronization signal, if the device is large such as a projection type, the convergence adjustment section and the signal input section are separated, and the current display The disadvantage is that it is difficult to determine the frequency of the horizontal and vertical synchronizing signals of the crosshatch by tracing the cables, and it takes time to confirm.

The present invention aims to provide a device that allows easy confirmation of an external synchronization frequency.

Means for Solving the Problems The display device of the present invention includes a crosshatch or dot pattern signal generator for convergence adjustment, and two
A deflection circuit synchronized with horizontal and/or vertical external synchronization signals of different frequencies is provided, and the frequency of the external synchronization signal is measured using a reference time signal generator and a counter, and the frequency of the external synchronization signal is measured using a reference time signal generator and a counter. The present invention is characterized in that the measurement frequency is displayed on a part of the convergence adjustment screen.

Effect: According to this configuration, the external synchronizing signal frequency is displayed on the screen of the display device during convergence adjustment.

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 to 4.

FIG. 1 shows a display device of the invention. 1 is a pulse shaping circuit that forms a thin pulse to reset the counter 3, and 2 is a 14.3181MHz crystal oscillator.

4 is a 12-bit latch memory, and 5 is a conversion ROM that converts the output of the latch memory 4 into a 4-digit BCD code.

6 is a character generator, 7 is a selector that selects four outputs of the character generator 6, 8 is a shift register as a parallel-to-serial converter that converts a parallel signal into a serial signal, 12 is an AND gate, 9R19G, 9B is a character generator 6 10B is a video output circuit, II
R, IIG, and IIB are cathode ray tubes that serve as light sources for the projection television receiver.

The outline of the operation is 1. For example, the horizontal oscillation circuit 15 is 31.5K.
1(z), the pulse shaping circuit 1 shapes this into a pulse with a width of about 30 ns, and loads the 12-pit output of the counter 3 at the leading edge of this pulse.

The counter 3 counts the output of the crystal oscillator 2 during one period of the output of the horizontal oscillation circuit 15, that is, 1/31500-31.746 μS. The output of counter 3 should be "454" or "455". If it is 454”, it will be 31.
50K)lz is the conversion ROM5. The output "454" of the counter 3 is latched into the latch memory 4, and converted into r31.50J by the conversion ROM 5.
r31.50 shown in Figure 3 from Character Generator 6
The pattern J is output, the selector 7 selects the output of the character generator 6 according to horizontal scanning, and the address of the character generator 6 is changed for each IH.
31.50" pattern. Generally, horizontal direction 5
Since four sets of ~8 dots are output from the character generator 6, these are converted into a serial signal by the shift register 8,
AND gate 12, mixer 9R, 9G, 9B amplifier 1
0R, IOG, IOB, Braun tube 11R, IIG, I
The oscillation frequency is displayed on the screen via the IB as shown in FIG.

I will explain in more detail. Here, a high-definition display is formed using a projection television receiver, and horizontal scanning lines of 500 to 7
Consider a case where approximately 00 signals (each field) are to be displayed. Since the screen is large, the convergence circuit usually consists of static convergence and dynamic convergence, and the dynamic convergence is an electrically rewritable non-volatile memory EEPROM.
When storing the correction amount, it is necessary to change the correction value in accordance with changes in the vertical and horizontal synchronization signals. When switching the frequency of the synchronization signal, prepare as many memories as the frequencies of the synchronization signal to be matched.

At the same time, the memory address (or memory chip) will be switched. By the way, convergence adjustment often uses a crosshatch signal, and expensive receivers such as those used in projection-type high-definition displays have a built-in crosshatch signal. In FIG. 2, 14 is a horizontal AFC circuit, which is synchronized with an external input synchronization signal. This horizontal AFC circuit 1
4 controls the horizontal oscillation circuit 15, so even if the horizontal synchronization signal input to the horizontal AFC circuit 14 includes a vertical synchronization signal, the output of the horizontal oscillation circuit 15 will always be a signal with a constant period. . On the other hand, 16 is a vertical oscillation circuit that oscillates in response to an external vertical synchronization signal. Horizontal AFC circuit 1
4. The time constants of the horizontal oscillation circuit 15 and the vertical oscillation circuit 16 are:
In some cases, it is switched in response to the frequency of an external synchronization signal. The crosshatch signal generator 17 generates the crosshatch signal shown in FIG. 3 using the vertical synchronization pulse and the horizontal synchronization pulse, and supplies an output to the selector 18. Selector 1
8 is controlled by a manual switch (not shown), and when crosshatch is specified during convergence adjustment, the output of the crosshatch signal generator 17 is output to mixers 9R, 90, and 9B instead of the R, G, and B signal inputs. . On the other hand, the convergence waveform/voltage control circuit 19 writes into the EEPROM 20 the dynamic convergence correction amount at the crosshatch intersection shown in FIG.

That is, the horizontal and vertical convergence of R, G, and B is adjusted using buttons or knobs to match each point of the crosshatch, and data is written to the corresponding address in the EEPROM 20 for each point.

21R, 21G, and 21B are dynamic convergence circuits having the same configuration.

Now, if you want to adjust convergence while looking at the screen,
If you only look at the crosshatch, you may not be able to understand or confuse the input synchronization signals, and the same data may not be transferred to EEPROM2.
You may write to 0 or write the address incorrectly. Therefore, in the present invention.

Each time the frequency of the synchronization signal is switched, in the case of a crosshatch, that frequency is measured and displayed numerically. 1st
In the figure, the crystal oscillator 2Q of the crystal oscillator 2 is 14.3
1818 MIIz, and this circuit typically operates at ±100Hz.
It is operating stably within The output of the horizontal oscillator 15 is waveform-shaped by the pulse shaping circuit 1 to create a pulse with a width of about 3 Qns. This pulse φ (see FIG. 4 φ1) is applied with positive polarity to the load terminal of the latch memory 4, and the output of the counter 3 is read at the rising edge.

A negative polarity pulse φ2 (see FIG. 4 φ2) is supplied to the clear terminal of the counter 3. If this negative polarity pulse φ2 is delayed by approximately 30 ns from the positive polarity pulse φ3, φ2. φ is approximately 60 ns, which approaches the repetition period of 70 ns for the output φ of the crystal oscillator 2.

When loading the latch memory 4 or clearing the counter 3, a falling edge of φ1 appears and the output value of the counter 3 changes during loading, or the count decreases by one clock, but it is difficult to judge one frequency. Counter 3 is a 12-pit binary counter, and 1
4.3181.8MHz can be divided by 4095, but in this case, the divided output will be about 349Hz. 31.5K
If IIz, the frequency division ratio will be between "454" and "455". "454" is 31,538 Hz.

If it is "453", it becomes 31.607 KHz, and if it is "455", it becomes 31.468 Ilz. Therefore, even if one φ1 in FIG. 4 is miscounted, a measurement error of 100 Hz or more will not occur. Also, even if the oscillation frequency changes by ±10011z, if the frequency is divided by 453, 3 ], , 11z to 607, 45
If the frequency is divided by 5, it will not be affected by 468 Hz. In other words, using a crystal oscillator, the fluctuation of one oscillation frequency will be ±10011
If it is below z, 31.5Kl (approximately 100Kl around z)
It is possible to discriminate between synchronization signals that differ by 11z or more.

On the other hand, when the horizontal frequency is 15.734 Kt (z), the division ratio will be between 910" and "911", and when divided by 910, it becomes 15.734 KHz, and when divided by 911, it becomes 15,71
7KHz, and even if the oscillation frequency deviates by ±100Hz,
If the frequency is divided by 910, it becomes 15.734KHz. That is, 1
If it is around 5,734 Hz, it can be determined by the input frequency difference of 5011 Hz.

As described above, the frequency of the synchronizing signal can be determined by decimating the output of the counter (frequency division ratio) and displaying it in four digits. If the counter 3 is made up of 4 decimal units in series, the latch memory 4 will also be 16
Although it is a bit, ROM5 becomes easier. However, here 3 is a binary counter and 4 is a 12-bit latch memory. Converts the output of the latch memory into binary and decimal R
Supplied to OM5 in the form of an address. 5 is considered to be a 4x4=16-bit parallel output, but with a 4-bit output, 4 digits may be sequentially output according to the horizontal scanning of the beam, but the conversion R
Since the OM5 must operate at high speed, we will assume here that four digits worth of 16 bits are output in parallel to simplify the explanation. 4 pieces in parallel. Therefore, the 4-digit BCD (4 bits) output from the conversion ROM 5 is added as an address to each ROM of the character generator 6, and in synchronization with the vertical scanning, one horizontal scanning line (in the case of FIG. 3) at the end of the vertical scanning ( Or 2 or 3) every time.

The character generator 6 outputs dot signals (forming segment signals) for each row of displayed characters in the horizontal direction. Selector 7 is 1, for example 14.31818M
) When the beam scans from the screen thread to the right using a switching pulse obtained by dividing the frequency of the lz clock, the output of the character generator 6 is sequentially switched character by character and transmitted from the selector 7 to the parallel-to-serial converter 8. If the character font is 5 dots horizontally, the output of the character generator 6 is 5×4=20 (lines), and the data of 4 sets of 5 lines are collectively switched and transmitted to the parallel-to-serial converter 8. This parallel-serial converter 8 is, for example.

Parallel input like digital IC model number 74LS166 →
A serial output type shift register may be used, S bit input, 3
If you use 8 bits (input "O") without inputting bits, the character spacing can be 3 bits. The load pulse can be applied to the parallel-to-serial converter 8 in synchronization with the switching of the selector 7.The clock of the parallel-to-serial converter 8 may be the displayed clock 1, for example, 7.159090Hz.This frequency is set by the crystal oscillator 2. This is the output of φ1 divided by 172. When the erase switch 13 is not set, the output of the erase switch 13 is at a high level, the AND gate 12 is conductive, and the output of the parallel to serial conversion m8, that is, the character pattern signal, is sent to the mixing circuits 9R, 90, 9B. The R, G, and B signals, in this case, the crosshatch signal, are mixed with each other and displayed as r31.50J as shown in FIG. The above-mentioned "31°53" may be displayed. These processes are performed in the conversion ROM 5. When adjusting the convergence elbow, r31°50
” If the numerical display is a nuisance, scan the erase switch 13,
AND gate 12 sets the output of 13 to low level “L”
All you have to do is shut off the r31.50J in Figure 3.

In this way, the frequency can be displayed in response to changes in the input horizontal synchronization signal.

Details of the invention As described above, the display device of the present invention is as follows.

Even when there are several types of input synchronization signal frequencies and the frequencies are close to each other, the frequency can be determined without having to trace the cable to the signal source and check the output state of the signal source. Therefore, it is possible to avoid a situation where an erroneous write is performed when a dynamic focus correction value is written to the EEPROM.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the display device of the present invention, FIG. 2 is a block diagram for explaining the operation of FIG. 1,
FIG. 3 is an explanatory diagram of the display state, and FIG. 4 is a waveform diagram of the main part of FIG. 1. DESCRIPTION OF SYMBOLS 1...Pulse shaping circuit, 2...Crystal oscillator [reference time signal generator], 3...Counter, 4...Latch memory, 5...Conversion ROM, 6...Character generator. 7...Selector, 8...Ordinary to direct converter, OR, 9G
. 9B... Mixer, LOR, LOG, IOB... Video output circuit, 11R, IIG, ■B... Braun tube,
12...AND gate, 13...Erase switch k + Shima) (t)

Claims (1)

[Claims] 1. A crosshatch or dot pattern signal generator for convergence adjustment and a deflection circuit synchronized with horizontal and/or vertical external synchronization signals of two or more different frequencies are provided, and the external synchronization A display device configured to measure the frequency of a signal using a reference time signal generator and a counter, and display the measured frequency on a part of a convergence adjustment screen via a character generator. 2. The reference signal generator is configured with a crystal oscillator whose frequency is sufficiently higher than that of the input synchronization signal, and the counter is configured with an input synchronization signal or a pulse synchronized with this synchronization signal while dividing the output of the crystal oscillator. Claim 1, characterized in that the counter is configured to be reset, the counted value of the counter is recorded in a latch memory, and the contents of the latch memory are converted into numbers via a character generator and displayed. Display device as described.