JPH0572156B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to projection television receivers, etc.
In particular, the present invention relates to a display device equipped with a signal generator for convergence adjustment of a high-definition display.

Conventional technology If the input synchronization signal is horizontal, for example, 31.5KHz,
If the frequencies are different, such as 33KHz and 28KHz, check the input cable to determine which frequency is the input sync signal. Furthermore, in digital convergence, when writing misconvergence correction values for each point on the screen into a nonvolatile memory, an address in the nonvolatile memory corresponding to the input is selected and written.

Problems to be Solved by the Invention When adjusting convergence using a crosshatch synchronized with an external synchronization signal, if the device is large such as a projection type, the convergence adjustment section and signal input section are separated, and the current display The disadvantage is that it is difficult to determine the frequency of the horizontal and vertical synchronizing signals of the crosshatch by tracing the cables, and it takes time to confirm.

The present invention aims to provide a device that allows easy confirmation of an external synchronization frequency.

Means for Solving the Problems The display device of the present invention includes a crosshatch or dot pattern signal generator for convergence adjustment, and a deflection circuit synchronized with horizontal and/or vertical external synchronization signals of two or more different frequencies. Further, the frequency of the external synchronization signal is measured using a reference time signal generator and a counter, and the measured frequency is displayed on a part of the convergence adjustment screen via a character generator. .

Effect: According to this configuration, the external synchronization signal frequency is displayed on the screen of the display device during convergence adjustment.

Embodiment Hereinafter, one embodiment of the present invention will be described based on FIGS. 1 to 4.

FIG. 1 shows a display device of the present invention. 1
2 is a 14.3181MHz crystal oscillator, 4 is a 12-bit latch memory, and 5 is a conversion circuit that converts the output of latch memory 4 into a 4-digit BCD code.
ROM, 6 is a character generator, 7 is a selector for selecting four outputs of character generator 6,
8 is a shift register as a parallel-to-serial converter that converts parallel signals into serial signals, 12 is an AND gate, and 9R, 9G, 9B are character generators 6.
a mixer for mixing the output of into R, G, B signals, 1
0R, 10G, 10B are video output circuits, 11R,
Reference numerals 11G and 11B are cathode ray tubes that serve as light sources for the projection television receiver.

The outline of the operation is, for example, when the horizontal oscillation circuit 15
Assuming that it is oscillating at 31.5 KHz, the pulse shaping circuit 1 shapes it into a pulse with a width of about 30 ns, and loads the 12-bit output of the counter 3 at the leading edge of this pulse. Counter 3 is horizontal oscillation circuit 15
1 period of the output, i.e. 1/31500 = 31.746μs
During this period, the output of the crystal oscillator 2 is counted. counter 3
The output should be "454" or "455". In the case of "454", the ROM that represents 31.50KHz is the conversion ROM 5. The output “454” of the counter 3 is latched in the latch memory 4 and is stored in the conversion ROM 5.
31.50'', and the character generator 6 outputs the pattern ``31.50'' shown in Figure 3.
Select the output of the character generator 6 according to horizontal scanning with the selector 7, change the address of the character generator 6 every 1H, and select "31.50" in Fig. 3.
make a pattern. Generally, four sets of 5 to 8 dots in the horizontal direction are output from the character generator 6, so this is converted into a serial signal by the shift register 8, and then the signal is sent to the AND gate 12, mixer 9R, 9G,
The oscillation frequency is displayed on the screen as shown in FIG. 3 via the 9B amplifiers 10R, 10G, 10B and the cathode ray tubes 11R, 11G, 11B.

I will explain in more detail. Let us now consider the case where a high-definition display is formed using a projection television receiver, and signals of about 500 to 700 horizontal scanning lines (each field) are displayed. Since the screen is large, the convergence circuit usually consists of a static convergence and a dynamic convergence, and the dynamic convergence is often of the type where the correction amount is stored in EEPROM, an electrically rewritable non-volatile memory. When storing the correction amount, it is necessary to change the correction value as the vertical and horizontal synchronization signals change.In order to switch the convergence correction amount in response to the synchronization signal during initial setting, the corresponding synchronization signal must be changed. When you prepare memories for the number of frequencies and switch the frequency of the synchronization signal,
At the same time, the memory address (or memory chip)
You will have to switch. By the way, convergence adjustment often uses a crosshatch signal, and expensive receivers such as those used in projection high-definition displays have a built-in crosshatch signal. In FIG. 2, 14 is a horizontal AFC circuit, which is synchronized with an external input synchronization signal. Since the horizontal oscillation circuit 15 is controlled by the output of this horizontal AFC circuit 14, the horizontal
Even if the horizontal synchronization signal input to the AFC circuit 14 includes a vertical synchronization signal, the output of the horizontal oscillation circuit 15 is always a signal with a constant period. On the other hand, 16 is a vertical oscillation circuit that oscillates in response to an external vertical synchronization signal. horizontal AFC circuit 14, horizontal oscillation circuit 15,
The time constant of the vertical oscillation circuit 16 may be changed depending on the frequency of an external synchronization signal. The crosshatch signal generator 17 generates a vertical synchronization pulse,
The horizontal sync pulse is used to generate the crosshatch signal shown in FIG. 3, which provides an output to selector 18. The selector 18 is controlled by a manual switch (not shown), and when crosshatch is specified during convergence adjustment, the output of the crosshatch signal generator 17 is sent to the mixer 9R, 9 instead of the R, G, B signal input.
Output to G, 9B. On the other hand, the convergence waveform/voltage control circuit 19 writes into the EEPROM 20 the dynamic convergence correction amount at the crosshatch intersection shown in FIG. That is, R,
Adjust the horizontal and vertical convergence of G and B using buttons or knobs to match each point of the crosshatch, and write data to the corresponding address in the EEPROM 20 for each point. 21R, 21
G and 21B are dynamic convergence circuits having the same configuration.

Now, when adjusting the convergence while looking at the screen, if you only look at the crosshatch, you may not be able to understand or confuse the input synchronization signals, and you may write the same data to the EEPROM 20 or write the wrong address. be. Therefore, in the present invention, each time the frequency of the synchronization signal is rewritten, in the case of a crosshatch, the frequency is measured and displayed numerically. In FIG. 1, the crystal oscillator 2Q of the crystal oscillator 2 has a frequency of 14.31818 MHz, and this circuit normally operates stably within ±100 Hz. The output of the horizontal oscillator 15 is waveform-shaped by the pulse shaping circuit 1 to create a pulse with a width of about 30 ns. Apply this pulse ₃ (see Figure 4, ₃ ) with positive polarity to the load terminal of latch memory 4, read the output of counter 3 at the rising edge, and supply negative polarity pulse ₂ (see Figure 4, ₂ ) to the clear terminal of counter 3. do. If this negative polarity pulse ₂ is delayed by about 30 ns from the positive polarity pulse ₃ , as shown in Fig. 4, ₂ and ₃ will be about 60 ns, which will approach the repetition period of 70 ns of the output ₁ of the crystal oscillator 2, so the loading of the latch memory 4 will be delayed. Or, while counter 3 is being cleared, a falling edge of ₁ appears and the output value of counter 3 changes during loading, or the counter is counted down by one clock, but this does not have a major effect on determining the frequency. . counter 3
is a 12-bit binary counter, 14.31818MHz
can be divided by 4095, but in this case, the divided output will be around 349Hz. If it is 31.5KHz, the division ratio will be between "454" and "455". “454”
31.538KHz, “453” is 31.607KHz, “455” is
It becomes 31.468KHz. Therefore, even if one of the numbers ₁ in FIG. 4 is miscounted, a measurement error of 100 Hz or more will not occur.
Also, even if the oscillation frequency changes by ±100Hz, it will not be affected as it will be 31,607KHz if it is divided by 453 and 31.468KHz if it is divided by 455. That is, if a crystal oscillator is used and the fluctuation of the oscillation frequency is kept below ±100Hz, it is possible to distinguish synchronization signals that differ by about 100Hz or more around 31.5KHz. On the other hand, when the horizontal frequency is 15.734KHz, the division ratio will be between "910" and "911", and dividing by 910 will result in 15.734KHz, and dividing by 911 will result in 15.717KHz, so even if the oscillation frequency shifts by ±100Hz, If the frequency is 910
It becomes 15.734KHz. In other words, if it is around 15.734KHz,
It can be determined even by a 50Hz frequency difference in the input.

As mentioned above, the output of the counter (dividing ratio) is set to 10
If it has evolved and is displayed in 4 digits, you can find the frequency of the synchronization signal. If four decimal counters 3 are connected in series, the latch memory 4 will also be 16 bits, but the ROM 5 will be simpler. However, here 3 is a binary counter and 4 is a 12-bit latch memory. The output of the latch memory is supplied to the binary/decimal conversion ROM 5 in the form of an address. 5 is considered to be a 4 x 4 = 16-bit parallel output, but with a 4-bit output, it is also possible to output 4 digits sequentially according to the horizontal scanning of the beam, but the conversion
Since the ROM 5 must operate at high speed, it is assumed here that 4 digits of 16 bits are output in parallel to simplify the explanation. Character generator 6 outputs the 7 segment pattern shown in FIG.
Assume that 4 ROMs are connected in parallel. Therefore, the 4-digit BCD (4 bits) output from the conversion ROM 5 is added as an address to each ROM of the character generator 6, and in synchronization with the vertical scanning, in the case of FIG. For each book (or two or three), the character generator 6 outputs a dot signal (forming a segment signal) corresponding to one row of displayed characters in the horizontal direction. For example, when the beam scans the screen from left to right using a switching pulse obtained by dividing the frequency of the 14.31818 MHz clock, the selector 7 sequentially switches the output of the character generator 6 for each character, and performs parallel-linear conversion from the selector 7. Tell it to vessel 8. If the character font is 5 dots horizontally, the output of the character generator 6 is 5 x 4 = 20 (lines), 5
Four sets of data are collectively switched and transmitted to the parallel-to-serial converter 8. This parallel-to-serial converter 8
For example, it may be a parallel input to serial output type shift register such as the digital IC model number 74LS166,
5-bit input, no 3-bit input (input "0")
If you use 8 bits, the character spacing will be 3 bits.
The load pulse may be applied to the parallel to serial converter 8 in synchronization with the switching of the selector 7. Parallel→
The clock of the serial converter 8 may be a display clock, for example 7.159090 Hz. This frequency is the output of the crystal oscillator ₂ divided by 1/2. Erase switch 1
3 is not set, the output of the erase switch 13 is at a high level, the AND gate 12 is conductive, and the output of the parallel to serial converter 8, that is, the character pattern signal, is sent to the mixing circuits 9R, 9G, and 9B. The transmitted R, G, and B signals, in this case, are mixed with the crosshatch signal and displayed as "31.50" as shown in FIG. The above-mentioned "31.53" may be displayed.
These processes are performed in the conversion ROM 5. If the number display "31.50" is a nuisance when adjusting the convergence, just operate the erase switch 13 and set the output of 13 to a low level "L" to shut off the AND gate 12, and the display of "31.50" as shown in Figure 3. disappears.

In this way, the frequency can be displayed in response to changes in the input horizontal synchronization signal.

Effects of the Invention As explained above, the display device of the present invention can trace the cable to the signal source and check the output state of the signal source even when there are several input synchronization signal frequencies and the frequencies are close to each other. You can tell the frequency without acknowledging it. Therefore, it is possible to avoid a situation where an erroneous write is performed when a dynamic focus correction value is written to the EEPROM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the display device of the present invention, FIG. 2 is a block diagram for explaining the operation of FIG. 1, FIG. 3 is a diagram for explaining the display state, and FIG. It is a main part waveform diagram. DESCRIPTION OF SYMBOLS 1... Pulse shaping circuit, 2... Crystal oscillator (reference time signal generator), 3... Counter, 4... Latch memory, 5... Conversion ROM, 6... Character generator, 7... Selector, 8... ...Ordinary to direct converter, 9R, 9G, 9B...Mixer, 10R, 1
0G, 10B...Video output circuit, 11R, 11
G, 11B... Braun tube, 12... AND gate, 13... Erase switch.

Claims (1)

[Claims] 1. A crosshatch or dot pattern signal generator for convergence adjustment and a deflection circuit synchronized with horizontal and/or vertical external synchronizing signals of two or more different frequencies are provided, and the external synchronizing signal is A display device configured to measure a frequency using a reference time signal generator and a counter, and display the measured frequency on a part of a convergence adjustment screen via a character generator. 2. The reference signal generator is configured with a crystal oscillator with a sufficiently higher frequency than the input synchronization signal, and the counter is reset by the input synchronization signal or a pulse synchronized with this synchronization signal while dividing the frequency of the output of the crystal oscillator. Claim 1 is characterized in that the count value of the counter is recorded in a latch memory, and the contents of the latch memory are converted into numbers via a character generator and displayed. Display device.