JPS62198219A - Synchronizing type counter circuit - Google Patents

Abstract

PURPOSE:To attain a high speed counter circuit by using a counting circuit employing partly a carry look-ahead circuit in common. CONSTITUTION:A NAND circuit NANDn1 uses signals C0, Cn-1 to generate the inversion of a carry signal to the n-th stage. The signal and an inverted output signal Qn of a D flip-flop D FFn are inputted to an exclusive OR circuit EORn and its output is inputted to the D flip-flop DEFn to form a unit block circuit of the counter. On the other hand, in figure, a NOR circuit NOR(N+1)1 uses a common inverted carry signal, the inverse of C0 and the n-stage carry enable signal, the inverse of Cn to generate a carry signal to the (n+1)th state. The signal and an output signal Qn+1 of the D flip-flop DEFn+1 are inputted to an exclusive OR circuit EORn+1, its output is inputted to the D flip-flop DFFn+1 to form the unit block circuit of the other kind of counter. In connecting the counters above, number of gates passing the carry signal is reduced and the transfer speed is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in a synchronous counter circuit constituted by a logic circuit.

2. Description of the Related Art Conventional synchronous counter circuits include a sequential carry circuit type and a carry look ahead circuit type.

The synchronous counter circuit using the sequential carry circuit method is
As shown in the figure, it is constructed using a plurality of unit element circuits including a NAND circuit 1, an inverter circuit 2, an exclusive OR circuit 3, and a D-type flip-flop 4. φ is a common clock signal, φON is a clock input, D is a data input, Q is an output, C is a carry signal from the previous stage, and Cm is a carry signal to the next stage.

A synchronous counter circuit using a carry look-ahead circuit is composed of unit element circuits as shown in FIG. The unit element circuits that perform the same actions as those in FIG. The output of the D-type flip-flop 4, Q0 to Q, is the output of the D-type flip-flop 4 of each stage.

The problem that the invention aims to solve Such a conventional configuration has the following problems.

The circuit configuration shown in Figure 5 is a simple circuit configuration because the same circuit is repeated even in a multi-stage configuration, and it is difficult to design and
It has the advantage of being easy to convert into FG. However, the carry (lj
Since the signal is incremented in each stage sequentially, the propagation of the signal becomes slow, which poses a problem when used as a high-speed counter circuit.

Even if the circuit configuration in Figure 6 is a multi-stage configuration, the carry signal of each stage is constructed by a look-ahead circuit. It is generated by two gates: 1 and inverter 2. Therefore, the propagation of the carry signal is fast, which is advantageous for configuring a high-speed counter, but in a multi-stage configuration, the carry signal generation circuit in each stage becomes larger, and at the same time, the scale of one circuit becomes larger.
The ratio of the repeat circuit section to the carry signal generation circuit section decreases, increasing the number of problems that are difficult to design and integrate.

The above problems can be summarized as follows.

In a counter that uses sequential carry signals, the propagation path of the one-carry signal becomes long, so it is difficult to increase the speed with a multi-stage configuration.
Although it is possible to increase the speed, the circuit scale increases rapidly as the multi-stage configuration is adopted, making design and integration difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous counter circuit that can increase speed even in a multi-stage configuration, is easy to design, and is suitable for integration.

Means for Solving the Problems The synchronous counter circuit of the present invention has a common clock (Fi) and a common carry signal of forward rotation and one inversion, and has The normal carry signal and the carry permission signal generated at the (n-1)th stage are logically ANDed, and this logical product signal is used in exclusive logic with the inverted output of the D-type flip-flop at the nth stage. Combine the signals synthesized by the sum as input.

The normal output of the n-th D-type flip-flop and the (n
-1) means for generating an AND signal with a carry permission signal generated in the next stage as a carry permission signal to the next stage;
+1) The inverted carry signal and the carry permission signal generated in the n-th stage are logically ORed for the D-type flip-flop in the (n+1)th stage, and this ORed signal and the D-type flip-flop in the (n+1)th stage are
A signal synthesized by exclusive OR with the normal output of the D-type flip-flop is input and coupled to the inverted output of the (n+1)th D-type flip-flop and the carry permission signal generated in the n-th stage. ) and means for generating an OR signal with the Mj increase permission signal to the subsequent stage.

The device is characterized in that the unit components of the 11th stage and the (+1)th stage are coupled in multiple stages using the common clock signal.

According to this configuration, the carry signal generation circuit of the component unit is configured by an AND generation circuit of a common carry signal and a carry permission signal generated by a sequential carry permission signal generation circuit, and the common carry signal is inverted. A common carry signal can be generated for higher speeds by alternately using two types of configurations, each consisting of a logical sum generation circuit of a signal and an inverted signal of the carry permission signal generated by a sequential carry permission signal generation circuit. This is achieved by connecting a carry look-ahead circuit to the circuit that performs this, and slowing down the calculation cycle of the repeating circuit.

In the present invention, synchronous counting is realized by generating a carry signal using a common carry signal and a carry permission signal.

Furthermore, each structural unit can sequentially send a carry permission signal to the next stage.

Embodiments Hereinafter, embodiments of the present invention will be explained based on FIGS. 1 to 4.

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams of each unit element of the main part. C0 is a common normal carry signal, C0 is an inverted carry signal of the common carry signal, and C,1 is a carry permission signal generated in the (, n -1)th stage unit element circuit, dτ is the inverted signal of the carry permission signal generated in the n-th stage unit element circuit, Cn
+1 indicates a carry permission signal generated in the (n+1)th stage unit element circuit.

In FIG. 2, a NAND circuit NANDTlxG:ic.

and Cn-□ generate an inverted signal of the carry signal for the nth stage. This signal and the D-type flip-flop DFFn
The inverted output signal stone is used as an input to an exclusive OR circuit EORn, and its output is used as an input to a D-type flip-flop DFFn, thereby forming a constituent unit circuit of a counter.

On the other hand, in FIG. 3, the NOR circuit 73 NOR(n+,) generates a carry signal for the (n+1)th stage using a common inverted carry signal stone and a carry permission signal stone of n1Q11. This signal and the output signal Q n + z of the D-type flip-flop D F F n + m are connected to an exclusive OR circuit EOR□1.
and its output is a D-type flip-flop OF
By inputting 11+, it becomes a constituent unit circuit of another type of counter. Also, the NAND circuit NAND in Figure 2
□ inputs the carry permission signal Cn-4 at the (n-1)th stage and the output Qn of the D-type flip-flop DFFn, and
Generates an inverted signal - of the +1st stage carry permission signal. On the other hand, the NOR circuit NOR(n+u)Z in FIG.
, and generates a carry permission signal for the (n+2) stage.

FIG. 1 is a diagram showing the n-th to n+3-th stages of a counter circuit in which the two types of unit circuits shown in FIGS. 2 and 3 are alternately arranged.

2. As shown in Figure 1. By connecting the counter shown in Figure 3, a carry permission signal or an inverted signal is generated in sequence at one gate of a NAND circuit or NOR circuit and used as is. , the number of gates through which the carry signal passes is reduced, and the transmission speed can be increased.

FIG. 4 is a diagram showing an example of generation portions of a common carry signal and its inverted signal in another embodiment of the present invention;
FFO~DFF3 are D-type flip-flop circuits, EOR
, ~E OR, is an exclusive OR circuit, NAND, ,NA
ND, , NAND, , NAND32 is a NAND circuit, I
NV is an inverter circuit.

In FIG. 4, a D-type flip-flop DFF.

The two stages with the DFF are composed of a counter circuit using a conventional carry look-ahead circuit. Here, CE is a count permission signal. This second stage NAND circuit NAND□
and inverter INV1 generate a common carry signal C6 and an inverted signal of 7.

Since each carry signal C6 and C0 is generated by a two-stage counter, the common clock operates at 22 times the cycle, that is, 4 times the period. Therefore, by configuring the third and subsequent stages in Figure 4 as shown in Figure 1, the multi-stage counter circuit can effectively be made about 4 times faster than a counter circuit using a sequential carry signal generation circuit. be able to. In the circuit shown in FIG. 4, the counter circuit using the carry look-ahead circuit has two stages, but it can generally be made into i stages. At this time, C1° and C have a period of 21 times, and as a counter circuit, the period is 21 times.
It is possible to increase the speed by about 1 times.

Although the above embodiment has been described using an example of an additive type synchronous counter circuit, it is also possible to configure a subtractive type synchronous counter circuit in which the output signal of a D-type flip-flop is inverted.

As described in the detailed description of the invention, the synchronous counter circuit of the present invention partially uses a counter circuit that uses a carry look-ahead circuit.
It becomes possible to realize a high-speed counter circuit. Further, since the main part of this circuit is constructed using repeating circuits of two types of circuits, the circuit construction can be easily designed and integrated.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a synchronous counter circuit according to an embodiment of the present invention,
FIGS. 2 and 3 are circuit diagrams of each of the seven circuits of two types of synchronous counters according to the present invention. Fig. 4 is a circuit diagram of another embodiment of the present invention, Fig. 5 is a structural unit circuit diagram of a synchronous counter circuit using a conventional sequential carry signal generation circuit, and Fig. 6 is a circuit diagram using a carry look ahead circuit. FIG. 2 is a circuit diagram of a first stage of a synchronous counter circuit; c.1. cTI, c,,1. c3... Carry permission signal, c. ...Common carry signal, EORn, EORn+,,E
OIku. , EORl, EOR2, EOR, . . . exclusive OR circuit, NANDII, NANDy12. NAN
Dcn+t)xtNAND(net)2+ NA, ND
ixt NANDiz"' NAND circuit, INV, --...
Inverter circuit, NOR(1141)th N0R(n+1
),, N0RC,+3),, N0R(n+3). ...Nor circuit, D F F n , D F F ne
t, DFFnet-DFFn, 3. DF[
”,, DFF , , DFF,, D
FF. -D type flip-flop circuit, Q n v Q net
+Q net pQn+,,Q,,Q,,Q,,Q
Outputs of 3-D flip-flops, D n, Dll,
,, Dn, , Dn, 3. D. D,, D2. D, . . . input of D-type flip-flop, ψn, φn+1. φ. Ya 2. φn+3. φ. ,φ0
．． φ2. φ3...D-type flip-flop clock input, φ...Common clock signal agent Yoshihiro MorimotoFigure 2Figure 3Figure 5Figure 4

Claims (1)

[Claims] 1. It has a common clock signal and common forward and inverted carry signals, and is generated at the (n-1)th stage with the normal carry signal for the n-th D-type flip-flop. The carry permission signal is ANDed, and the signal synthesized by the exclusive OR of this ANDed signal and the inverted output of the nth D-type flip-flop is input and coupled, and the means for generating an AND signal of the normal output of the flip-flop and the carry permission signal generated at the (n-1)th stage as a carry permission signal to the next stage; For the D-type flip-flop, the inverted carry signal and the carry permission signal generated at the nth stage are logically summed, and this logical sum signal and the positive signal of the (n+1)th stage D-type flip-flop are A signal synthesized by exclusive OR with the inverted output is input and coupled, and an OR signal is generated between the inverted output of the D-type flip-flop of the (n+1)th stage and the carry permission signal generated in the nth stage. a synchronous counter circuit comprising means for generating a carry permission signal to a subsequent stage, and in which each of the unit components of the nth stage and the (n+1)th stage are coupled in multiple stages using the common clock signal.