JPS62198165A - Schottky junction type field effect transistor - Google Patents

Abstract

PURPOSE:To enhance the reliability and screening test yield of a Schottky junction type field effect transistor by forming a cutout at part of an active layer on the periphery of a source electrode near a gate power supplying point in a GaAs FET to alleviate a current concentration generated at the end of the source electrode even if an excess surge is input. CONSTITUTION:A drain electrode 104d and a source electrode 104s ohmically bonded on an active layer 103 formed through a buffer layer 102 are formed on a semi-insulating semiconductor substrate 101. A gate electrode 104g ohmically bonded between the electrodes 104d and 104s is formed. After a hole is opened by a photoresist 105 in an SiO2 layer 105 near a gate power supplying point 114g around the electrode 104s by photoetching, with the photoresist 106 as a mask it is etched to remove part of the layer 103 to form a cutout 11. A small signal GaAs FET having a Schottky junction at the source electrode has excellent surge resistance characteristic.

Description

[Detailed description of the invention] [Industrial field] This invention is a Schottky junction type IT! ! It concerns the structure of a V-effect transistor.

[Conventional technology]

In recent years, potassium arsenide Schottky junction sliding current JF1-effect transistors (hereinafter referred to as GaAsFETs) have been in trouble, and as their range of use has expanded, improvements in their breakdown strength have become increasingly important.0Figure 6 shows Ga As
F E '1' is usually a semi-insulating substrate [0] with a high purity GaAs buffer layer [02] on it and is n-type with a carrier concentration of ~3 XI O"cm-".

Using a wafer on which active layer 03 with a thickness of 0.5 μm and 8 degrees was epitaxially grown, gold germanium/nickel was scraped onto the active layer 103 to form source and drain electrodes, and heat treatment was performed in a hydrogen furnace. A source To electrode which becomes an ohmic contact by applying the same voltage to the source To electrode] 04g and a drain electrode 104d are formed. Furthermore, an aluminum gate electrode &104g is formed on the 51021m105 between the two chamber electrodes using fine photoetching technology.
Bt) Used as a small signal around Hz diameter (jaAsi
'ET's inter-electrode dimensions are determined to ensure its frequency stability.
North. 4 μm between drain electrodes 1 gate, source II
The distance between electrodes is 1 μm, and the gate length is 0.3 to 0.5 μm, which is an extremely small value.A chip with this structure can be incorporated into a small package to meet the requirements for 0aAsF'ET. In order to ensure high reliability, the product is manufactured after rigorous screening has been carried out to completely eliminate any latent defects.

[Problem that the invention seeks to solve]

By the way, even products that have gone through such a rigorous processing process can sometimes experience failures that lead to destruction. If we examine these defective products in detail, in most cases, burnout fffl106 was observed between the gate and source electrodes near the gate and source electrodes, indicating that the failure was caused by a voltage surge. Presumed.

The cause of the soft soil is the North in terms of plane. Drain 111 pole]
'04s,]]0d or the gate electrode 104g are formed at equal intervals between the gate electrode 104g and the gate terminal 124g'l, so a surge exceeding the gate withstand voltage may occur between the gate electrode 104g and the gate electrode 104g. When the electric field is applied to the pole, a two-ironemental breakdown (amentary Bre
akdown (hereinafter abbreviated as destruction) occurs, followed by /
This caused the FET to be destroyed due to the generation of iodobas and eventual burnout.

To explain this with reference to FIG. 7, since the current flows only on the very surface of the active layer 103, current concentration tends to occur at the source end, and this also causes filamentary breakdown at the source end opposite to the gale electrode. It was also inside the dormitory. In order to prevent this, there is a method of rounding the corners of the source tLh 104 s to weaken the electric field concentration.
Methods such as making the 4S ohmic junction penetrate deep into the active layer 03 have also been adopted, but none of these methods have yielded effective results.

Like soft soil, a small signal U a that touches the real parent of high-frequency physical properties
A s FET had a problem as it was 2 weak against surge.

Therefore, in view of the above-mentioned conventional interpolation points, it is an object of the present invention to provide an improved field-effect transistor supplement. The configuration will be explained using FIG. 1 (tag, fb) corresponding to the embodiment. In this invention, the drain electrode]04 (1, the source is connected to the active layer 103 which is ohmically connected to the active layer 103 formed on the surface of the semi-insulating semi-integrated substrate 101 via the buffer layer [02]).
A Schottky junction field effect transistor is formed in which a Schottky junction field effect transistor 04S is provided, and a Schottky junction gate electrode 104g is provided between these two electrodes, and the gate' of this Schottky junction field effect transistor is located close to another power supply point 114g. By removing a part of the active layer around the source electrode] 04S, a cutout 1] is provided to form a 4111 structure. In a junction field effect transistor, the gate electrode 104
When a surge exceeding G)% is applied to g, the potential is lowest near the gate feeding point 114g, and the gate feeding point where the electric field is concentrated is the source electrode near the point 114g]
Since a notch 11 is provided between the corner of 04S,
The current flowing through these two electrodes c]o4g, 1o4s) detours through the notch]] as shown in Figure 2, so the current flowing through both electrodes (104g
, 104s) is less likely to occur.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention (C), which is an embodiment of the present invention, in which parts that are the same as the conventional one are given the same reference numerals as the conventional one, and their explanations are omitted.
In the aAsFE'l', a notch 11 is provided in a portion of the shaving area of the source electrode 104S that is close to the power feeding point 114g of the gate electrode. This is explained by (e).

High-purity GaA on the semi-insulating substrate ( ) 1 as before
na! via the s-balance layer 102! ! A wafer on which an active layer 103 having a carrier concentration of 1 to 3×10 cIn and a thickness of 0.5 μm was epitaxially grown was prepared.
Sin! Forming layer 105 (FIG. 3 ta)
)Next, holes were made in the 5i01 layer]05 by photoetching in the regions where the source and drain ti were to be formed, gold-germanium alloy/nickel was deposited, unnecessary parts were removed, and the layer was heated in a hydrogen furnace for 400mm. Heat treatment is performed for 0.5 minutes to obtain ohmic contact (WXB diagram (b)).Next,
In order to form the gate electrode 104g, an opening is formed in the 5i01 layer 105 by photoetching, and then 5OOOL of aluminum is vapor deposited and unnecessary portions are removed by a lift-off method. Then, by photoetching, holes are formed in the 5j01 layer 05 near the gate power supply point 4g around the source electrode 04S using a photoresist 106, and the active layer is etched using the photoresist 106 as a mask. A part of the source electrode 1 is removed to form a notch 1 (FIG. 3(c), (d)).
04S and the drain for bonding to the pole 104d, unnecessary parts of titanium, platinum, and gold were removed by a lift-off method to form a metal layer 07, and a semi-insulating substrate 1 was roughly formed.
A gold layer with a thickness of 2000X]08 is formed on the back side of 01,
Then, die-cutting is performed (a jaAsFET chip is obtained (Fig. 3 (?)).
It was confirmed in the following manner that the aAsFET has better anti-surge characteristics than those of conventional shapes. That is, a conventional GaAsFE'l' chip and the same chip of the present invention were each housed in an envelope, and an n-electrode breakdown strength measurement test was conducted using the electric circuit shown in FIG. The capacitor (Q) in this electric circuit had a capacitance of 200 pF, which is the standard value.The GaAs used in the test
In the FET, the notch 11 has a width of 0.5 μm,
They were formed to have a length of 50 μm and a depth of 0.2 μm, and the gate widths were set to 400 μm and 800 μm. The results of the above test are shown in Figure 5 regarding the correlation between gate width and electrostatic breakdown energy.
The conventional product is shown with a black circle and a broken line, and the present invention is shown with a white circle and a solid line.0 From the results shown in this figure, it is clear that the product of the present invention is about three times more resistant to electrostatic damage, and is intended for current dispersion. Although the effectiveness has been confirmed, in the present invention, a notch] is provided in a part of the periphery of the source electrode 104S close to the power feeding point 114g of the gate electrode, but a If it is formed in all areas, the series resistance value between the gate electrode 104g and the source electrode 1045 will increase, which will cause an increase in the noise figure and a decrease in the gain, which is not a good idea. Experimentally, gate electrode 1
If the length of the notch 11 facing the gate electrode 114g is a portion close to the power feeding point 114g of the gate electrode, the gate electrode 1
The result was obtained that it did not affect the fluctuation of the series resistance value between the source electrode 104g and the source electrode 104s, and did not contribute to the above deterioration factor.

〔Effect of the invention〕

As described above, according to the present invention, GaAsF E
By providing a notch in a part of the active layer around the source electrode near the gate power supply point where damage due to surges is likely to occur in 'I', even if there is an excessive surge input,
The concentration of tg generated at the end of the source electrode can be alleviated, and burnout between the gate electrode and the source electrode does not occur.
GaAsF with high reliability and screening test yield
There are significant advantages that ET can offer0

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention (JaAsFET).
Figure a is a top view, Figure a is a cross-sectional view taken along the line A--A in Figure A, and Figure 2 is a diagram showing the area between the gate and source electrodes of the GaAsFET according to the present invention. Cross-sectional view showing MTh, Figure 3 t
a+ to (e) are cross-sectional views showing the manufacturing method of GaAsF' ET of one embodiment in the order of steps, and FIG.
The electrical circuit diagram used to measure the electrostatic breakdown strength of ``ET'', Figure 5 is a diagram showing the electrostatic breakdown strength test results of )' Figure a showing Ji' is a top view, it is a sectional view taken along A-AIli! of figure a, and Figure 7 is a sectional view showing the current between the gate and source of pE, rl+. 11... Notch, 10]... Semi-insulating substrate, 103...
...Active 1t5.104g...Gate electrode +]
04s...Source electrode, ]04d...Drain electrode, 114g...Gate feed point. Agent Patent Attorney Nori Kei Yudo Takehana Kikuka) $2 round, 3 figures (GaiLwrdd) Lj figure/24 #ge;

Claims (1)

[Scope of Claims] A Schottky junction field effect transistor comprising a source electrode and a drain electrode which are ohmically connected to an active layer on a semi-insulating semiconductor substrate, and a gate electrode which is connected to a Schottky junction between these two electrodes, comprising: A Schottky junction field effect transistor, characterized in that a part of the active layer around the source electrode close to a power feeding point of a gate electrode is removed.