JP2002043586A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve durability and reliability by preventing a concentration of a surge current. SOLUTION: In a semiconductor device, an n-type region 3 is formed on a surface of a silicon support board via a dielectric film 2, and an n-type high concentration buried region 5 is formed in contact with the film 2 on a bottom of the region 3. A frame-like trench groove type insulating region 4 contacted with the film 2 is formed on the region 3. A p-type region 6 is formed in contact with an n-type high concentration buried region 5 on an inside n-type region 3A in the region 4, and a p-type high concentration region 7 is formed on the region 6. An n-type high concentration region 8 is provided in isolation from the region 6 on the region 3A, and a trench groove type insulating region 9 contacted with a dielectric film is formed between the region 8 and the region 6. The region 7 is connected to a low potential terminal, the region 8 is connected to an input terminal, and a protective diode is formed therebetween.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which a semiconductor region is formed on a surface (main surface) of a semiconductor support substrate via a dielectric.

[0002]

2. Description of the Related Art In general, as a semiconductor device, there is known a semiconductor device in which a silicon region made of p-type silicon or n-type silicon is formed on a silicon substrate as a semiconductor support substrate via a dielectric such as a silicon oxide film. (For example, Japanese Patent Application Laid-Open No. 7-313424).

[0003] In such a conventional semiconductor device, a MOS device is operated due to an excessive current due to static electricity or a surge voltage.
In order to prevent a transistor from being destroyed, a diode capable of flowing a large current is formed. This diode employs a planar structure in which an anode side high concentration diffusion region and a cathode side high concentration diffusion region are formed on the surface of a silicon region. The cathode-side high-concentration diffusion region of the diode is disposed, for example, so as to surround the outer periphery of the anode-side high-concentration diffusion region. In addition, the anode-side high-concentration diffusion region and the cathode-side high-concentration diffusion region are electrically connected to each other through polycrystalline silicon provided on their bottom surfaces.

[0004]

By the way, the semiconductor device according to the prior art described above employs a planar structure in which both the high concentration diffusion region on the anode side and the high concentration diffusion region on the cathode side of the diode are formed on the surface of the silicon region. are doing. For this reason, when a surge is applied, the surge current flows through the shortest path with the minimum resistance.
It is concentrated on the outer peripheral end side of the anode side high concentration diffusion region forming the end of the n-junction. As a result, a surge current that becomes a large current flows intensively at the end of the minute pn junction, which causes a problem that the diode is easily damaged.

In a diode having a planar structure, it is necessary to increase the distance between the anode and the cathode and increase the resistance component in order to increase the breakdown strength. But,
When the magnitude of the surge current is limited in this way, the surge current may flow into the internal circuit and damage the internal circuit.

Further, in the conventional semiconductor device,
Since a dielectric is provided between the anode-side high-concentration diffusion region and the cathode-side high-concentration diffusion region, it is necessary to add a step for forming the dielectric, and there is a problem that the manufacturing time becomes long.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a semiconductor device capable of preventing surge current concentration and improving durability and reliability. is there.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor region of a second conductivity type formed on a main surface of a semiconductor support substrate via a dielectric. Forming a high-concentration buried region of the second conductivity type on the bottom surface of the semiconductor region of the second conductivity type, and forming a semiconductor region of the first conductivity type on the main surface of the semiconductor region of the second conductivity type; The semiconductor region of the first conductivity type is provided so as to be in contact with the high concentration buried region, and the high concentration region of the first conductivity type is provided on the main surface of the semiconductor region of the first conductivity type. A concentration region provided between the high-concentration region of the first conductivity type and the high-concentration region of the second conductivity type; Forming a groove-type insulating region, wherein the high-concentration region of the first conductivity type and the high-concentration region of the second conductivity type are formed. Input terminal either one of the degree region, the output terminal, the high potential terminal, as well as connected to one of terminals of a low potential terminal, and configured to connect the other to one of the terminals of the remainder.

With this configuration, a first diode can be formed between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, and the semiconductor region of the first conductivity type can be formed. A second diode can be formed between the second conductive type and the high-concentration buried region of the second conductivity type, and these two diodes can function as protection diodes. At this time, the high concentration buried region of the second conductivity type has a higher impurity concentration than the semiconductor region of the second conductivity type, and the semiconductor region of the first conductivity type and the high concentration buried region of the second conductivity type have a small curvature. Since the contact state can be established, the breakdown voltage of the second diode can be lower than that of the first diode.

Further, since a trench-type insulating region is formed between the semiconductor region of the first conductivity type and the high-concentration region of the second conductivity type, a current flowing between these regions bypasses the trench-type insulating region. And flow Therefore, the first current path from the first diode to the high-concentration region of the second conductivity type through the semiconductor region of the second conductivity type;
Each of the second current paths extending from the high-concentration buried region of the conductivity type to the high-concentration region of the second conductivity type becomes longer by an amount that bypasses the trench-type insulating region. Further, since the high-concentration buried region of the second conductivity type has a higher impurity concentration than the semiconductor region of the second conductivity type, the longer the first and second current paths, the smaller the parasitic resistance of the first current path. It is significantly larger than the parasitic resistance of the second current path.

As a result, even when the positive or negative overvoltage surge is applied, most of the surge current can flow to the second diode having a low breakdown voltage and a small parasitic resistance. The second diode can be formed by bringing the semiconductor region of the first conductivity type into high-concentration buried region of the second conductivity type by surface contact.
It is possible to prevent surge current from concentrating on a minute end.

A second aspect of the present invention is that a pad electrode is provided on the main surface of the high-concentration region of the first conductivity type, and the high-concentration region of the first conductivity type is connected to the pad electrode.

Thus, a diode can be formed below the pad electrode, so that a high degree of integration can be maintained without impairing the degree of integration of the semiconductor device. Also,
Since the surge current flows between the pad electrode and the high-concentration region of the first conductivity type that are in surface contact with each other, the surge current can flow substantially uniformly throughout the high-concentration region of the first conductivity type.
As a result, a surge current with a more uniform current density can flow through the pn junction of the diode formed between the high-concentration region of the first conductivity type and the high-concentration buried region of the second conductivity type. As a result, the withstand capacity of the diode can be increased.

Further, according to a third aspect of the present invention, the semiconductor region of the second conductivity type is located on the side opposite to the high concentration region of the one second conductivity type with the high concentration region of the first conductivity type interposed therebetween. A high concentration region of another second conductivity type is provided on the main surface, and the high concentration region of the second conductivity type is located between the high concentration region of the first conductivity type and the high concentration region of the other second conductivity type. On the main surface of the semiconductor region, another trench-shaped insulating region is formed so as to be in contact with the dielectric and in a U-shape with the one trench-shaped insulating region,
Another high conductivity region of the second conductivity type is connected to the high concentration region of the one second conductivity type.

Thus, since two high-concentration regions of the second conductivity type are provided, the area of the entire high-concentration region of the second conductivity type is reduced as compared with the case where a single high-concentration region of the second conductivity type is provided. Can be bigger. Therefore, the first conductive type semiconductor region formed between the first conductive type semiconductor region and the second conductive type semiconductor region is formed.
And the second diode formed between the semiconductor region of the first conductivity type and the high-concentration buried region of the second conductivity type have small resistance components. Therefore, the impedance of the entire first and second diodes is reduced, and a potential increase such as an input terminal voltage at the time of applying a surge can be more reliably suppressed, and a surge current injected into an internal circuit can be suppressed. .

Further, since a U-shaped trench groove type insulating region is provided between the high-concentration region of the first conductivity type and the two high-concentration regions of the second conductivity type, respectively, the high-concentration region of the first conductivity type is provided. A first current path from the region through the semiconductor region of the second conductivity type to the high-concentration region of the second conductivity type, from the high-concentration region of the first conductivity type to the high-concentration buried region of the second conductivity type; Each of the second current paths leading to the high-concentration region is much longer than that of the U-shaped trench-shaped insulating region. For this reason, the resistance difference between the parasitic resistance of the first current path and the parasitic resistance of the second current path can be increased, and the parasitic resistance of the first current path is larger than the parasitic resistance of the second current path. It can be even larger. Therefore, most of the surge current flows through the diode formed between the high-concentration region of the first conductivity type and the high-concentration buried region of the second conductivity type, so that damage to the semiconductor device can be prevented.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS.

First, FIGS. 1 to 3 show a first embodiment of the present invention. In the drawings, reference numeral 1 denotes a silicon support substrate made of, for example, a silicon material. A dielectric film 2 such as an oxide film is provided, and an n-type region 3 made of n-type silicon is formed via the dielectric film 2. As a result, the silicon support substrate 1, the dielectric film 2, and the n-type region 3 are SOI (Sili)
The n-type region 3 has a low concentration (for example, about 10 ¹⁵ to 10 ¹⁶ cm ⁻³ ) of an impurity such as arsenic in a single-crystal silicon material while having a con-on-insulator structure.
Formed by adding

Reference numeral 4 denotes a frame-shaped trench-groove-type insulating region provided in the n-type region 3. The frame-shaped trench-groove-type insulating region 4 is formed in a substantially rectangular frame shape. Has reached. The frame-shaped trench-type insulating region 4 divides the n-type region 3 into an inner n-type region 3A located inside and an outer n-type region 3B located outside, and separates them into an insulating state. . In the inner n-type region 3A, a protection diode including a p-type region 6 described later is formed, and in the outer n-type region 3B, for example, an internal circuit (not shown) for performing various processes is formed. ing.

Reference numeral 5 denotes n provided on the entire bottom surface of the n-type region 3.
The n-type high-concentration buried region 5 is:
It is provided between the n-type region 3 and the dielectric film 2 and is formed by adding an impurity such as arsenic at a high concentration (for example, about 10 ¹⁸ to 10 ¹⁹ cm ⁻³ ). Further, the n-type high-concentration buried region 5 is also divided into the frame-shaped trench-groove-type insulating region 4, and the inside n-type high-concentration buried region 5 A located inside the frame-shaped trench-groove-type insulating region 4 and the outside n located outside. It is isolated from the high-concentration buried region 5B in an insulating state.

Reference numeral 6 denotes a p-type region provided on the surface of the inner n-type region 3A. The p-type region 6 has a substantially quadrangular shape and is disposed at the center of the inner n-type region 3A, and has a bottom surface which corresponds to the inner n-type region 3A. Is in surface contact with the high-concentration buried region 5A. The p-type region 6 is formed by diffusing impurities such as boron to a low concentration (for example, about 10 ¹⁵ to 10 ¹⁶ cm ⁻³ ) from the surface side of the inner n-type area 3A.

Reference numeral 7 denotes a p-type high-concentration region provided on the surface of the p-type region 6. The p-type high-concentration region 7 has a substantially square shape and is arranged at the center of the p-type region 6. The p-type high concentration region 7 is formed by diffusing impurities such as boron into the p-type region 6 at a high concentration. The p-type high concentration region 7 is connected to a low potential terminal such as a ground terminal.

Reference numeral 8 denotes an n-type high-concentration region provided on the surface of the inner n-type region 3A. The n-type high-concentration region 8 is located substantially at the center with respect to one side of the substantially square p-type region 6. Located, p
It is arranged between the p-type region 6 and the frame-shaped trench-groove type insulating region 4 so as to be spaced from the p-type region 6. The n-type high-concentration region 8 is formed by diffusing impurities such as arsenic into the inner n-type region 3A at a high concentration. The n-type high concentration region 8 is connected to, for example, an input terminal as a terminal different from the low potential terminal.

Reference numeral 9 denotes a trench-type insulating region provided between the p-type region 6 and the n-type high-concentration region 8 and provided on the surface of the inner n-type region 3A. It is formed in a straight line extending substantially parallel to one side of the p-type region 6, and has a length dimension longer than one side of the p-type region 6. Although the trench groove type insulating region 9 has its bottom portion in contact with the dielectric film 2 over the entire length, both ends extending linearly do not contact the frame trench type insulating region 4, A gap is formed between the region 4.

The semiconductor device according to the present embodiment has the above-described configuration, and its operation will now be described.

First, since the p-type region 6 is provided on the center side of the inner n-type region 3A, the first diode 10 of a pn junction is formed on the outer peripheral side. Also, p
Since the bottom surface of the p-type region 6 is almost entirely in contact with the inner n-type high-concentration buried region 5A, the second diode 11 is also formed on the bottom surface side of the p-type region 6 by a pn junction. Therefore, these diodes 10 and 11 function as protection diodes of the semiconductor device.

Here, the impurity concentration of the inner n-type high concentration buried region 5A is set higher than that of the inner n-type region 3A. For this reason, the breakdown voltage of the second diode 11 is set lower than that of the first diode 10.

Further, the resistance component of the second diode 11 has a smaller value than the resistance component of the first diode 10 for the following reason. That is, between the p-type region 6 and the n-type high-concentration region 8, a first current path passing through the inner n-type region 3 </ b> A from the pn junction on the cathode side of the first diode 10 and the second diode 10 And a second current path from the pn junction to the inner n-type high-concentration buried region 5A on the cathode side. Here, since the trench type insulating region 9 was formed between the p-type region 6 and the n-type high concentration region 8,
The current flowing between them bypasses the trench insulating region 9 and flows through both ends in the longitudinal direction of the trench insulating region 9. Therefore, the first and second current paths are:
Compared to the case where the trench groove type insulating region 9 is not provided, the length is longer by an amount corresponding to the length dimension of the trench groove type insulating region 9.
The impurity concentration of the inner n-type high concentration buried region 5A is 1
0 ¹⁸ to 10 ¹⁹ cm ⁻³ , which is higher than the impurity concentration of the inner n-type region 3A of 10 ¹⁵ to 10 ¹⁶ cm ^−3, so that the second current path (the cathode of the second diode 11) The parasitic resistance of the first current path (the cathode side of the first diode 10) is about 10 ⁻³ times as large as the parasitic resistance of the first current path (the cathode side of the first diode 10). Therefore, as the first and second current paths become longer, the parasitic resistance component of the second diode 11 becomes significantly smaller than the parasitic resistance component of the first diode 10.

As a result, when a positive overvoltage surge is applied to the input terminal, most of the surge current flows through the second diode 11 having a low breakdown voltage and a small parasitic resistance. That is, when the surge voltage rises, the first
The second diode 11 breaks down earlier than the diode 10, and most of the current thereafter flows through the second diode 11 having a small parasitic resistance.

Since the pn junction of the second diode 11 is formed between the p-type region 6 and the inner n-type high-concentration buried region 5A, the pn junction of the diode 11 can be regarded as a planar junction. The resistance of the inner n-type high-concentration buried region 5A has a small value. Therefore, the current flowing through the diode 11 (diode current) flows approximately unitarily, and the current density becomes substantially uniform over the entire pn junction. Therefore, since the diode current does not concentrate on a part of the pn junction, damage to the diode can be prevented.

Furthermore, since the parasitic resistance component of the diode 11 itself is small, it is possible to suppress an increase in the input terminal voltage due to a surge, and to prevent a surge current from flowing into an internal circuit connected to the input terminal. Therefore, damage to the internal circuit can be prevented.

Further, since most of the surge current can flow from the diode 11 through the inner n-type high-concentration buried region 5A, the surge current can be suppressed from increasing, and the p-type region 6 and the n-type high-concentration region can be suppressed. It is not necessary to increase the breakdown strength of the diode by increasing the distance between the diodes. Therefore, a high degree of integration can be maintained without impairing the degree of integration of the semiconductor device.

Further, since the trench type insulating region 9 is configured to be in contact with the dielectric film 2 in the same manner as the frame type trench type insulating region 4, the trench type insulating region 9 is divided into the frame type trench type insulating region 4. At the same time, it can be processed and formed.
For this reason, it is not necessary to separately provide a process for processing the trench-shaped insulating region 9 during the manufacture of the semiconductor device, so that the manufacturing time can be reduced as compared with the conventional technology that requires an additional processing step, and Performance can be improved.

Further, the trench type insulating region 9 does not contact the pn junction of the first and second diodes 10 and 11. For this reason, when the pn junction comes into contact with the trench type insulating region 9, no leak current flows along the trench type insulating region 9, so that the rectification characteristics and the like of the diodes 10 and 11 are deteriorated. And high characteristics can be maintained.

On the other hand, when a negative overvoltage surge is applied to the input terminal, the first and second diodes 10 and 11 are forward-biased. At this time, since the resistance component of the second diode 11 is significantly smaller than that of the first diode 10, most of the surge current flows through the diode 11 as in the case where a positive overvoltage surge is applied. . Further, the diode current flowing through the diode 11 flows approximately unitarily and has a substantially uniform current density over the entire pn junction, so that concentration of the diode current can be prevented. As described above, since there is no difference from the case where the positive overvoltage surge is applied except in the direction in which the surge current flows, even if the negative overvoltage surge is applied, the same operation and effect as described above can be obtained. it can.

Thus, in the present embodiment, the p-type region 6
Is provided in surface contact with the inner n-type high-concentration buried region 5A, and a trench-groove-type insulating region 9 is provided between the p-type region 6 (p-type high-concentration region 7) and the n-type high-concentration region 8. Irrespective of whether a positive or negative overvoltage surge is applied, most of the surge current can flow to the second diode 11 having a low breakdown voltage and a small parasitic resistance. At this time, since the diode current does not concentrate on a part of the pn junction, damage to the semiconductor device can be prevented, and reliability and durability can be improved.
Further, since the distance between the p-type region 6 and the n-type high-concentration region 8 can be reduced, a high degree of integration of the semiconductor device can be maintained. Further, various effects such as a reduction in manufacturing time and an improvement in productivity as compared with the related art can be achieved.

Next, FIG. 4 shows a second embodiment of the present invention. The feature of this embodiment is that a pad electrode is provided on the surface of a p-type high-concentration region, That is, it is connected to the pad electrode. In the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Reference numeral 21 denotes an oxide film provided on the surface of the n-type region 3. The oxide film 21 forms a field oxide film, and the surface of the p-type high-concentration region 7 is open.

Reference numeral 22 denotes a pad electrode provided on the surface of the p-type high-concentration region 7. The pad electrode is made of a conductive metal material and is electrically connected to the p-type high-concentration region 7.
Connected to low voltage terminal.

Thus, in the present embodiment, the same operation and effect as in the first embodiment can be obtained. However, in the present embodiment, the diode 1 is located immediately below the pad electrode 22.
Since 1 can be formed, a high degree of integration can be maintained without impairing the degree of integration of the semiconductor device as compared with the case where the pad electrode 22 is provided in another portion.

Since the surge current flows uniformly downward from the pad electrode 22 (in the thickness direction of the n-type region 3), the current inside the p-type region 6 is also uniformly distributed, and the pn junction of the diode 11 The current density of the portion can be made even more uniform.

However, when a large current such as a surge current flows, the resistance of the metal wiring region such as the pad electrode 22 also greatly affects. Here, if the pad electrode 22 is provided at a position other than on the diode 11, the surge current is injected into the p-type high concentration region 7 via the wiring region on the oxide film 21. At this time, since the potential distribution occurs inside the wiring region due to the resistance in the wiring region, the ratio of the surge current flowing from the wiring region to the end (outer peripheral portion) of the p-type high concentration region 7 as the shortest path increases. Therefore, it is difficult to completely uniform the current density flowing through the pn junction of the diode 11.

On the other hand, in the present embodiment, the current density at the pn junction of the diode 11 can be made more nearly uniform, so that either positive or negative overvoltage surge is applied. Therefore, damage to the diode 11 and the like can be hardly caused, and the withstand voltage of the diode 11 can be increased.
Reliability and durability can be further improved.

Next, FIGS. 5 and 6 show a third embodiment of the present invention. The feature of this embodiment is that two n-type regions are provided on the surface of an n-type region with a p-type high-concentration region interposed therebetween. A high-concentration region is provided, and a U-shaped trench-type insulating region is provided between the p-type high-concentration region and each of the n-type high-concentration regions. Note that, in the present embodiment, the first
The same reference numerals are given to the same components as those of the embodiment, and the description thereof will be omitted.

Reference numeral 31 denotes a first n-type high-concentration region provided on the surface of the inner n-type region 3A.
Like the n-type high-concentration region 8 according to the first embodiment, it is formed by diffusing impurities such as arsenic into the inner n-type region 3A at a high concentration. Further, the n-type high concentration region 31
Is located substantially on the center side with respect to one side of the p-type region 6 having a substantially rectangular shape, and is arranged between the p-type region 6 and the frame-shaped trench-type insulating region 4 at a distance from the p-type region 6. ing. The n-type high concentration region 31 is connected to, for example, an input terminal as a terminal different from the low potential terminal.

Reference numeral 32 denotes a second n-type high-concentration region provided on the surface of the inner n-type region 3A.
Like the n-type high-concentration region 8, the inner n-type region 3A is formed by diffusing impurities such as arsenic at a high concentration. The n-type high-concentration region 32 is a p-type high-concentration region 7.
It is located on the opposite side of the n-type high-concentration region 8 with the (p-type region 6) interposed therebetween, and is spaced apart from the p-type region 6 and arranged between the p-type region 6 and the frame-shaped trench-type insulating region 4. ing. And
The n-type high-concentration region 32 is connected to the n-type high-concentration region 31 by a wiring or the like as shown by a dashed line in FIG.

Reference numeral 33 denotes a first trench-type insulating region provided between the p-type region 6 and the first n-type high-concentration region 31 and provided on the surface of the inner n-type region 3A. The mold insulating region 33 extends in a straight line substantially parallel to one side of the p-type region 6, and has both ends formed in a U-shape bent toward the p-type region 6. Thereby, the trench type insulating region 33 extends along the outer periphery of the p-type region 6,
The p-type region 6 is partially surrounded. Although the trench groove type insulating region 33 has its bottom portion in contact with the dielectric film 2 over the entire length, both ends thereof do not contact the frame trench type insulating region 4, and the trench groove type insulating region 4 A gap is formed between them.

Numeral 34 denotes a second trench-type insulating region provided between the p-type region 6 and the second n-type high-concentration region 32 and provided on the surface of the inner n-type region 3A. The mold insulating region 34 is provided at a position opposite to the trench-shaped insulating region 33 with the p-type region 6 interposed therebetween, and has both ends formed in a U-shape bent toward the p-type region 6. As a result, the trench-type insulating region 34 extends along the outer periphery of the p-type region 6 and partially surrounds the p-type region 6.
Although the trench-groove-type insulating region 34 has its bottom portion in contact with the dielectric film 2 over the entire length, both ends do not contact the frame-like trench-groove-type insulating region 4 and the trench-groove-type insulating region 33, A gap is formed between the trench-shaped insulating region 4 and the trench-shaped insulating region 33.

Thus, in the present embodiment, the same functions and effects as those of the first embodiment can be obtained. However, in the present embodiment, since two n-type high-concentration regions 31 and 32 are provided on the surface of the inner n-type region 3A with the p-type high-concentration region 7 interposed therebetween, as in the first embodiment. Compared to the case where one n-type high-concentration region 8 is provided, n-type high-concentration regions 31 and 32 are provided.
The entire area can be increased. Therefore, the first diode 35 formed between the p-type region 6 and the inner n-type region 3A, and the second diode formed between the p-type region 6 and the inner n-type high-concentration buried region 5A Each of the samples 36 has a small resistance component. Accordingly, the overall impedance of the first and second diodes 35 and 36 is reduced,
Since the potential rise of the input terminal voltage at the time of applying a surge can be suppressed more reliably, the surge current injected into the internal circuit can be further suppressed, the damage of the semiconductor device can be prevented, and the reliability and the like can be improved. be able to.

Since the trench-type insulating regions 33 and 34 are formed in a U-shape with both ends bent, the n-type high-concentration region 3 extends from the p-type high-concentration region 7 through the inner n-type region 3A.
The first current path leading to the high-concentration regions 31 and 32 from the p-type high-concentration region 7 to the high-concentration regions of the n-type high-concentration regions 31 and 32 are all provided. In comparison with the first embodiment, the length is further increased by the amount of bypassing the U-shaped trench-shaped insulating region. For this reason, the resistance difference between the parasitic resistance of the first current path and the parasitic resistance of the second current path can be increased, and the parasitic resistance of the first current path is larger than the parasitic resistance of the second current path. It can be even larger. Therefore, most of the surge current is reduced to the inside n while reducing the resistance component of the entire protection diode.
It can flow through the second diode 36 passing through the high-concentration buried region 5A. As a result, the p-type high concentration region 7
Without increasing the distance between the semiconductor device and the n-type high concentration regions 31 and 32, damage to the semiconductor device can be more reliably prevented, and reliability and the like can be improved while maintaining high integration.

In the third embodiment, both ends of the trench-shaped insulating regions 33 and 34 are formed in a U-shape bent along the outer periphery of the p-type region 6.
As shown in a first modification shown in FIG.
, Which are bent along the outer periphery of the n-type high-concentration regions 31 and 32 to surround the n-type high-concentration regions 31 and 32.
34 '.

In the first embodiment, the trench-type insulating region 9 is formed in a straight line.
As in the second modified example shown in FIG. 7, a trench-shaped insulating region 9 'having a U-shape with both ends bent may be used. The n-type high-concentration region 8 does not need to be separated from the trench-groove-type insulating region 9 ', and is in contact with the trench-groove-type insulating region 9' as shown by a two-dot chain line in FIG. A configuration in which the high concentration region 8 'is provided may be employed.

In each of the above embodiments, the n-type high-concentration regions 8, 31, and 32 are connected to the input terminals of the semiconductor device. However, the n-type high-concentration regions may be connected to the output terminals of the semiconductor device. In this case, a similar effect can be obtained for a surge applied to the output terminal.

Further, the p-type high-concentration region 7 may be connected to an input terminal or an output terminal, and the n-type high-concentration regions 8, 31, and 32 may be connected to high-potential terminals. In this case, the surge applied to the semiconductor device can be bypassed to the power supply side or the like that has a high potential, and the same operation and effect as the above-described embodiments can be obtained.

Further, the p-type high-concentration region 7 is connected to a low-potential terminal (low-potential power supply terminal), and the n-type high-concentration regions 8 and 3 are connected.
1, 32 may be connected to a high potential terminal (high potential power supply terminal). In this case, a surge applied to the power supply terminal can be generated, and the same operation and effect as those of the above-described embodiments can be obtained.

In each of the above embodiments, the dielectric film 2
Although the n-type high-concentration buried region 5 and the n-type region 3 are formed on the surface of the dielectric film 2, a p-type high-concentration buried region and the n-type region may be formed on the surface of the dielectric film 2. In this case, if the n-type and the p-type described in each embodiment are interchanged, and the low-potential terminal (low-potential power supply terminal) and the high-potential terminal (high-potential power supply terminal) are interchanged, the same operation as described above is performed. The effect can be obtained.

[0057]

As described above in detail, according to the first aspect of the present invention, the semiconductor region of the first conductivity type is provided in contact with the high-concentration buried region of the second conductivity type, and the high-concentration semiconductor region of the first conductivity type is provided. Since the trench type insulating region is provided between the region and the high-concentration region of the second conductivity type, the breakdown voltage of the semiconductor region of the first conductivity type is low in the high-concentration buried region of the second conductivity type, and A diode having a small parasitic resistance can be formed. Therefore, most of the surge current can flow through the diode regardless of whether a positive or negative overvoltage surge is applied. At this time, since the diode current does not concentrate on a part of the pn junction, damage to the semiconductor device can be prevented, and reliability and durability can be improved. In addition, since the distance between the semiconductor region of the first conductivity type and the high-concentration region of the second conductivity type can be reduced, high integration of the semiconductor device can be maintained. Further, various effects such as a reduction in manufacturing time and an improvement in productivity as compared with the related art can be achieved.

According to a second aspect of the present invention, a pad electrode is provided on the main surface of the high-concentration region of the first conductivity type, and the high-concentration region of the first conductivity type is connected to the pad electrode. A high degree of integration can be maintained, and a surge current can be made to flow substantially uniformly throughout the high-concentration region of the first conductivity type. This allows a surge current to flow through the pn junction of the diode formed between the high-concentration region of the first conductivity type and the high-concentration buried region of the second conductivity type with a more uniform current density. As a result, the breakdown voltage of the diode can be increased, and the reliability and durability can be further improved.

Further, according to the present invention, the second conductive type semiconductor region has, on the main surface, a second conductive type high-concentration region opposite to the second conductive type high-concentration region with the other first conductive type high-concentration region interposed therebetween. Since a high-concentration region of the second conductivity type is provided, and a U-shaped trench type insulating region is formed between the high-concentration region of the first conductivity type and the high-concentration region of each second conductivity type, The area of the entire high-concentration region of the second conductivity type can be increased. For this reason, since the impedance of the whole protection diode can be reduced, a surge current injected into an internal circuit or the like can be suppressed small, and damage to the semiconductor device can be prevented.

Further, since a U-shaped trench type insulating region is provided between the high-concentration region of the first conductivity type and the two high-concentration regions of the second conductivity type, the resistance component of the entire protection diode is reduced. Most of the surge current is
The current can flow through a diode formed between the high-concentration region of the conductivity type and the high-concentration buried region of the second conductivity type. Thereby, without increasing the distance between the high-concentration region of the first conductivity type and the high-concentration region of the second conductivity type of the semiconductor device,
Damage to the semiconductor device can be more reliably prevented, and reliability and the like can be improved while maintaining a high degree of integration.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view as seen from the direction of arrows II-II in FIG.

FIG. 3 is a cross-sectional view as seen from the direction of arrows III-III in FIG.

FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment as viewed from the same position as in FIG. 3;

FIG. 5 is a plan view showing a semiconductor device according to a third embodiment.

6 is a cross-sectional view as seen from the direction of arrows VI-VI in FIG. 5;

FIG. 7 is a plan view showing a semiconductor device according to a first modification.

FIG. 8 is a plan view showing a semiconductor device according to a second modification.

[Explanation of symbols]

Reference Signs List 1 silicon support substrate (semiconductor support substrate) 2 dielectric film (dielectric) 3 n-type region (semiconductor region of second conductivity type) 3A inner n-type region 5 n-type high concentration buried region (second conductivity type high concentration) 5A Inside n-type high-concentration buried region 6 P-type region (semiconductor region of first conductivity type) 7 P-type high-concentration region (high-concentration region of first conductivity type) 8,8 'N-type high-concentration region ( 9, 9 'Trench-groove-type insulating region 31 First n-type high-concentration region (high-concentration region of one second-conductivity-type) 32 Second n-type high-concentration region (others) 33, 33 'First trench type insulating region (one trench type insulating region) 34, 34' Second trench type insulating region (other trench type insulating region) region)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiro Shinohara 1370 Onna, Atsugi-shi, Kanagawa Prefecture Inside Unisia Gex Co., Ltd. 72) Inventor Teruyuki Mihara 2 Takara-cho, Kanagawa-ku, Yokohama-shi, Kanagawa Pref. Nissan Motor Co., Ltd. (72) Inventor Masakatsu Hoshi 2 Takara-cho, Kanagawa-ku, Yokohama-shi, Kanagawa Pref. BH13 EZ20

Claims (3)

[Claims] 1. A semiconductor region of a second conductivity type is formed on a main surface of a semiconductor support substrate via a dielectric, and a high-concentration buried region of the second conductivity type is formed on a bottom surface of the semiconductor region of the second conductivity type. Forming a semiconductor region of the first conductivity type on the main surface of the semiconductor region of the second conductivity type so as to be in contact with the high-concentration buried region of the second conductivity type; Providing a high-concentration region of one conductivity type, a high-concentration region of the second conductivity type on a main surface of the semiconductor region of the second conductivity type, and a high-concentration region of the first conductivity type and a high-concentration region of the second conductivity type; Forming a trench type insulating region on the main surface of the semiconductor region of the second conductivity type located between the high concentration region of the first conductivity type and the second conductivity type; One of the input terminal, output terminal, high potential terminal and low potential terminal While connected to Chiizure of terminals, the semiconductor device comprising the other as configuration of connecting to one of the terminals of the remainder. 2. The semiconductor device according to claim 1, wherein a pad electrode is provided on the main surface of the high-concentration region of the first conductivity type, and the high-concentration region of the first conductivity type is connected to the pad electrode. 3. The semiconductor device according to claim 1, wherein the first conductive type high-concentration region is located on the opposite side of the one second conductive type high-concentration region, and the second conductive type semiconductor region has another main region. A second conductivity type high concentration region is provided, and the second conductivity type semiconductor region is located between the first conductivity type high concentration region and another second conductivity type high concentration region. Forming another trench-shaped insulating region in contact with a dielectric and in a U-shape with the one trench-shaped insulating region; and forming the other second-conductivity-type high-concentration region into the second conductive-type high-concentration region. 3. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a high-concentration region of a conductivity type.