JPS62191262U - - Google Patents
Info
- Publication number
- JPS62191262U JPS62191262U JP7698986U JP7698986U JPS62191262U JP S62191262 U JPS62191262 U JP S62191262U JP 7698986 U JP7698986 U JP 7698986U JP 7698986 U JP7698986 U JP 7698986U JP S62191262 U JPS62191262 U JP S62191262U
- Authority
- JP
- Japan
- Prior art keywords
- clamp
- output transistor
- base terminal
- transistor
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims 1
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図は本考案によるペデスタスルレベルクラ
ンプ回路の一実施例、第２図は従来のペデスタル
レベルクランプ回路の一例、第３図は映像信号と
クランプパルスとの関係を示すタイミングチヤー
トである。
Ｔｒ１…出力用トランジスタ、Ｔｒ２…クラン
プ用トランジスタ、Ｔｒ３…温度補償用トランジ
スタ。
FIG. 1 is an example of a pedestal level clamp circuit according to the present invention, FIG. 2 is an example of a conventional pedestal level clamp circuit, and FIG. 3 is a timing chart showing the relationship between a video signal and a clamp pulse. T r1 ...Output transistor, T r2 ...Clamp transistor, T r3 ...Temperature compensation transistor.
Claims (1)
力される出力用トランジスタと、ベース端子にク
ランプパルスが入力したとき導通して前記出力用
トランジスタのベース端子の電位をコレクタ・エ
ミツタ回路に直列接続されたクランプレベル設定
素子により決定されるレベルにクランプするクラ
ンプ用トランジスタとを有する映像信号のペデス
タルレベルクランプ回路において、 前記クランプ用トランジスタのコレクタ・エミ
ツタ回路に、前記クランプレベル設定素子と直列
に前記出力用トランジスタの温度特性とほぼ等し
い温度特性を有する温度補償素子を接続したこと
を特徴とするペデスタルレベルクランプ回路。[Claims for Utility Model Registration] An output transistor to which a video signal is input to the base terminal via a capacitor is electrically connected when a clamp pulse is input to the base terminal, and the potential of the base terminal of the output transistor is connected to the collector. In a video signal pedestal level clamp circuit having a clamping transistor that clamps to a level determined by a clamp level setting element connected in series to an emitter circuit, the clamp level setting element is connected to a collector-emitter circuit of the clamping transistor. A pedestal level clamp circuit characterized in that a temperature compensating element having temperature characteristics substantially equal to the temperature characteristics of the output transistor is connected in series with the output transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7698986U JPS62191262U (en) | 1986-05-23 | 1986-05-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7698986U JPS62191262U (en) | 1986-05-23 | 1986-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62191262U true JPS62191262U (en) | 1987-12-05 |
Family
ID=30924578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7698986U Pending JPS62191262U (en) | 1986-05-23 | 1986-05-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62191262U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01239590A (en) * | 1988-03-22 | 1989-09-25 | Seiko Epson Corp | Liquid crystal display device |
-
1986
- 1986-05-23 JP JP7698986U patent/JPS62191262U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01239590A (en) * | 1988-03-22 | 1989-09-25 | Seiko Epson Corp | Liquid crystal display device |
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