JPS62191176U - - Google Patents

Info

Publication number
JPS62191176U
JPS62191176U JP1986079483U JP7948386U JPS62191176U JP S62191176 U JPS62191176 U JP S62191176U JP 1986079483 U JP1986079483 U JP 1986079483U JP 7948386 U JP7948386 U JP 7948386U JP S62191176 U JPS62191176 U JP S62191176U
Authority
JP
Japan
Prior art keywords
circuit board
display panel
electro
terminals
optical display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986079483U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986079483U priority Critical patent/JPS62191176U/ja
Publication of JPS62191176U publication Critical patent/JPS62191176U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Multi-Conductor Connections (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案の一実施例を説明するもので、第１
図は回路基板側の電極パツドに半田メツキを施し
た状態の説明図、第２図は電極パツド間にソルダ
ーレジストを塗布した状態の説明図、第３図は回
路基板と表示素子とを接合した状態の説明図であ
る。 １……回路基板、２，６……電極パツド、３…
…半田メツキ、４……ソルダーレジスト、５……
液晶表示パネル。 The figure is for explaining one embodiment of the present invention.
The figure is an explanatory diagram of the state in which the electrode pads on the circuit board side are soldered. Figure 2 is an explanatory diagram of the state in which solder resist is applied between the electrode pads. Figure 3 is an explanatory diagram of the state in which the circuit board and display element are bonded. It is an explanatory diagram of a state. 1... Circuit board, 2, 6... Electrode pad, 3...
...Solder plating, 4...Solder resist, 5...
LCD display panel.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電気光学的表示パネルと回路基板のいずれか一
方の端子上に低融点の半田を設けると共に、端子
間に絶縁性の接着剤を設け、この端子部分を重ね
合わせて熱圧着したことを特徴とする電気光学的
表示パネルと回路基板との接続構造。 A low melting point solder is provided on the terminals of either the electro-optical display panel or the circuit board, an insulating adhesive is provided between the terminals, and the terminal portions are overlapped and bonded by thermocompression. A connection structure between an electro-optical display panel and a circuit board.
JP1986079483U 1986-05-28 1986-05-28 Pending JPS62191176U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986079483U JPS62191176U (en) 1986-05-28 1986-05-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986079483U JPS62191176U (en) 1986-05-28 1986-05-28

Publications (1)

Publication Number Publication Date
JPS62191176U true JPS62191176U (en) 1987-12-04

Family

ID=30929383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986079483U Pending JPS62191176U (en) 1986-05-28 1986-05-28

Country Status (1)

Country Link
JP (1) JPS62191176U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0832195A (en) * 1994-07-11 1996-02-02 Nippondenso Co Ltd Connection structure of composite printed board
JPH10275967A (en) * 1997-03-28 1998-10-13 Nec Corp Electronic-component assembly and its manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0832195A (en) * 1994-07-11 1996-02-02 Nippondenso Co Ltd Connection structure of composite printed board
JPH10275967A (en) * 1997-03-28 1998-10-13 Nec Corp Electronic-component assembly and its manufacture

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