JPS6218956B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a preprocessing device for pattern recognition, and more particularly to a device for extracting minute portions of a pattern that will not remain in a thinned pattern.

The binary pattern is replaced with a thinning pattern, and based on the thinning pattern, feature points (for example, end points, branch points, intersections, bending points) and feature values (for example, stroke direction, degree of bending, dents near branch points) are calculated. There is a method of recognizing patterns by extracting the number of feature points and feature amounts stored in a dictionary.

However, when the pattern shown in FIG. 1a is subjected to line thinning processing, it becomes as shown in FIG. 1b, and some elements are generated in which nothing remains as a thinned pattern. Therefore, after comparing the information obtained from the thinning pattern with the recognition dictionary and giving a pattern name, it is difficult to distinguish whether the element disappeared during the thinning process for which the given pattern name was registered. It is necessary to check whether it matches the name, and if it does, refer to the recognition dictionary again and check whether there is an element that disappears in the original binary pattern, which makes the control difficult.
The disadvantage is that recognition takes time.

The present invention extracts minute portions of the binary original pattern that do not remain in the thinning pattern, and writes the representative points of the minute portions into a skeleton pattern memory that stores the thinning pattern, thereby creating a dot-like pattern. The purpose of this invention is to compensate for the drawback of thinning processing that nothing remains after thinning, and to facilitate recognition using a thinning pattern.

According to the present invention, the area measuring means for each element of the binary pattern, the representative point storing means for each element, and the two
A means for detecting whether a thinning pattern is included in an area of a skeleton pattern memory corresponding to each element existing area of a value pattern; A device for extracting minute portions of a pattern is obtained, which includes means for writing the representative points of the pattern into a skeleton pattern memory.

The present invention will be described below with reference to drawings showing embodiments.

FIG. 2 is a block diagram of an embodiment of the pattern minute part extraction device of the present invention, which includes an original pattern memory 1, a thinning processing section 2, a skeleton pattern memory 3, an area measurement section 4, and an element representative point storage section 5. , a skeleton pattern confirmation section 6, and a minute portion detection section 7.

The pattern to be recognized is optically scanned and quantized into a binary pattern such that the pattern part is ``1'' and the other part is ``0'', and the original pattern stores the binary pattern information (hereinafter referred to as the original pattern). It is stored in pattern memory 1. The original pattern in the original pattern memory 1 is thinned using a thinning mask from both sides of the pattern outline, leaving only the center line in the thinning processing section 2.
The pattern is converted into a thinning pattern (hereinafter referred to as a skeleton pattern) having a line width of 1 bit and stored in the skeleton pattern memory 3.

The area measurement unit 4 sequentially accesses the contents of the original pattern memory 1, uses a group of connected original patterns as elements, and calculates the area of each element.

The element representative point storage unit 5 stores the coordinates of the point that becomes the representative point of each element when the area measurement unit 4 extracts the elements.
Memorize point by point.

The skeleton pattern confirmation unit 6 accesses the contents of the skeleton pattern memory 3 and checks whether a skeleton pattern exists in the area corresponding to each element existing area of the original pattern.

Based on the outputs of the area measurement unit 4 and the skeleton pattern confirmation unit 6, the minute portion detection unit 7 determines whether there is no skeleton pattern in the area of the skeleton pattern memory 3 corresponding to the element existing area of the original pattern and whose area is larger than a certain value. Make the element a minute part and write the quantization signal "1" at the element representative point position of the skeleton pattern memory 3.

FIG. 3 is a block diagram for calculating area based on run length data as an example of area measuring means used in the present invention.

In FIG. 3, 8 is a binary pattern, 9 is a run length memory, 10 is a partial area memory, 11 is a label counter, 12 is a connection relation memory, and 13 is a label memory.

FIG. 5a shows an example of the binary pattern of FIG. 38, and FIGS. 5b to d, and FIGS. 6a and b show changes in the contents of the memory and counter of FIG. 3 for each scanning row, Each number on the left represents an address.

5b is the run length memory of FIG. 39, c
is the label counter in Figure 3 11, d is the label counter in Figure 3 1
3 shows changes in the contents of the label memory in No. 3.

6a shows the change in the contents of the connection relationship memory of FIG. 312, b shows the change in the contents of the partial area memory of FIG. 3, and c shows the final state of the contents of the partial area memory of FIG. 3.

A method for determining the area will be briefly explained with reference to FIGS. 5 and 6.

As a binary pattern, FIG. 5a shows the result in which points belonging to the pattern are set to "1" and points not belonging to the pattern are set to "0". However, in FIG. 5a, "0" is shown as a blank, and scanning is performed in the direction of the arrow in the order of the numbers from the smallest number on top.

Address A of the position added to the left side of the figure where the signal changes from "0" to "1" by scanning Figure 5 a.
Then, after A is detected, the address B at the position attached to the left side of the diagram of "0" that changes from "1" to "0" is stored as run length data A, B in the run length memory for one scanning column in the order of occurrence.

FIG. 5b shows changes in the contents of the run-length memory corresponding to one scanning line.

One run length data A, B of one scan row
1 already labeled for (B>A)
Run length data C, D before scanning row (D>C)
The minimum value 1 = min (l ₁ , l ₂ , ... l _o ) found from the labels l ₁ , l 2 , ... l o of the run-length data A and B is determined from the labels l 1 , l ₂ , ... l _o of the run-length data A and B. Label.

The conditions for being connected are (1) C≦A and A≦D (2) C≦B and B≦D (3) A<C and D<B (1), (2), or (3).

If there is no connected run length data, the contents of the label counter, which increases by one at that time, are given as the label.

FIG. 5c shows changes in the value of the label counter corresponding to the columns.

FIG. 5d shows a change in the contents of the memory storing the label when the label is attached corresponding to the run length data of FIG. 5b. Here, the label counter is cleared at the beginning of a scan, and the run length memory and label memory are cleared at the beginning of each scan.

Generally, with a label, l _n = min (l ₁ , l ₂ ,...l _o )
When finding n≧2, it indicates that different partial regions are merging, and when n=1, it indicates that the partial regions are continuous “1”. For example, if n=2, label l ₁ partial area and label
This means that the subregions 1 _{and 2} are connected. Therefore, the relationship between the partial areas of "1" is l _n = min (l ₁ , l ₂ , ... l _i , l _j ... l _o ) If l _n ≠ l _i , l _n ≠ l _j , the label l _i The "1" partial area of is connected to the "1" partial area of label l _j via the partial area of label l _n . here
l ₁ , l ₂ , ... _lo are the connected label values arranged in the order of detection.

FIG. 6a shows changes in the contents of the memory, which also shows the connection relationship of partial areas of "1", in correspondence with the scanning rows. The connection relation memory should have a capacity greater than the number of partial areas of "1" that are expected to occur, the contents can be accessed using label l as an address, and the contents are updated every scanning line. do. Before scanning an area including a pattern, the connection relationship memory is cleared, and when a label is generated, the label l is written in the connection relationship memory specified by label l. For example, the run length data 3 and 6 of the run length memory at address 1 in FIG. 5 b obtained by scanning the 6th column in FIG. 5 a are as follows:
Because there is no connection with the run length data obtained in the scan one scan row earlier, that is, the fifth row,
The value of the label counter increases by 1 to 2, and label 2 is written to the label memory location in Figure 5d at the same address as address 1 in the run-length memory, as shown in the 6th column of Figure 6a. ,
Label 2 is written to the connection relationship memory using label value 2 as an address.

Label l when a combination of partial regions is detected.
The label l _o is written in the connection relationship memory specified by _i , and it is assumed that the partial area of label l _n that is “1” has been combined with the partial area of label l _i that is “1”. For example, the run length data 7, 12 at address 1 in the 10th column in FIG. 5b obtained by scanning the 10th column in FIG. The label value 3 is based on the label memory values 4 and 3 in the 9th column of Figure 5 d, which is a label that is connected to both of 13 and is attached corresponding to the run length data.
= min (4, 3), and the label value 3 is written to the same label memory location as address 1 of the run-length memory shown in the 10th column of FIG. As shown in column
Label value 3 is written to the connection relationship memory location with label 4 as the address, and as a result, the partial area of label 3 is combined with the partial area of label 4.

The area memory of the partial area that stores the area of each partial area consists of a memory having the same capacity as the connection relationship memory, and the partial area memory can be accessed by label l.

When the label l is determined, the difference found from the run length data A and B (B>A) is added to the content of the partial area memory location designated by l. FIG. 6b shows the changes in the contents of the partial area memory corresponding to each column. For example, the run length data 3 and 6 in the 8th column of FIG. 5B obtained by scanning the 8th column in FIG. The run length data value difference 3=6-3 is added to the value 6 in the partial area memory at address 2 in the 7th column of FIG. Written as shown in column.

The processing of the area of the partial region and the connection relationship between the partial regions is performed until the entire scanning is completed. At the time when the scanning of the pattern shown in FIG. 5a is completed, the connection relation memories have addresses 1, 2, 3, 3 in the order of addresses. From now on, partial areas 1, 2, and 3 are partial areas 1, 2, and 3, respectively.
2 and 3, it can be seen that partial area 4 is connected to partial area 1. Each area is the final value of each partial area memory, 4, 9, 26, 1 in address order.
It is becoming. Based on the connection relationship, the area value of the label 1 area is set to address 1, the area value of the label 2 area is set to address 2, the area value of the label 3 area is set to address 3, and label 4 is set to label 1. Since they are combined, they are added to the area of label 1, and the area value of label 4 is reset to zero as shown in FIG. 6c.

Representative points of an element include the first point detected as an element, the last point detected as an element, and the center of gravity of the element.

To find the center of gravity of an element, it is necessary to add the positions of each point that makes up the element and divide the added value by the number of points.
On the other hand, to find the first point detected as an element, you only need to memorize the first point found when each element is detected, and to find the last point detected as an element, It can be obtained by reversing the direction of finding elements using the method of finding points detected in .

Therefore, if the representative point of an element is the point that is first detected as an element, the circuit becomes simpler.

FIG. 4 is a diagram showing an embodiment in which the element representative point is the first point detected as an element. , a partial element connection relationship processing circuit 30 , a connection relationship storage circuit 50 , an element area processing circuit 60 , and a partial area processing circuit 70 . Note that the control section is not shown.

80 is an address generation circuit that generates an address for accessing the memory, and includes counters 810 and 820.
Initially, both are cleared, and the outputs 821 and 822 of the counter 820 indicate the address corresponding to the row, and the outputs 811 and 8 of the counter 810 indicate the address corresponding to the row.
12 generates an address corresponding to the column. The counter 820 is cleared by a signal S-901 on a line 901 (hereinafter the signal on line L will be expressed as a signal S-L) from the control section every time the counter 810 is incremented by one.

The run length detection circuit 20 includes a flip-flop 200, a counter 210, and registers 220, 2.
30, 240, AND gates 250, 260, an inverter 270, and an OR gate 280. The signal S-901 from the control section is input to the OR gate 280 at the same time as clearing the counter 210, setting the output signal S-281 to "1", and the signal S-281
is input to the flip-flop 200 and the output signal S
-201 is set to "1" and S-202 is set to "0".
When an address is generated by the address generation circuit 20, the original pattern memory 1 is accessed, and the memory value of the specified address is set in the register 220. When the output signal S-221 of the register 220, in which the contents of the memory 1 are set, becomes "1" when the signal S-201 is "1", the AND gate 2
The output signal S-251 of the counter 820 becomes "1", and the output signal S-822 of the counter 820 indicating the row position of the address is set in the register 230 which sets the signal S-251. Also signal S-251
“1” is input to the flip-flop 200,
The output signal S-202 is set to "1" and the output signal S-201 is set to "0". When the counter 820 increases and the output signal S-221 of the register 220 becomes "0", the output signal S-271 of the inverter 270 becomes "1", and the output signal S-221 of the AND gate 260 becomes "0".
261 becomes "1", the counter 210 is incremented by 1, and the position where the memory 1 becomes "0", that is, the output signal S-822 of the counter 820, is set in the register 240 which uses the signal S-261 as a set signal. In addition, "1" of the output signal S-261 is input to the OR gate 280, and the flip-flop 200
The output signal S-201 is changed to "1" and the output signal S-202 is changed to "0" to return to the original state. The counter 820 is incremented and the above process is repeated until the value of the counter 820 crosses the value corresponding to the last row position.
10 is incremented by 1, and the counter 820 is cleared by the control signal S-901.

Therefore, the value of the counter 210 indicates the number of run length data in one scanning line.
The value 0 represents the position P of "1" that changes from "0" to "1" in one scanning line, and the value of the register 240 represents the position Q of "0" that changes to "0" after detecting P in one scanning line. ing.

The partial element connection relationship processing circuit 30 includes a label counter 300, a connection relationship detection circuit 310, and registers 320, 360, 370, 390, and 42.
0,440,460, and a run length data memory 330 that stores the run length data of the previous column.
, a run-length data memory 340 that stores the run-length data of the column being accessed, a memory 410 that stores the label corresponding to the run-length data of the column being accessed, and a memory 410 that stores the run-length data of the previous column. a memory 430 for storing labels to be selected, selection circuits 350, 380,
It consists of a comparison circuit 400 and a counter 450 that generates a memory address.

When a set of run length data is detected by the run length detection circuit 20, the counter 450 is started by the signal S-261, and the run length data memory 340 receives the output from the registers 230 and 240 using the signal S-211 as an address. Signal S-231
and S-241. label memory 410
is the signal S where the label attached to the run length data is output using the signal S-211 as the address.
-351 is stored. The run-length data memory 330 and the label memory 430 store data from the previous column, and the run-length data memory 330 is read out using the output signal of the counter 450 as an address and set in the register 320. The coupling relationship detection circuit 310 uses the obtained run length data signals S-231, S-241 and 1
Run length data signal in front of column S-321, S-
322 satisfies the above-mentioned coupling conditions (1), (2), or (3), and outputs "1" to the line 311 that is satisfied, which is then sent to the control section. When the line 312 is not connected to any data in the run-length data memory 330, "1" is output, and the label counter 300 is incremented by 1. Here, the label counter 300 is cleared before calculating the area. Counter 450 is started by signal S-261 and increments by one each time control signal 452 is sent. The label memory 430 outputs a label value using the output signal S-451 of the counter 450 as an address, that is, a label value attached to the combined line one line before. The output label value is set in the register 440 by the signal S-311 that is output when a connection is established. The register 460 stores all labels attached to connected run length data. (For example, 2 is set in register 440,
If 4 is set thereafter, 2 and 4 are stored in register 460. Here, the register 460 is cleared before obtaining the label. ) On the other hand, the maximum label value (for example, 64 in decimal notation for a 6-bit register) is set in the register 370, and the selection circuit 380 is set to the line 38.
The signal S-371 is output to the line 381 with the control signal S-382-1 of 2, and the signal S-401 is output to the line 381 with the control signal S-382-2 of the line 382.
Output. Hereinafter, the Nth control signal on line L will be denoted by S-L-N. When labeling,
First, the signal S-382-1 is generated, and the register 39
Set the maximum label value to 0. Next, the label memory 410 is read into the register 440,
When the label value attached to the combined run length data is set, the comparison circuit 400 compares the signal S-391 and the signal S-441 and outputs the signal with the smaller value to the line 401. After that, when the control signal S-382-2 is generated, the signal S-401 is input to the register 390, so that the minimum value of the label values attached to the combined run-length data is set in the register 390. Therefore, if the value of register 390 is the maximum value, the contents of counter 300 are not the maximum value, register 3 is
The content of 90 becomes the label attached to the run length data. The selection circuit 350 receives the signal S-301 from the counter 300 using the control signal S-352-1 output from the control unit when the value of the register 390 is the maximum value, and uses the control signal S-301 output from the control unit when the value is not the maximum value. -352-2 selects the signal S-401 from the register 390 and outputs the signal S-351 as a label value attached to the run-length data. registers 360, 420
is run length memory 330 and label memory 4
A buffer register for writing a value to 30.
After labeling one column of run length data, the contents of memories 340 and 410 are transferred to register 36.
Transferred via 0.420.

The connection relationship storage circuit 50 includes a selection circuit 500,
It consists of a memory 510 that indicates the connection relationship between partial elements, a memory write register 530, and a read register 520.

The selection circuit 500 selects the signal S-301 using the control signal S-502-1, the signal S-461 using the control signal S-502-2, and the signal S using the control signal S-502-3.
-601 with control signal S-502-4 and signal S-
641 on line 501. memory 510
is the control signal S- with signal S-501 as the address.
The output of register 530 is written under control signal S-511-1 and read to register 520 under control signal S-511-2. Therefore, the labels that are connected are connected to the counter 300 and the register 530.
Or, since it is set in register 460 and register 530, control signal S-502-1 and control signal S-511-1, or control signal S-50
2-2 and the control signal S-511-1 to the memory 51.
Written to 0. Here, the memory 510 is cleared before calculating the area.

The partial element area processing circuit 70 includes a partial element area memory 740, an addition circuit 700, and a subtraction circuit 78.
0, selection circuits 710, 750, 760, a register 770 containing the value "0", and registers 720, 730.

The selection circuit 750 sends the signal S-521 to the line 751 with the control signal S-752-1, the signal S-351 with the control signal S-752-2, and the signal S-601 with the control signal S-752-3. Output. The subtraction circuit 780 receives the run length data signal S-241.
and signal S-231 and outputs the result on line 781. Since subtraction here represents a difference in position, the result is the area value of the subelement. The control signal S-742-1 uses the signal S-351 (corresponding to the label value attached to the run-length data) selected by the control signal S-752-2 as an address.
The area value stored in the partial element area memory 740 up to now is set in the register 720 under
The signal S-713 and the signal S-781 are selected by the control signal S-713-1 of the selection circuit 710 and input to the adder circuit 700, and the added result is sent to the line 70.
1 and is set in register 730 through selection circuit 760 under control signal S-762-1. Since the new area has been set in the register 730, the control signal S-351 selected by the control signal S-752-2 is used as the address.
Under 742-2, the value of register 730 is written to memory 740. Here, the memory 740 is cleared before calculating the area.

After the entire memory has been accessed, the element area processing circuit 60 is started. Element area processing circuit 60
consists of a counter 600 (cleared), comparison circuits 620 and 630, a selection circuit 610, and a register 640.

The counter 600 is incremented by 1 every time the counter control signal S-602 is sent from the control section, and the output signal S-601 of the counter 600 is sent to the register 640 by the control signal S-612-1 of the selection circuit 610.
is set to

The output signal S-641 of the register 640 is output to the line 501 by the selection circuit 500 in accordance with the control signal S-502-4, and becomes the address of the memory 510. Memory 5 under control signal S-511-1
10 is read out and set in the register 520, the comparator circuit 630 detects whether the contents of the register 520 are equal to the contents of the register 640 used as the address, and the result is sent to the control section through the line 631 and is explained later. take action. register 52
If the values of 0 and 640 are not equal, register 52
The content of 0 is output to line 611 by selection circuit 610 by control signal S-612-2, and register 6
Set to 40.

When such operations are repeated until the contents of register 520 become equal to the contents of register 640 set immediately before, the label of the contents of counter 600 and the label of register 640 are combined.

The contents of counter 600 are compared with the contents of register 640 in comparator circuit 620, and the result is output on line 62.
1 to the control unit. When the result obtained in this way is that the contents of registers 520 and 640 are equal and the contents of register 640 and counter 600 are different, selection circuit 750 under control signal S-752-3 selects signal S on line 600. -60
1 on line 751, followed by the control signal S-
752-1 outputs the signal on line 521 to line 751. A control signal S-713-2 is sent to the selection circuit 710 so that the output of the register 720 containing the area of the partial element is selected. When the line 601 is selected by the selection circuit 750, the contents of the partial element memory 740 specified by the contents K of the counter 600 are set in the register 730,
The contents of the register 770 set to “0” are changed to the selection circuit 760 by the control signal S-762-2.
is set in register 730 via . Subsequently, when the line 521 is selected, the contents of the memory 740 specified by the contents H of the register register 520 are set in the register 720, and the control signal S-
Register 7 containing the output of register 720 and the contents specified by the address of K by 713-2
The output of 30 is selected by the selection circuit 710 and input to the addition circuit 700, and the added result is set in the register 730 and written to the address location of H. Through this processing, the area of the partial element of label K is integrated with the area of the partial element of label H. When the contents of the counter 600 and the contents of the register 520 are equal, nothing is done, the contents of the counter 600 are incremented by 1, and processing moves on to the partial element area of the next label. Through the above processing, each label element area is set in the memory 740.

The skeleton pattern confirmation section 6 has a memory 670.
(cleared before accessing original pattern memory 1) and registers 650 and 6
60, 680, an AND gate 690, and an OR gate 695.

Register 660 is cleared each time run length data is determined by signal S-201. The contents of the skeleton pattern memory 3 accessed by the address of the address generation circuit 20 are set in the register 650, and on the other hand, the signal S-202 is "1" between the addresses where run-length data is detected, so the run-length data is If a skeleton pattern is detected between the addresses where the AND gate 690 is detected, the AND gate 690 outputs "1" and sets the register 660 to "1", and if the output of the AND gate 690 is "0", the register 660 retains the previous value. ing.

First, the signal S-351 indicating the label value to be added to the run length data is set as an address, and the memory 67
The contents of 0 are output to register 680, then the outputs of registers 660 and 680 are logically summed by OR gate 695, and the output is written to memory 670 using signal S-351 as an address. Therefore, when the entire processing is completed, the contents of the memory 670 indicate whether there is a skeleton pattern in the element area of each label value of the original pattern by "1" if there is, and by "0" if not.

The element representative point storage unit 5 includes a memory 560 for storing the representative point position of an element, that is, the position address of the first detected point of each element of the binary pattern in the original pattern memory 1, and a memory output buffer register 550.

The first run length data of each element is run length data that is not connected to the run length data of the previous scan row, and the position of the first point of each element is the row length data of the scan row for which the run length data is being obtained. The first run length data A1, B1 of each element is represented by A1 as a line position, and one point is stored for each element. Therefore, in the memory 560 that stores element representative points, a signal S-312 which becomes "1" when unconnected run length data is detected is used as a set signal, and a signal S-351 indicating a label value representing an element number is stored. When the output signal S-811 of the counter 810, which represents the scanning column as the address and the column position, changes from "0" to "1" of the scanned quantized signal corresponding to A1 of the run length data as the row position. The output signal S-231 of the register 230 having the location address set to 1'' is stored.

The minute portion detection unit 7 includes a register 900 containing a constant value, a comparison circuit 910, and an inverter 930.
and an AND gate 920.

After area processing of each element, control signals S-742, S
-671 and S-561 access the memories 740, 670, and 560 in order for each label, and the comparison circuit 910 detects an area larger than a certain value, and the output of the inverter 930 indicates whether a skeleton pattern is included. The gate 920 outputs "1" when the area does not include a skeleton pattern and is above a certain value, and the element representative point, which is the output of the memory 560, is set in the register 550 by the output of the AND gate 920, and the output value of the register 550 is set. "1" is written to the skeleton pattern memory as the address.

Through the above processing, elements that do not remain in the skeleton pattern are extracted, and the representative points of the elements are written in the skeleton pattern memory, thereby making it possible to set the element representative points as points of the skeleton pattern.

As described above, according to the present invention, the drawback of thinning processing that nothing remains when a dot-like pattern is thinned is compensated for, and minute portions of a pattern can be easily recognized using thinning patterns. We can provide extraction equipment.

[Brief explanation of the drawing]

FIG. 1a is an example of a binary pattern, b is an example of a pattern obtained by thinning a, and FIG. 2 is a block diagram of an embodiment of the pattern minute part extraction device of the present invention. Figure 3 is an example of the area measuring means used in the present invention, which is a block diagram for determining the area by leveling run length data, and Figure 4 is a block diagram of the area measuring means used in the present invention.
This is a detailed diagram in which the area measuring section in the block diagram shown in the figure is configured by labeling run length data. 5 and 6 are diagrams for explaining the process of FIG. 3, where FIG. 5 a stores an example of a binary pattern, and FIG. 5 b stores run length data of the pattern of FIG. 5 a. Figure 5c shows the changes in the contents of the run-length memory, Figure 5c shows the changes in the value of the label counter, and Figure 5d shows the changes in the contents of the label memory that stores the label value attached to the run-length data in Figure 5b. , Figure 6a shows the changes in the contents of the connection relationship memory that stores the connection relationships between labels, and Figure 6b shows the changes in the contents of the partial area memory that stores the partial area of each label. are shown in correspondence to the scan rows of . FIG. 6c shows the contents of the partial area memory after completing each label area process. In the figure, 1 is an original pattern memory, 2 is a thinning processing section, 3 is a skeleton pattern memory, 4 is an area measurement section, 5 is an element representative point storage section, 6 is a skeleton pattern confirmation section, 7 is a minute portion detection unit, 8 is a binary pattern, 9 is a run length memory, 10 is a partial area memory,
11 is a label counter, 12 is a connection relationship memory, and 13 is a label memory. Further, 20 is a run length detection circuit, 30 is a partial element connection relationship processing circuit, 50 is a connection relationship storage circuit, and 60 is a connection relationship storage circuit.
70 represents an element area processing circuit, 70 represents a partial element area processing circuit, and 80 represents an address generation circuit.

Claims (1)

[Scope of Claims] 1. An original pattern memory that stores a binary pattern, a thinning processing means that converts the binary pattern into a thinning pattern, a skeleton pattern memory that stores the thinning pattern, and the binary pattern. means for measuring the area of each element using a connected block of elements; means for extracting a representative point of each element and storing the position of the representative point; A method for checking whether a thinning pattern is included in the area of the corresponding skeleton pattern memory, and defining an element that does not include a thinning pattern and having an area of a certain value or more as a minute part, and storing a representative point of the element in the skeleton pattern memory. 1. An apparatus for extracting minute portions of a pattern, comprising a writing means. 2. The pattern minute portion extraction device according to claim 1, wherein the representative point of the element is the first point detected in element detection.