JPS62188423A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62188423A JPS62188423A JP61030019A JP3001986A JPS62188423A JP S62188423 A JPS62188423 A JP S62188423A JP 61030019 A JP61030019 A JP 61030019A JP 3001986 A JP3001986 A JP 3001986A JP S62188423 A JPS62188423 A JP S62188423A
- Authority
- JP
- Japan
- Prior art keywords
- level
- output
- state
- circuit
- goes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000001052 transient effect Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 2
- 230000007704 transition Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野１
本発明は半導体回路装置に係り、特に相補型論理回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a semiconductor circuit device, and particularly to a complementary logic circuit.
従来、各種表示素子等の駆動用の回路においては、第２
図に示すように１入力端子７に入力された入力信号が状
態保持回路１によりラッチされた後、バッファを通して
出力端子８に出力される構成が一般的である。このとき
、０Ｍ０８回路では出力バッファとしてインバータ１３
を用いている。Conventionally, in circuits for driving various display elements, etc., the second
As shown in the figure, a general configuration is such that an input signal input to one input terminal 7 is latched by a state holding circuit 1 and then outputted to an output terminal 8 through a buffer. At this time, in the 0M08 circuit, the inverter 13 is used as an output buffer.
is used.
前述した回路では、出力バッファは外部負荷を駆動する
ため、他の内部素子に比べ大型となり、特に０Ｍ０８回
路の場合、出力が切り換わる際に流れる貫通電流はＣＭ
Ｏ８構成にすることによる低消費電力性を損なうと共に
、特に多出力の回路で多数の出力が同時に変化し、電源
ラインのインピーダンスが高い場合等の電源電圧の過渡
的な変動に起因する誤動作の生じる回部性があり、低消
費電力化の必要とされる機器においては望ましくないと
いう欠点がある。In the circuit described above, the output buffer drives an external load, so it is larger than other internal elements, and especially in the case of the 0M08 circuit, the through current that flows when the output is switched is CM
In addition to impairing the low power consumption achieved by the O8 configuration, malfunctions may occur due to transient fluctuations in the power supply voltage, especially in multi-output circuits where many outputs change simultaneously and the impedance of the power supply line is high. This has the disadvantage that it is undesirable for equipment that requires low power consumption.
本発明の目的は、前記欠点が改轡され、一時的に大電流
が流れないようにした半導体装置を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the above-mentioned drawbacks are corrected and a large current does not temporarily flow.
本発明の半導体装置の構成は、入力が印加される第１の
状態保持回路の出力を第２の状態保持回路の入力に接続
し、前記第１．第２の状態保持回路の出力をそれぞれ第
１．第２のデコード回路の入力に接続し、前記第１．第
２のデコード回路の出力をそれぞれＰチャネル型トラン
ジスタのゲート、Ｎチャネル型トランジスタのゲートに
接続し、前記Ｐチャネル型、Ｎチャネル型トランジスタ
は互いに直列接続され、共通の接続点から出力端子を得
ていることを特徴とする。The configuration of the semiconductor device of the present invention is such that the output of the first state holding circuit to which an input is applied is connected to the input of the second state holding circuit, and the output of the first state holding circuit is connected to the input of the second state holding circuit. The outputs of the second state holding circuits are respectively connected to the first and second state holding circuits. connected to the input of the second decoding circuit; The output of the second decoding circuit is connected to the gate of a P-channel type transistor and the gate of an N-channel type transistor, respectively, and the P-channel type and N-channel type transistors are connected in series with each other, and an output terminal is obtained from a common connection point. It is characterized by
〔実施−〇 次に本発明について図面を参照して詳細に訣明する。[Implementation-〇 Next, the present invention will be explained in detail with reference to the drawings.
第１図は本発明の一実施例の半導体装置を示すブロック
図である。同図において、第１の状態保持回路１の出力
を第２の状態保持回路２の入力に接続し、第１．第２の
状態保持回路１，２の出力をそれぞれ第１．第２のデコ
ード回路３，４の入力に接続し、これら第１．第２のデ
コード回路３゜４の出力をそれぞれＰチャネル型トラン
ジスタ５のゲート、Ｎチャネル型トランジスタ６のゲー
トに接続する。トランジスタ５．６の共通接続点から出
力端子８を得る。ラッチ信号端子９からのラ 。FIG. 1 is a block diagram showing a semiconductor device according to an embodiment of the present invention. In the figure, the output of the first state holding circuit 1 is connected to the input of the second state holding circuit 2, and the first state holding circuit 1 is connected to the input of the second state holding circuit 2. The outputs of the second state holding circuits 1 and 2 are connected to the first and second state holding circuits 1 and 2, respectively. The inputs of the second decoding circuits 3 and 4 are connected to the inputs of the first and second decoding circuits 3 and 4. The outputs of the second decoding circuit 3.4 are connected to the gate of the P-channel transistor 5 and the gate of the N-channel transistor 6, respectively. Output terminal 8 is obtained from the common connection point of transistors 5.6. La from latch signal terminal 9.
ッチ信号け、直接第１の状態保持回路１へ、インバータ
を介して第２の状態保持回路２へ、それぞれ入力される
。The switch signal is input directly to the first state holding circuit 1 and to the second state holding circuit 2 via the inverter.
第３図は本発明の他の実施例の半導体装＃Ｌを示す回路
図である。同図において、第１．第２の状態保持回路と
して、Ｄ型ラッチ１０．１０’を用い、第１のデコード
回路３としてＮＡＮＤ素子１１を、第２のデコード回路
４としてＮＯＲ素子１２を使用している。FIG. 3 is a circuit diagram showing a semiconductor device #L according to another embodiment of the present invention. In the figure, 1. A D-type latch 10, 10' is used as the second state holding circuit, a NAND element 11 is used as the first decoding circuit 3, and a NOR element 12 is used as the second decoding circuit 4.
本発明の一実施例、他の実施例による回路は以上のよう
に構成されているので、これらを使用する際には、例え
ばデコード回路３として、２つの入力が両方とも１ＩＨ
１′の場合に” Ｌ １１ 、他の場合にＩＨＩを出力
する回路を使用し、デコード回路４として、２つの入力
が両方ともＩＩ Ｌ ＩＩの場合にＩＩ ｌ（ＩＩ１他
の場合にＩＩ Ｌ ＩＩを出力する回路を使用する。ま
た状態保持回路はラッチ信号端子９がＩＩＩ、ＩＩで保
持、Ｈ″で入力信号端子からの信号を読み込むとする。Since the circuits according to one embodiment and other embodiments of the present invention are configured as described above, when using them, for example, as a decoding circuit 3, two inputs are both 1IH.
A circuit that outputs "L 11 in the case of 1' and IHI in other cases is used as the decoding circuit 4, and when the two inputs are both II L II, II l (II1 in other cases II L II It is assumed that the state holding circuit holds the latch signal terminal 9 at III and II, and reads the signal from the input signal terminal at H''.
まず、出力がＩＩＬ″から１１Ｈ１１に変化する場合を
考えると、初期状態として状態保持回路１にはＩＩ Ｌ
ＩＩが保持されている。ここで入力信号端子７をＩＩ
）ｌ １１とし、ラッチ信号端子９ｔ−ＩＩ ）ｌ
ＩＩとすると、状態保持回路１が” Ｈ”となる。従っ
てデコード回路４の出力が１ｌＨ１１からＩＩ Ｌ Ｉ
Ｉに変化し、出力端子８けハイ寺インピーダンス状態と
なる。First, considering the case where the output changes from IIL'' to 11H11, the state holding circuit 1 has II L as an initial state.
II is retained. Here input signal terminal 7 is connected to
)l 11, and the latch signal terminal 9t-II)l
If it is set to II, the state holding circuit 1 becomes "H". Therefore, the output of the decoding circuit 4 is from 1lH11 to II L I
The output terminal changes to I, and the output terminal becomes in a high impedance state.
次にラッチ信号端子９がＩＩ Ｌ ＩＩに戻ると、状態
保持回路２が” Ｈ”となるため、デコード回路３の出
力がｎＨＩ′から’ｌ Ｌ ”に変化し、出力端子８は
ＩＩ ｌ（１１となる。Next, when the latch signal terminal 9 returns to II L II, the state holding circuit 2 becomes "H", so the output of the decoding circuit 3 changes from nHI' to 'l L', and the output terminal 8 becomes II l ( It becomes 11.
このようにラッチ信号端子９にパルスを加えると、出力
端子の状態遷移の過程で必らずハイ・インピーダンス状
態となるので、出力のＰチャネル型トランジスタ５から
Ｎチャネル型トランジスタ６へ流れる貫通電流が生じな
い。When a pulse is applied to the latch signal terminal 9 in this way, the output terminal always enters a high impedance state during the state transition process, so that the through current flowing from the output P-channel transistor 5 to the N-channel transistor 6 is reduced. Does not occur.
以上説明したように、本発明によれば、出力信号の切り
換わりの際に出力バッファが一時的にハイ・インピーダ
ンス状態となるため、過渡状態での貫通電流が流れず、
このため回路の低消費電力化が可能なだけでなく、大電
流による過渡的な電源電圧変動も生じず、誤動作の防止
にも有効であり、また特にラッチ信号のパルス＠ｆ：Ｓ
る程度小さくすることで、ハイ・インピーダンス状態の
期間を短かくすれば、表示パネルの駆動においては視覚
上も全く問題がない等の効果が得られる。As explained above, according to the present invention, the output buffer temporarily enters a high impedance state when the output signal is switched, so that no through current flows in a transient state.
Therefore, not only is it possible to reduce the power consumption of the circuit, but also there is no transient power supply voltage fluctuation due to large current, which is effective in preventing malfunctions, and especially the latch signal pulse @f:S
If the period of the high impedance state is shortened by making the impedance as small as possible, effects such as no visual problems can be obtained when driving the display panel.
【図面の簡単な説明】
第１図は本発明の一実施例の半導体装置を示すブロック
図、第２図は従来の一般的な回路例を示すブロック図、
第３図は本発明の他の実施例の半導体装＃、を示す回路
図である。
１．２・・・・・・状態保持回路、３．４・・・・・・
デコード回路、５・・・・・・Ｐチャネル型トランジス
タ、６・・・・・・Ｎチャネル型トランジスタ、７・・
・・・・入力端子、８・・・・・・出力端子、９・・・
・・・ラッチ信号端子、１０．１０’・・・・・・Ｄ型
ラッチ、１１・・・・・・ＮＡＮＤ素子、１２・・・、
・・ＮＯ几素子、１３・山・・インバータ。
代理人 弁理士 内 原 晋 ″“−・ツバ゛ハ
人ｊｌ−ｌＩ象１１日詩
峯１圀
猶？削[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional general circuit example,
FIG. 3 is a circuit diagram showing a semiconductor device # according to another embodiment of the present invention. 1.2... State holding circuit, 3.4...
Decode circuit, 5...P-channel transistor, 6...N-channel transistor, 7...
...Input terminal, 8...Output terminal, 9...
...Latch signal terminal, 10.10'...D-type latch, 11...NAND element, 12...,
・・NO element, 13・mountain・inverter. Agent Patent Attorney Susumu Uchihara Cut
Claims (1)
態保持回路の入力に接続し、前記第１、第２の状態保持
回路の出力をそれぞれ第１、第２のデコード回路の入力
に接続し、前記第１、第２のデコード回路の出力をそれ
ぞれＰチャネル型トランジスタのゲート、Ｎチャネル型
トランジスタのゲートに接続し、前記Ｐチャネル型、Ｎ
チャネル型トランジスタは互いに直列接続され、共通の
接続点から出力端子を得ていることを特徴とする半導体
装置。The output of the first state holding circuit to which the input is applied is connected to the input of the second state holding circuit, and the outputs of the first and second state holding circuits are connected to the inputs of the first and second decoding circuits, respectively. The outputs of the first and second decoding circuits are connected to the gates of the P-channel transistor and the N-channel transistor, respectively.
A semiconductor device characterized in that channel type transistors are connected in series with each other and have an output terminal obtained from a common connection point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030019A JPS62188423A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030019A JPS62188423A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62188423A true JPS62188423A (en) | 1987-08-18 |
Family
ID=12292128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61030019A Pending JPS62188423A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188423A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5324766A (en) * | 1976-08-20 | 1978-03-07 | Citizen Watch Co Ltd | Driving circuit for electronic device |
-
1986
- 1986-02-13 JP JP61030019A patent/JPS62188423A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5324766A (en) * | 1976-08-20 | 1978-03-07 | Citizen Watch Co Ltd | Driving circuit for electronic device |
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