JPS62187943A - Data monitoring device - Google Patents

Abstract

PURPOSE:To reduce bugs which can not be detected by debugging by forming a means for stopping the operation of a device referring a memory if necessary at the time of detecting that an uninitialized memory has been referred. CONSTITUTION:In case of the contents of bits of a certain AND memory being '1', '0' has ever written in bits corresponding to an objective memory until that time, and when the contents of bits or an OR memory are '0', '1' has never written in the coresponding bits of the objective memory. When the memory in which data have been never written until that time, is read out, '1' is outputted to a non-initialized memory reading detecting signal 16 to be an output from an AND gate 15. The operation of the device can be stopped by inputting the detecting signal 16 to an operation stop signal input terminal of the device operating the objective memory.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data monitoring device that monitors data of a memory manipulation device that performs data manipulation to a memory, and in particular, to a data monitoring device for monitoring data of a memory manipulation device that performs data manipulation to a memory, and in particular, a data monitoring device for monitoring data of a memory manipulation device that manipulates data in a memory. The present invention relates to a data monitoring device for monitoring data manipulated by a program to be debugged in an evaluation device.

[Conventional technology]

One of the causes of failure in programs such as microcomputers is due to referencing the contents of uninitialized memory.The memory referenced by the program must have some data such as ii+1 beforehand. To do this, it is desirable to initialize and initialize all the contents of the memory used as the data area as preprocessing of the program, but especially in micro combinators, there are limitations due to the size of the program and , or because of the time issue of initializing memory that does not need to be initialized, only the minimum necessary memory is often initialized.In such cases, initialization is necessary due to a mistake in the programming grammar. Sometimes the required memory initialization is forgotten. Such program bugs are usually not discovered during the debugging process. This is because even uninitialized memory may be 0" or 11" after the power is turned on. This is because if the value at that time is different from the value to be initialized, the progerium will operate normally.

Such bugs are usually discovered after the Deva Nob process is completed and the program is released. However, conventional micro combinator program evaluation devices do not have a means to detect this type of bug in advance.

Furthermore, in the process of evaluating (debugging) a created program, all specification items of the program must be evaluated.

For example, if a bit of memory is set to 7 in the program.
If used as a lug, the bit should be 1″
It is necessary to evaluate both cases of '01' and '01', but in a program that uses many 7-lags of this type, some of them may be 0" or 1" due to omission of evaluation items. There may be cases where only one side is evaluated.

In this way, when evaluation items are omitted, '0' or '1
In general, if a flag that has been set only with "" is stored as a value opposite to the value at the time of evaluation during actual f-history use, it is not guaranteed that the program will operate normally.
At the time the evaluation is completed, all 7 lags are low (both 1
1g1 is considerably reduced by 1 Li to determine whether the state is both "l" and 0. However, conventional micro combinator evaluation devices only evaluate whether the state is 0" or 0".
There was no means for detecting memory bits in which only data of 1" was written.

[Means to solve the problem]

In view of the current situation described above, the present invention detects that uninitialized memory is referenced, and if necessary, stops the operation of the device that made the memory reference at that point, and evaluates the After completion, ’1” and ’θ” are stored in the memory of all
An object of the present invention is to provide a data monitoring device used in a program evaluation device such as a micro combinator, which is capable of detecting whether or not both data have been written.

The data monitoring device of the present invention can similarly target a memory that is initialized to ``0'' with a bit configuration that corresponds one-to-one to each beat of the memory to be transparently viewed (hereinafter referred to as OR memory). A memory that is initialized to “1” with a bit configuration that corresponds one-to-one to each bit of the memory (hereinafter referred to as AN
Each time data is written to the target memory, each bit of the OR memory and AND memory corresponding to the address of the target memory that participated in the write operation is Perform the following processing. That is, for the OR memory, the content of the corresponding bit and the write data are logically ORed, and the result is sent to the corresponding OR memory. ! Also, for the AND memory, a logical AND operation is performed between the contents of the corresponding bit and the write data, and the result is written to the corresponding AND memory.

If a read operation is performed on the target memory, the contents of the corresponding OR memory and the contents of the corresponding AND memory are read, and if the contents of the OR memory are 0'' and the AND memory If the content of is 1”, then
It is determined that no data has ever been written to the target memory that participated in the read operation, that is, a reference was made to uninitialized memory. If necessary, at the time when an uninitialized memory reference is made, an operation stop request signal is output to the device that made the memory reference.

Further, the data monitoring device of the present invention, after the evaluation of the program is completed, if the content of the 0 memory is "1°" and the content of the corresponding AND memory is 1, the data monitoring device of the present invention changes the bits of that memory to It is determined that only "■" was written to the corresponding target memory bit at the time of evaluation. Similarly, if the content of the AND memory is O" and the content of the corresponding 01 memory is @0", it is determined that only O" was written to the bit of the corresponding target memory. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diaphragm of one embodiment of the present invention.

When a write operation is performed to the target memory,
Its address is:! F@ is output to the incoming address bus 1, and if a read operation is performed, it is output to the read address bus 2. Write address - bus 1
The read address bus 2 is input to the selection circuit 30, and either address selection 43 or 9 is output to the address bus 5. In the embodiment shown in FIG. 1, it is assumed that the target memory is 4 bits wide. Address bus 5 is connected to address inputs of test memory 6. An 8-bit wide memory is used as the test memory 6, of which the upper 4 bits are used as an AND memory and the lower 4 bits are used as an O11 memory. Reading and writing to the test memory 6 is performed by keeping the test memory write signal 7 low, and when this signal is activated, the contents of the AND data bus 8 and the OR data bus 9 are read from and written to the test memory 6. are written to the lower 4 bits and upper bits of the test memory specified by the contents of .

Furthermore, when the test memory write signal 7 is not activated,
The contents of the test memory 6 specified by the contents of the address bus 5 are read out to the AND path 8 and the 0 bus 9, respectively.

Data to be written to the target memory is output to the data bus 11, and each bit of the data is input to the write data units 200-230. When an arbitrary address of the target memory is accessed not in units of 4 bits, but when specific bits are masked and -C accessed, the mask data bus 12 corresponding to the masked bits is "0" is output to the store number line, and "1" is output to line 48 corresponding to the other bits.

Write data unit 200, 210, 220°2
30 are composed of the same circuit, so here, the configuration will be explained using the least significant bit 200 as an example. The least significant bit of the mask data bus 12 is inverted to an inverter 24)1 and output to an OR gate 20.
2 is input. The other input of gate 202 is the least significant bit of the data bus, and the output of gate 202 is input to AND gate 204.

) k i'J The other human power of D gate 204 is
The least significant bit of AND pass 8 (test memory 60 bits -
The contents of item a 4) are input. AND gate 203 contains the least significant bit of data bus 11 and mask data e.
The least significant bit is input to bus 12. OR gate 20
5, the output of the AND gate 203 and the least significant bit of the OR+ bus 9 are input.

The data latches 300 and 400 each have a 4-bit configuration, and the data latch 400 receives four gate output signals corresponding to the AND gate (AND gate) 204 of the write data units 200 to 230.
write data units 200, 210, 220
, 230 are input, and are latched using the latch clock 13, respectively. Data latches 300 and 400 are connected to AND data paths 8 and OR data paths, respectively, via 4-bit three-state buffers 401 and 301, respectively.
Connected to data bus 9.

Read data unit 100, 110, 120°1
30 are all composed of the same circuit, so here we use the read data unit 10, which is the least significant bit.
9 will be explained using 0 as an example. The AND gate 102 contains the least significant bit of the mask data path 12 and the AND data.
Least significant bit of pass 8 (bit number 4 of test memory 6)
and the least significant bit of data path 9 is inverter 10
A signal that is inverted and modified to 1 is input, and its output becomes the output of the read data unit 100.

Read data unit 100, 110, 120°1
The output of 30 is input to the 0 gate 140, and the output is ANDed with the target memory read mode signal 14.
It is input to gate 15.

Next, the operation of the embodiment shown in FIG. 1 will be explained. Incidentally, FIG. 2 shows a timing chart of the main signals of the embodiment of FIG. 1.

Before monitoring data, the data monitoring device of the embodiment shown in FIG. Initialize to @1”.

Although the means for initialization is not shown in FIG. 1, this initialization may be performed by a control device such as a microcombi controller that controls this data monitoring device. At that time, the control device outputs the address of the test memory 6 to be initialized on the write address path 1 and outputs the address of the test memory 6 to be initialized on the AND bus 8.
11 (binary) data and 0000 (
By outputting data in binary format and activating test memory write signal 7 for all addresses in the test memory, the lower 4 bits of all addresses in the test memory become 0000 (binary). , and the upper 4 bits are 1111
(binary).

After the above initialization is completed, the data monitoring device shown in FIG. 1 monitors the data in the target memory.

Assuming that a read operation is performed on the target memory, the read operation is performed on the near address bus 5 during the period (■) in the timing diagram of FIG. The data at the address corresponding to the memory is output. If the read operation is now performed on all bits of the specified address, the mask data bus 1')
PJA? If the readout operation is performed only on a specific bit, an 'O' is output to the mask data bus 120 bit corresponding to the bit to be masked that is not read.

Read data unit 100, 110, 120°1
30 unconditionally sets the output to "0" when the target memory bit corresponding to each bit is masked.
“, but if not masked, and AND
Only when the corresponding bit of the data bus is @l” and the corresponding bit of the OR data bus is 10”, the output is “
Set it to 1”.

The fact that the output of the read data unit is 11" indicates that the corresponding bit in the test memory is the initial value. If the read unit is 100°110.120
, 130, the output of the OR gate 140 becomes 1''.

Since the memory in question is in read mode,
Since 1" is output to the read mode signal 14, A
If the output of the ND gate 15 is "1", no data has been written yet. Indicates that a read operation was performed on target memory that does not exist.

When a write operation is performed on the target memory, the contents of the write address 1 are output to the address path 5 during the periods marked ■ and ◎ in the timing diagram of FIG. Inspection memory 6
When the test memory write signal 7 is ``O'', the contents of the address-path 5 and the contents of the specified memory 6 are ANDed.
Output to data path 8 and OR data path 9.

The timing chart in FIG. 2 shows that the contents of the test memory 6 are read out during the period (■). The data written to the target memory during this period (2) is masked in the same manner as in the read data unit by modifying the contents of the corresponding bit of the mask data path 12. if,
If the corresponding bit is masked, the output of the AND gate 204 contains the contents of the corresponding bit of the AND memory, and the output of the OfL gate 205 contains the OR gate.
The contents of the corresponding bits in memory are output as they are. If it is not masked, the AND gate 204 outputs the result of the AND operation of the corresponding bits of the data path 11 and the AND memory, and the OR gate 205 outputs the result of the AND operation of the corresponding bits of the data path 11 and the OR memory. The result of the logical OR operation of the corresponding bits is output. The results of these operations are applied to the latch clock 13, which is output in the second half of the period (■) in the timing diagram of FIG.
and latched to 400. Next, in period O, gate signal 10 is activated and the contents of latches 300 and 400 are output to OR data path 9 and AND data path 8 via three-state buffers 301 and 401. During this O period, the test memory fF write signal 7 is also activated, and the contents of the OR data path 9 and the AND data path 8 are written to the lower 4 bits and upper 4 bits of the test data memory 6, respectively.

From this, it is possible to determine the contents of the 60 bits of the test memory (9) and the status of the target memory corresponding to those bits. In other words, if the content of a bit in a certain AND memory is 11'', it means that @0'' has not been written to the corresponding bit in the target memory by that time, and If the content is ``0'',
Indicates that ``1'' has never been written to the corresponding bit in the target memory. In other words, if the content of a certain bit in the AND memory is ``1'' and the corresponding bit in the OR memory is 10''.

This means that data ``1'' or θ'') has never been written to the corresponding bit of the target memory. If such a memory in which data has never been written is read, "1" is output to the non-initialized memory read detection signal 16 which is the output of the AND gate 15. In other words, '1' is applied to the non-initialized memory read detection signal 16.
'' is output, it means that uninitialized memory was read.

In order to stop the device operating the target memory at the time when the uninitialized memory is read next, the non-initialized memory detection signal 16 is used as a request to stop the operation of the device operating the target memory. Just connect it to the signal input. For example, if the target memory is being modified by a microprocessor called 8080 developed by Intel, the non-initialized memory read detection signal 16 can be connected to the HOLD terminal of the 8080 processor. It's fine. By doing this, when the non-initialized memory read detection signal 16 is output, the 8080 processor interrupts the execution of the program.

Further, if the device is configured with hard-wired logic, the device may be configured to stop its operating clock when the non-initialized memory read detection signal 16 is output.

FIG. 3 is one of the objects of the present invention. '1'or'
This is a block diagram of one embodiment of a device for detecting bits of memory that have not been written. Signals in FIG. 3 that are the same as in FIG. The embodiment shown in Fig. 3 is similar to A of the embodiment shown in Fig. 1.
It is represented in the form of an accessory device connected to the ND data bus 8 and the 0 data bus 9. Also, the @1'' detection units 500, 510, 520, and 530 all have the same configuration, and the internal configuration is shown with 500 as a representative.Similarly, the ``0'' detection units 600, 610゜62
0.630 also has the same circuit configuration, with 600 as a representative,
It shows its internal configuration.

11" The detection unit 500 has %OBOR data 80
One bit and the corresponding bit of the AND data path are input and they are input to AND gate 502. The output of the AND gate 502 is directly derived as the output of the 1" detection unit 500, and becomes the '1" detection pit signal 550. '''l'' detection unit 500,5
The output of 10,520°530 is OR, gate 540
, and its output is output as a "1" detection signal 541.

O” detection unit 600 includes an OR data path 801
and the corresponding AND data bus bits are input to inverters 602 and 60, respectively.
After the phase is inverted by 1.

It is input to AND gate 603. AND gate 603
The output of is derived as a ``'θ'' detection bit signal 650. 10” detection unit) 600,610°620.63
The output of 0 is input to the OR gate 640 and @O″
A detection signal 641 is obtained.

Next, a concrete usage method of the embodiment shown in FIG. 3 will be described.

The block diagram of the embodiment shown in FIG.

It is used connected to the block diagram of FIG. For example, if we assume that the block diagram in Figure 1 is connected to a microcomputer program development/evaluation device, then when the program evaluation is completed, all addresses in the target memory will be When performing an operation to read the contents, if there is a memory bit that was set only by 1 degree during evaluation of the program, the OR, memory bit, and AND memory bit corresponding to that bit will be ''. 1" should have been written. In this case, when a read operation is performed on that bit, the output of the 1" detection unit corresponding to that bit becomes '1', and the 1" detection signal which is the output of the OR gate 540 541 is output. In other words, @l”
By monitoring the detection signal 541, it is possible to know whether there is a memory in which only '1' was written during evaluation.

If you need to know the location of the bit in the memory where only @1" is written, use the 11" detection signal 541.
@1” detection bit signal 550, 55
1,552,553 should be determined.

Similarly, to check whether there is a left or right memory in which only 0" has been written, the 0" detection signal 640 is determined while reading the target memory.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to know the data writing history of the memory to be monitored. It is possible to detect 'references' (, '0' or '1')
It is possible to know which bits of memory have only been written to. Therefore, the application of the present invention to a microcomputer evaluation device brings about a great effect in detecting bugs in Eri programs.

In the example shown in FIG. 1, the data width is 4 bits, but this is simply the bit width of the target memory of
This is because the bits are fixed, and it goes without saying that any bit length can be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a non-initialized memory detector according to the present invention, FIG. 2 is a timing diagram thereof, and FIG.
A block diagram of the detection unit of a memory in which only 1" has been written is 66° 1......-it write address, 2......a
Extrusion address, 3... Selection circuit, 4...
... Address selection signal, 5 ... Address bus, 6 ... Test memory, 7 ... Test memory write signal, 8 ... AND data bus,
9...OR data e-bus, 10...gate signal, 11...data bus, 12...
...Mask data path, 13 ... Rough clock, 14 ... Read mode signal, 1
5...AND gate, 100, 110, 120
, 130... Read data unit, 10
1...Inverter, 102...AND
Gate, 140...OR gate, 200. 210.220,230...Write data
Unit, 201... Inverter, 202...
...OR gate, 203...AND gate, 204...AND gate, 300.400.
...Latch, 301, 401 ...
3-state buffer, 500-. 510, 520° 530...1" detection unit), 502...
・・AND gate, 551, 552, 553, 554
・・・・・・″1@Detection Pit Ig No. 540...
...0 gate, 541..."1" detection signal,
600, 610, 620, 630..."0"' detection unit, 601, 6Q2...Inverter, 60
3...AND gate, 650,651°653
...-'O" detection bit signal, 0 for 640...
641...-0" detection signal. Agent: Patent attorney Susumu Uchihara c5, W

Claims (4)

[Claims] (1) A device for monitoring data of a memory operation device comprising a first memory in which data can be written and read, and a control device that operates the first memory,
a second memory consisting of bits having a one-to-one correspondence with each bit of the first memory and having an initial value of “0”; and a second memory consisting of bits having a one-to-one correspondence with each bit of the first memory and having an initial value of “0”; is "1", and when the control device performs a data write operation to the first memory, the bit of the second memory corresponding to the bit that participated in the write operation is provided. stores the result of performing an OR operation between the write data to the first memory and the contents of the corresponding bit of the second memory, and stores the result of the logical sum operation between the write data to the first memory and the contents of the corresponding bit of the second memory, and stores the write data and the Performs an AND operation with the contents of the corresponding bit in the third memory, and stores the result in the third memory.
means for performing an operation of writing to a corresponding bit of the memory, and when the control device performs a read operation on the first memory, the first memory that participated in the read
non-initialized memory detection means for detecting whether the content of a bit in a second memory corresponding to the bit in the memory is "0" and the content in a bit in a corresponding third memory is "1"; A data monitoring device characterized by comprising: (2) The non-initialized memory detecting means detects that the content of the bit of the second memory corresponding to the bit of the first memory that participated in the read operation is "0", and the content of the bit of the corresponding third memory is "0".
Claim (1) further comprising means for stopping the operation of the memory manipulation device when it is detected that the bit content of the memory is "1". Data monitoring equipment. (3) The scope of claim 1 is characterized in that it includes means for detecting whether or not the content of the third memory corresponding to the bit whose content is "0" in the second memory is "0". 1)
Data monitoring device as described in Section. (4) Claims characterized by comprising means for detecting whether the content of the bit in the second memory corresponding to the bit in the third memory is "1". The data monitoring device according to paragraph (1).