JPS6218769A - Vertical type semiconductor device and manufacture thereof - Google Patents
Vertical type semiconductor device and manufacture thereofInfo
- Publication number
- JPS6218769A JPS6218769A JP60157821A JP15782185A JPS6218769A JP S6218769 A JPS6218769 A JP S6218769A JP 60157821 A JP60157821 A JP 60157821A JP 15782185 A JP15782185 A JP 15782185A JP S6218769 A JPS6218769 A JP S6218769A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- semiconductor
- insulating film
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012212 insulator Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims description 23
- 230000003647 oxidation Effects 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000007704 transition Effects 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 230000007423 decrease Effects 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 10
- 239000012535 impurity Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910021357 chromium silicide Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- -1 molybdenum silicide Chemical compound 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 210000000496 pancreas Anatomy 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、縦形構造Ｍｉｓ型半導体装附等の縦形半導体
装置及びその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical semiconductor device, such as a vertically structured Mis-type semiconductor device, and a method for manufacturing the same.
従来の技術
Ｍｌ’３型半導体装置のうち、特にＭＯＳ ＦＥＴ（
絶縁ゲート型電界効果トランジスタ）は低耐圧、低電力
用デバイスとして良く知られていたが、最近では高耐圧
、大電力設計が可能となり、現在ではパワーデバイスと
しても使用されるようになった。Among conventional Ml'3 type semiconductor devices, especially MOS FET (
Insulated gate field effect transistors (insulated gate field effect transistors) were well known as low-voltage, low-power devices, but recently they have become capable of high-voltage, high-power designs, and are now being used as power devices.
次に、従来の高耐圧パワーＭＯ８ＦＥＴとして知られて
いるＤ Ｓ Ａ （Ｄｌｆｆｕｓｌｔｌｏｎ Ｓｅｌｆ
−Ａｌｌ−ｇｎｍｅｎｔ）構造のＦＥＴ（以下Ｄ−ＭＯ
３ＦＥＴと称する）の製造方法について第３図を参照し
て説明する。Next, DSA (Dlffusltlon Self), which is known as a conventional high voltage power MO8FET
-All-gnment) structure FET (hereinafter referred to as D-MO
3FET) will be described with reference to FIG.
副型半導体基板１上にｎ型エピタキシャル成長層２を例
えば比抵抗／θ〜２ＳΩの、厚み３０〜６０μｍ形成後
、表面からＰ 型半導体層８を形成する。その後、ゲー
ト酸化膜５ａを約１０００人形成した様子を第３図（Ａ
ｌに示す。After forming an n-type epitaxial growth layer 2 on a sub-type semiconductor substrate 1, having a resistivity of, for example, /θ to 2 SΩ and a thickness of 30 to 60 μm, a P-type semiconductor layer 8 is formed from the surface. After that, about 1000 people formed the gate oxide film 5a in Figure 3 (A
Shown in l.
次に、ゲート電極となる多結晶シリコンノ９ター７６を
例えば乙０００人の厚さで形成しパターンが形成されて
いない部分を開口窓として、ここにＰ型不純物、例えば
ボロンをイオンインプラし拡散処理を行うことにより開
口部の下方にＰ型半導体層４を形成する。この様子を、
第３図（Ｂｌに示す。Next, a polycrystalline silicon layer 76 that will become the gate electrode is formed to a thickness of, for example, 1,000 mm, and the part where the pattern is not formed is used as an opening window, and a P-type impurity, such as boron, is ion-implanted and diffused. By performing the treatment, a P-type semiconductor layer 4 is formed below the opening. This situation,
Figure 3 (shown in Bl).
このＰ型半導体層４がチャンネル領域となる部分である
。This P-type semiconductor layer 4 is a portion that becomes a channel region.
次に、前記開口部の中間部にフォトプロセスによシレジ
スト膜７を形既し、これら多結晶シリコンノＪ？ターン
６とレジスト膜パターン７が形成されていない部分の酸
化膜５ａをエツチングにより除去する。この様子を第３
図（Ｃ１に示す。Next, a resist film 7 is formed in the middle part of the opening by a photo process, and the polycrystalline silicon film 7 is formed in the middle part of the opening. The portions of the oxide film 5a where the turns 6 and the resist film pattern 7 are not formed are removed by etching. This situation can be seen in the third
Figure (shown in C1).
次に、イオンインプラによシｎ 型不純物、例えばリン
又は砒素等を打込みその後熱拡散、熱酸化を行うことに
よってＰ型チャンネル領域上に計型半導体Ｎ（ソース領
域）８が形成される。この様子を第３図（０）に示す。Next, a semiconductor N (source region) 8 is formed on the P-type channel region by implanting an n-type impurity, such as phosphorus or arsenic, by ion implantation and then performing thermal diffusion and thermal oxidation. This situation is shown in FIG. 3(0).
その後ＣＶＤ法にてＰＳＧ膜５Ｃを例えばｇｏｏｏ人の
厚さで形成する。この様子を第３図（Ｅ）に示す。Thereafter, a PSG film 5C is formed to have a thickness of, for example, about 100 mm using the CVD method. This situation is shown in FIG. 3(E).
次に、Ｐ＋型ソース領域８上の部分を異方性のエツチン
グを行うことによ、９ｐｓＧ膜５Ｃを除去して開口部を
形成し、その後、アルミ電極膜９を形成して、第３図（
Ｆ）に示す如き構造を得る。第り図は、第３図（Ｆｌの
構造を平面図にて示しておシ、第３図（Ｆ）は、第７図
のＡ −Ａ’ 線断面図である。Next, by performing anisotropic etching on the portion above the P+ type source region 8, the 9psG film 5C is removed to form an opening, and then an aluminum electrode film 9 is formed, as shown in FIG. (
A structure as shown in F) is obtained. Figure 3 shows the structure of Figure 3 (Fl) in a plan view, and Figure 3 (F) is a sectional view taken along the line A-A' in Figure 7.
発明が解決しようとする問題点
従来構造において、スイッチングスピードヲ増す方法と
して、チャンネル長を小さくし、相互コンダクタンスＰ
７Ｆ！ を大きくする方法のほかに、ゲート絶縁膜を
薄くする方法がある。この方法によるとゲート絶縁膜が
薄いため、しきい値電圧が小さくなシ、スイッチングス
ピードも増すが、それに伴なって、ゲート・ドレイン間
の容量が増大し、むしろ最終的にはスイッチングスピー
ドが遅くなってしまう。また、他の方法として、ゲート
抵抗と呼ばれる、ゲート電極の配線抵抗を小さくするこ
とによって、更に効率よくスイッチングスピ−ドを向上
させることが可能である。しかしながら、一般的には、
従来構造のＤ−ＭＯＳ ＦＥＴのゲート電極材料は、
シリコンゲートと呼ばれ、多くは多結晶シリコン膜を用
いている。ゲート抵抗を下げるために多結晶シリコン膜
を厚くする場合には、この多結晶シリコン膜上に絶縁膜
を介して設けられるソースＡｅ 電極が、その多結晶シ
リコン膜の厚さのために断切れしてしまうことがあった
。Problems to be Solved by the Invention In the conventional structure, as a method of increasing the switching speed, the channel length is reduced and the transconductance P is reduced.
7F! In addition to the method of increasing the gate insulating film, there is a method of making the gate insulating film thinner. This method reduces the threshold voltage and increases the switching speed because the gate insulating film is thin, but this also increases the capacitance between the gate and drain, which ultimately slows down the switching speed. turn into. Furthermore, as another method, it is possible to improve the switching speed more efficiently by reducing the wiring resistance of the gate electrode, which is called gate resistance. However, in general,
The gate electrode material of D-MOS FET with conventional structure is
It is called a silicon gate, and many use a polycrystalline silicon film. When increasing the thickness of a polycrystalline silicon film to lower gate resistance, the source Ae electrode provided on the polycrystalline silicon film via an insulating film may be cut off due to the thickness of the polycrystalline silicon film. There were times when I ended up.
更Ｋまた、従来のＤ−ＭＯＳ ＦＥＴは、同一の拡散
窓からチャンネル領域の不純物拡散とソース領域の不純
物拡散を行なっている。そのため、チャンネル領域に濃
度勾配が生じ、ソースｎ＋型不純物拡散の不均一性によ
ってしきい値電圧のバラツキが生じ、生産性コストを著
しく低下させていた。Furthermore, in the conventional D-MOS FET, impurity diffusion in the channel region and impurity diffusion in the source region are performed from the same diffusion window. As a result, a concentration gradient occurs in the channel region, and variations in threshold voltage occur due to non-uniform diffusion of the source n+ type impurity, resulting in a significant reduction in productivity costs.
その上、従来構造では、極めて薄いゲート酸化膜上にゲ
ート電極用の多結晶シリコンパターンを配置しており、
ゲート多結晶シリコンパターンエツジに電界が集中して
、充分なｒ−ト耐圧が得られず、また、ゲート酸化膜の
破壊が生じ、ゲート耐圧が零となってしまうこともしば
しば生じていた。Furthermore, in the conventional structure, a polycrystalline silicon pattern for the gate electrode is placed on an extremely thin gate oxide film.
The electric field concentrates on the edge of the gate polycrystalline silicon pattern, making it impossible to obtain a sufficient r-to-breakdown voltage, and the gate oxide film is often destroyed, resulting in the gate breakdown voltage becoming zero.
本発明の目的は、前述したような従来技術の問題点を解
消した縦形半導体装置及びその製造方法を提供すること
である。SUMMARY OF THE INVENTION An object of the present invention is to provide a vertical semiconductor device and a method for manufacturing the same that eliminate the problems of the prior art as described above.
問題点を解決するだめの手段
本発明によれば、一導電型の半導体基体の主面上に絶縁
膜を介してゲート電極を有し該ｙ−ト電極のパターンエ
ツジに沿った前記半導体基体の主面にチャンネル領域と
ソース領域とを有し、前記半導体基体をドレイン領域と
する縦形半導体装直において、前記ゲート電極の中心部
は、そのゲート電極の厚さより厚い絶縁物によって分断
されており、該絶縁物の前記分断部に隣接した部分の上
面は、前記ゲート電極の上面へ滑めらかに移行する形状
とされる。Means for Solving the Problems According to the present invention, a gate electrode is provided on the main surface of a semiconductor substrate of one conductivity type with an insulating film interposed therebetween, and a gate electrode is formed on the semiconductor substrate along the pattern edge of the y-to-electrode. In a vertical semiconductor device having a channel region and a source region on a main surface and having the semiconductor substrate as a drain region, the center portion of the gate electrode is divided by an insulator thicker than the thickness of the gate electrode, The upper surface of a portion of the insulator adjacent to the divided portion has a shape that smoothly transitions to the upper surface of the gate electrode.
また、本発明によれば、前述したような構造の縦形半導
体装置の製造方法は、前記一導電型の半導体基体を準備
し、該半導体基体の主面に選択的に該半導体基体とは逆
導電型の第７半導体層を形成する工程と、前記半導体基
体の主面上に前記絶縁膜となる第１絶縁膜を形成する工
程と、該第１絶縁膜上に前記ゲート電極となる第１半導
体膜を形成する工程と、該第１半導体膜上に耐酸化絶縁
膜を形成する工程と、前記ｃ−ト＝極を形成すべき前記
第１半導体膜の上に前記耐酸化絶縁膜を残すように前記
耐酸化絶縁膜を選択的にエツチングする工程と、該耐酸
化絶縁膜をエツチングした部分の前記第１半導体膜を酸
化して前記ゲート１ｇ極を分断する前記絶縁物を形成す
る工程と、前記第１半導体膜を拡散マスクに、前記半導
体基体とは逆導電型であって前記第１半導体層よりは濃
度の低い前記チャンネル領域を形成する第２半導体層を
形成し、前記半導体基体と同じ導電型であって前記第λ
半導体層よりも浅い前記ソース領域となる第３半導体層
を形成する工程とを含む。Further, according to the present invention, a method for manufacturing a vertical semiconductor device having the above-described structure includes preparing a semiconductor substrate of one conductivity type, and selectively applying a conductivity opposite to that of the semiconductor substrate to the main surface of the semiconductor substrate. forming a first insulating film that will become the insulating film on the main surface of the semiconductor substrate; and forming a first semiconductor layer that will become the gate electrode on the first insulating film. a step of forming a film, a step of forming an oxidation-resistant insulating film on the first semiconductor film, and a step of leaving the oxidation-resistant insulating film on the first semiconductor film where the c-to=pole is to be formed. a step of selectively etching the oxidation-resistant insulating film, and a step of oxidizing the first semiconductor film in the etched portion of the oxidation-resistant insulating film to form the insulator that divides the gate 1g electrode; Using the first semiconductor film as a diffusion mask, a second semiconductor layer forming the channel region is formed which has a conductivity type opposite to that of the semiconductor body and has a lower concentration than the first semiconductor layer, and has a conductivity type that is the same as that of the semiconductor body. conductivity type and the λth
forming a third semiconductor layer that is shallower than the semiconductor layer and becomes the source region.
実施例
次に、添付図面の第１図及び第２図に基づいて本発明の
実施例について本発明をより詳細に説明する。Embodiments Next, the present invention will be described in more detail with reference to embodiments of the present invention based on FIGS. 1 and 2 of the accompanying drawings.
第１図（Ａ）から（Ｆｌは、本発明の一実施例としての
ＤＳＡ−ＭＯＳ ＦＥＴの製造工程を説明するための
断面構造図である。以下、この第１図を参照して、本発
明のこの実施例の製造方法について説明する。FIGS. 1A to 1F are cross-sectional structural diagrams for explaining the manufacturing process of a DSA-MOS FET as an embodiment of the present invention.Hereinafter, referring to FIG. The manufacturing method of this example will be explained.
まず、ｎ＋型半導体基板１上に、これよりも低濃度のｎ
型半導体層２を形成後、選択的にＰ＋型拡散層８を形成
した後、表面にゲート酸化膜５ａを、例えば、１ｏｏｏ
人の厚さで形威し、更にその上に５ｏｏｏＡの厚さでゲ
ート電極用多結晶シリコン膜６を形成し、更にその上に
耐酸化絶縁膜１１を形成する。この様子を第１図（Ａ）
に示している。続いて、第１図（Ｂ）に示すように、フ
ォトエツチング技術によって耐酸化絶縁膜１１を選択的
にエツチングする。この耐酸化絶縁膜の選択エツチング
は、例えば、フレオンガスと水素ガスの混合ガスエッチ
ャントを用いて、リアクティブイオンエツチングを行な
うことによって行なわれ、ゲート電極として多結晶シリ
コン膜６を残すべき位置に耐酸化絶縁膜１１を残すよう
にする。First, a lower concentration of n than this is deposited on the n+ type semiconductor substrate 1.
After forming the type semiconductor layer 2, and selectively forming the P+ type diffusion layer 8, a gate oxide film 5a is formed on the surface, for example, 1ooo.
A polycrystalline silicon film 6 for a gate electrode is formed on the polycrystalline silicon film 6 to a thickness of 500A, and an oxidation-resistant insulating film 11 is further formed on it. This situation is shown in Figure 1 (A).
It is shown in Subsequently, as shown in FIG. 1(B), the oxidation-resistant insulating film 11 is selectively etched using a photoetching technique. This selective etching of the oxidation-resistant insulating film is performed by performing reactive ion etching using, for example, a mixed gas etchant of Freon gas and hydrogen gas, and the oxidation-resistant insulating film is etched at the position where the polycrystalline silicon film 6 is to be left as the gate electrode. The insulating film 11 is left.
続いて、第１図（Ｃ）に示すように、酸化工程を施し、
露出した部分の多結晶シリコン）ｌａ６（ｎ型半導体層
２の一部を含んでもよい）を選択的に酸化し、約／μｍ
の厚みの酸化膜５ ｄ、及び５ｄ２を形成する。この際
、特に、ゲート電極となる多結晶シリコン膜６を分断し
ている絶縁物となる酸化膜５ ｄ、 は、その多結晶
シリコン膜６の厚さより厚くされていて、この酸化膜５
ｄ、 の分断部、すなわち多結晶シリコン膜６に隣
接した部分の上面は、それら多結晶シリコン膜６の上面
へ滑めらかに移行する形状とされる。Subsequently, as shown in FIG. 1(C), an oxidation step is performed,
The exposed portion of polycrystalline silicon (polycrystalline silicon) la6 (which may include a part of the n-type semiconductor layer 2) is selectively oxidized, and the
Oxide films 5d and 5d2 are formed to have a thickness of . At this time, in particular, the oxide film 5d, which is an insulator and which divides the polycrystalline silicon film 6 which becomes the gate electrode, is made thicker than the thickness of the polycrystalline silicon film 6.
The upper surface of the divided portion d, that is, the portion adjacent to the polycrystalline silicon film 6 is shaped to smoothly transition to the upper surface of the polycrystalline silicon film 6.
次に、フォトエツチング技術によって酸化膜５ｄ２ を
選択的にエツチングし、酸化膜５ｄ２ をエツチングし
た部分に再度約ＳＯＯ人の厚の酸化膜５ｅを形成する。Next, the oxide film 5d2 is selectively etched using a photoetching technique, and an oxide film 5e having a thickness of approximately SOO is again formed on the etched portion of the oxide film 5d2.
そして、イオン注入を施してチャンネル領域を形成する
Ｐ型半導体虐４を形成する。この様子を第１図（０）に
示している。Then, ion implantation is performed to form a P-type semiconductor layer 4 that will form a channel region. This situation is shown in FIG. 1(0).
その後、第１図（ε）に示すように、選択的にソース層
型半導体層８を形成し、再度酸化工程を施し、約−０θ
θＡの酸化膜５ｆを選択的に形成して、その後、耐酸化
絶縁膜１１をエツチング除去する。Thereafter, as shown in FIG. 1 (ε), a source layer type semiconductor layer 8 is selectively formed and an oxidation process is performed again to approximately -0θ
An oxide film 5f of θA is selectively formed, and then the oxidation-resistant insulating film 11 is removed by etching.
次に、第１図（Ｆ）に示すように、ＣＶＯ法にて、ＰＳ
Ｇ膜５Ｃを、例えば、！ｒ００θ人の厚みで形成し、熱
処理を施し、その後、コンタクトホールを開口して、Ａ
ｅ 金属電Ｓ膜９を、例えば、３．５μｍ程度の厚さ
に選択的に形成してＤ Ｓ Ａ −ＭＯ’５ＦＥＴを完
成する。この実施例では、酸化膜５ｆは、ゲート電極６
の絶縁物５ ｄ、 の反対側のパターンエツジの側に
残されている。Next, as shown in Fig. 1 (F), PS is
G film 5C, for example! A
e The metal electric S film 9 is selectively formed to have a thickness of, for example, about 3.5 μm to complete the DSA-MO'5FET. In this embodiment, the oxide film 5f is the gate electrode 6
Insulator 5d, left on the side of the pattern edge opposite to .
第２図は、本発明による別の実施例としてのＤＳＡ−Ｍ
ＯＳ ＦＥＴの断面構造を示す第１図（Ｆ）と同様の
図である。この第２図のＤ ’３ Ａ −ＭＯＳＦＥＴ
では、特に、ゲート配線抵抗を下げるために、絶縁物５
ｄ、 によって分断された多結晶シリコンゲート電
極６を、それらゲート電極６及び絶縁物５ ｄ、 上
に形成した゛ゲート電極膜としての多結晶シリコン膜６
ｂによって相互接続している。FIG. 2 shows a DSA-M as another embodiment according to the present invention.
FIG. 2 is a diagram similar to FIG. 1(F) showing the cross-sectional structure of an OS FET. This D '3 A-MOSFET in Fig. 2
In particular, in order to lower the gate wiring resistance, the insulator 5 is
A polycrystalline silicon film 6 as a gate electrode film is formed on the gate electrodes 6 and the insulator 5d.
interconnected by b.
その他の点は、第１図に関して説明した実施例と同様で
あるので繰ヤ返し説明しない。Other points are similar to the embodiment described with reference to FIG. 1, and therefore will not be described again.
本発明は、前述したような実施例に限定されるものでな
く、例えば、第１図（８１に関して説明した製造工程に
おいて、耐酸化絶縁膜１１をマスクに選択的に多結晶シ
リコン膜６を酸化する際、多結晶シリコン膜６を耐酸化
絶縁膜をマスクにエツチングしてから酸化工程を行なっ
ても良い。更にまたチャンネル飴域となるＰ型半導体層
４を形成する際、耐酸化絶縁［１１を除去した後、穿出
した多結晶シリコンパターン６をマスクにイオン注入で
Ｐ型半導体盾４を形成し、更にソース層型半導体層を形
成し、その上に、ＣＶＤｇＪ？５Ｃを堆積し、コンタク
トホールを形成して＾ｇ 金属電極膜９を形成するよう
にしてもよい。The present invention is not limited to the embodiments described above, and, for example, in the manufacturing process described with reference to FIG. In this case, the oxidation process may be performed after etching the polycrystalline silicon film 6 using the oxidation-resistant insulating film as a mask.Furthermore, when forming the P-type semiconductor layer 4 that will become the channel candy region, the oxidation-resistant insulating film [11 After removing the polycrystalline silicon pattern 6, a P-type semiconductor shield 4 is formed by ion implantation using the drilled polycrystalline silicon pattern 6 as a mask, and a source layer type semiconductor layer is further formed. The metal electrode film 9 may be formed by forming holes.
また、前述した実施例において、耐酸化絶縁膜１１は、
シリコンチツ化膜やアルミナ膜等であってよい。また、
ゲート電極膜６及び６ｂとしては、多結晶シリコン膜の
代りに、モリブデンシリサイド、チタンシリサイド、ク
ロムシリサイド、ニッケルシリサイド等のメタルシリサ
イドを使用してもよいし、ゲート電極膜６ｂとしては、
更に高融点メタルを使用してもよい。Furthermore, in the embodiment described above, the oxidation-resistant insulating film 11 is
It may be a silicon dioxide film, an alumina film, or the like. Also,
As the gate electrode films 6 and 6b, metal silicide such as molybdenum silicide, titanium silicide, chromium silicide, nickel silicide, etc. may be used instead of the polycrystalline silicon film, and as the gate electrode film 6b,
Furthermore, high melting point metals may be used.
更Ｋまた、前述した実施例において、各半導体ｊ−のＰ
型とｎ型とは逆にしても良い。また、多結晶シリコンに
は、ｎ又はＰ型不純物イオンがドーグされる。Further, in the above-mentioned embodiment, P of each semiconductor j-
The type and n-type may be reversed. Further, polycrystalline silicon is doped with n- or p-type impurity ions.
発明の効果
前述したように、本発明の一縦形半導体装ｔ／ｉでは、
ゲート′醒極６の中心部に、これらゲート電極６の厚さ
より厚い絶縁物５ ｄ、 を設け、しかも、その絶縁
物５ ｄ、 のゲート電極６に１４接した部分の上面
を、ゲート電極６の上面へ滑めらかに移行する形状とし
ているため、ゲート・ドレイン間の容量を減らしスイッ
チングスピードを向上させることができる上、それらゲ
ート電極６及び絶縁物５ｄ。Effects of the Invention As mentioned above, in the single vertical semiconductor device t/i of the present invention,
An insulator 5d, which is thicker than the gate electrodes 6, is provided at the center of the gate electrode 6, and the upper surface of the insulator 5d, which is in contact with the gate electrode 6, is connected to the gate electrode 6. Since it has a shape that smoothly transitions to the upper surface, it is possible to reduce the capacitance between the gate and drain and improve the switching speed.
の上に形成するソース用Ａｅ硯極９に断切れを生ずるお
それもなくなる。There is also no risk of breakage occurring in the source Ae inkstone electrode 9 formed on the source.
その上、本発明の前述した製造方法によれば、絶縁物と
しての酸化膜５ ｄ、 は自己整合的に形成され、酸
化膜５ ｄ、 の両側には同じ）４ターンサイズのゲ
ート多結晶シリコン６が形成されることになり、これら
多結晶シリコンｆ−トロは、チャンネル長に比例して形
成すれば良いため、例えば、相互コンダクタンス２ｍを
大きくするためチャンネル長を狭めた榊造とした場合、
ゲート多結晶シリコンツヤターン幅も小さくすることが
できる。このことは、ゲート・ソース間容量の減少にも
つながり、そのため、ゲート絶縁膜も従来より薄くする
ことができ、よりスイッチングスピードを向上させる上
で有利である。Moreover, according to the above-described manufacturing method of the present invention, the oxide film 5d, as an insulator is formed in a self-aligned manner, and on both sides of the oxide film 5d, a gate polycrystalline silicon film of the same 4-turn size is formed. 6 will be formed, and these polycrystalline silicon f-toros can be formed in proportion to the channel length. For example, if the channel length is narrowed to increase the mutual conductance of 2 m,
The gate polycrystalline silicon gloss turn width can also be reduced. This also leads to a reduction in the capacitance between the gate and the source, and therefore the gate insulating film can also be made thinner than before, which is advantageous in further improving the switching speed.
また、前述した本発明の実施例では、ゲート多結晶シリ
コンパターン６の一方の側に、酸化工程により絶縁物で
ある約／μｍ厚の酸化膜５ ｄ、 を形成し、他方の
側にも酸化工程により約＝００θＡの淳さの酸化膜５ｆ
を形成しているだめ、周知ノ如くゲート多結晶シリコン
パターン６のエツジ部はそれら酸化工程によって酸化さ
れて丸くされる。従って、ｒ−ト多結晶シリコン６のパ
ターンエツジにおける電界集中を減少させることができ
、ｙ−ト耐圧の大きな素子とすることができる。In addition, in the embodiment of the present invention described above, an oxide film 5d, which is an insulator, is formed on one side of the gate polycrystalline silicon pattern 6 by an oxidation process and has a thickness of about 1 μm, and the other side is also oxidized. Depending on the process, the oxide film 5f has a thickness of about 00θA.
As is well known, the edges of the gate polycrystalline silicon pattern 6 are oxidized and rounded by the oxidation process. Therefore, it is possible to reduce electric field concentration at the pattern edges of r-to polycrystalline silicon 6, and it is possible to provide an element with a high y-toto breakdown voltage.
第１図（Ａ）から（Ｆ）は、本発明の一実施例としての
ＤＳＡ−ＭＯＳ ＦＥｖｃＤ［！ｍ工ａｅｍ８Ｌｆる
＊めの断面構造図、第２図は本発明の別の央＃ｉ例とし
てのＤＳＡ−ＭＯＳ ＦＥＴの断面構造内、第３図（
Ａｌから（Ｆ）は従来のＤＳＡ−ＭＯＳ ＦＥＴの製
造方法の一例を説明するための断面構造図、第ダ図は第
３図軸）に示すＤＳＡ−ＭＯＳ ＦＥＴの部分千圃図
である。
１・・・・・・計型手導体基体、 ２・・・・・・ｎ
型エピタキシャル層、 ８・・・・・・Ｐ＋型半導体層
、４・・・・・・Ｐ型半導体層、 ５ａ・・・・・−
ｒ−ト酸化膜、５ ｄ＋ ｅ ５ ｆ−−・−ａ化膵、
５ ｃ ・−ＣＶ Ｄ ｇ、６・・・・・・多結晶シ
リコン膜、 ６ｂ・・・・・・多結晶シリコン膜、
８・・−・・ｎ＋型型半体体層 ９・・・・・・金禍電
極膜、 １１・・・・−耐酸化絶縁膜。
第３図FIGS. 1(A) to (F) show a DSA-MOS FEvcD[! as an embodiment of the present invention. Figure 2 shows the cross-sectional structure of a DSA-MOS FET as another example of the present invention, and Figure 3 (
Al to (F) are cross-sectional structural diagrams for explaining an example of a conventional method of manufacturing a DSA-MOS FET, and Fig. 3 (D) is a partial cross-sectional view of the DSA-MOS FET shown in Fig. 3 (axis). 1...meter-type hand conductor base, 2...n
type epitaxial layer, 8...P+ type semiconductor layer, 4...P type semiconductor layer, 5a...-
r-to oxide film, 5 d+ e 5 f--・-a pancreas,
5 c ・-CV D g, 6... Polycrystalline silicon film, 6b... Polycrystalline silicon film,
8...N+ type half body layer 9...Kinka electrode film, 11...-oxidation-resistant insulating film. Figure 3
Claims (6)
ゲート電極を有し該ゲート電極のパターンエッジに沿つ
た前記半導体基体の主面にチャンネル領域とソース領域
とを有し、前記半導体基体をドレイン領域とする縦形半
導体装置において、前記ゲート電極の中心部は、そのゲ
ート電極の厚さより厚い絶縁物によつて分断されており
、該絶縁物の前記分断部に隣接した部分の上面は、前記
ゲート電極の上面へ滑めらかに移行する形状とされてい
ることを特徴とする縦形半導体装置。(1) having a gate electrode on the main surface of a semiconductor substrate of one conductivity type via an insulating film, and having a channel region and a source region on the main surface of the semiconductor substrate along the pattern edge of the gate electrode; In the vertical semiconductor device in which the semiconductor substrate is used as a drain region, the center portion of the gate electrode is divided by an insulator thicker than the thickness of the gate electrode, and a portion of the insulator adjacent to the divided portion is divided. A vertical semiconductor device characterized in that an upper surface has a shape that smoothly transitions to an upper surface of the gate electrode.
れらゲート電極及び絶縁物上に形成されたゲート電極膜
によつて相互接続されている特許請求の範囲第（１）項
記載の縦形半導体装置。(2) The vertical type according to claim (1), wherein the gate electrodes separated by the insulator are interconnected by a gate electrode film formed on the gate electrodes and the insulator. Semiconductor equipment.
前記パターンエッジの側にも酸化膜が形成されている特
許請求の範囲第（１）項又は第（２）項記載の縦形半導
体装置。(3) The vertical semiconductor according to claim (1) or (2), wherein the insulator is an oxide film, and an oxide film is also formed on the pattern edge side of the gate electrode. Device.
囲第（１）項又は第（２）項又は第（３）項記載の縦形
半導体装置。(4) The vertical semiconductor device according to claim (1), (2), or (3), wherein the gate electrode is a semiconductor film.
点メタルである特許請求の範囲第（２）項又は第（３）
項記載の縦形半導体装置。(5) Claim (2) or (3), wherein the gate electrode film is metal silicide or a high melting point metal.
Vertical semiconductor device described in Section 1.
ゲート電極を有し該ゲート電極のパターンエッジに沿つ
た前記半導体基体の主面にチャンネル領域とソース領域
とを有し、前記半導体基体をドレイン領域とし、前記ゲ
ート電極の中心部は、そのゲート電極の厚さより厚い絶
縁物によつて分断されており、該絶縁物の前記分断部に
隣接した部分の上面は、前記ゲート電極の上面へ滑めら
かに移行する形状とされている縦形半導体装置の製造方
法において、前記一導電型の半導体基体を準備し、該半
導体基体の主面に選択的に該半導体基体とは逆導電型の
第１半導体層を形成する工程と、前記半導体基体の主面
上に前記絶縁膜となる第１絶縁膜を形成する工程と、該
第１絶縁膜上に前記ゲート電極となる第１半導体膜を形
成する工程と、該第１半導体膜上に耐酸化絶縁膜を形成
する工程と、前記ゲート電極を形成すべき前記第１半導
体膜の上に前記耐酸化絶縁膜を残すように前記耐酸化絶
縁膜を選択的にエッチングする工程と、該耐酸化絶縁膜
をエッチングした部分の前記第１半導体膜を酸化して前
記ゲート電極を分断する前記絶縁物を形成する工程と、
前記第１半導体膜を拡散マスクに、前記半導体基体とは
逆導電型であつて前記第１半導体層よりは濃度の低い前
記チャンネル領域を形成する第２半導体層を形成し、前
記半導体基体と同じ導電型であつて前記第２半導体層よ
りも浅い前記ソース領域となる第３半導体層を形成する
工程とを含むことを特徴とする縦形半導体装置の製造方
法。(6) having a gate electrode on the main surface of a semiconductor substrate of one conductivity type via an insulating film, and having a channel region and a source region on the main surface of the semiconductor substrate along the pattern edge of the gate electrode; The semiconductor substrate is used as a drain region, the center portion of the gate electrode is divided by an insulator thicker than the thickness of the gate electrode, and the upper surface of a portion of the insulator adjacent to the divided portion is connected to the gate electrode. In a method for manufacturing a vertical semiconductor device having a shape that smoothly transitions to the upper surface of an electrode, the semiconductor substrate of one conductivity type is prepared, and the main surface of the semiconductor substrate is selectively coated with the semiconductor substrate. forming a first semiconductor layer of opposite conductivity type; forming a first insulating film to become the insulating film on the main surface of the semiconductor substrate; and forming a first insulating film to become the gate electrode on the first insulating film. a step of forming a first semiconductor film, a step of forming an oxidation-resistant insulating film on the first semiconductor film, and a step of leaving the oxidation-resistant insulating film on the first semiconductor film where the gate electrode is to be formed. a step of selectively etching the oxidation-resistant insulating film; a step of oxidizing the first semiconductor film in the etched portion of the oxidation-resistant insulating film to form the insulator that divides the gate electrode;
Using the first semiconductor film as a diffusion mask, a second semiconductor layer forming the channel region is formed, which has a conductivity type opposite to that of the semiconductor body and has a lower concentration than the first semiconductor layer, and has a conductivity type that is the same as that of the semiconductor body. A method for manufacturing a vertical semiconductor device, comprising the step of forming a third semiconductor layer that is of a conductive type and is shallower than the second semiconductor layer and serves as the source region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60157821A JPS6218769A (en) | 1985-07-17 | 1985-07-17 | Vertical type semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60157821A JPS6218769A (en) | 1985-07-17 | 1985-07-17 | Vertical type semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6218769A true JPS6218769A (en) | 1987-01-27 |
Family
ID=15658040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60157821A Pending JPS6218769A (en) | 1985-07-17 | 1985-07-17 | Vertical type semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6218769A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04299868A (en) * | 1991-03-28 | 1992-10-23 | Sanyo Electric Co Ltd | Power mosfet and its manufacture |
| JPH04324642A (en) * | 1991-04-24 | 1992-11-13 | Sanyo Electric Co Ltd | Manufacture of insulated gate type semiconductor device |
| JPH04324684A (en) * | 1991-04-24 | 1992-11-13 | Sanyo Electric Co Ltd | Insulated gate type bipolar transistor and its manufacture |
| EP0567623A1 (en) * | 1991-11-12 | 1993-11-03 | Harris Corporation | Power fet having reduced threshold voltage |
-
1985
- 1985-07-17 JP JP60157821A patent/JPS6218769A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04299868A (en) * | 1991-03-28 | 1992-10-23 | Sanyo Electric Co Ltd | Power mosfet and its manufacture |
| JPH04324642A (en) * | 1991-04-24 | 1992-11-13 | Sanyo Electric Co Ltd | Manufacture of insulated gate type semiconductor device |
| JPH04324684A (en) * | 1991-04-24 | 1992-11-13 | Sanyo Electric Co Ltd | Insulated gate type bipolar transistor and its manufacture |
| EP0567623A1 (en) * | 1991-11-12 | 1993-11-03 | Harris Corporation | Power fet having reduced threshold voltage |
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