JPS62186524A - Epitaxial wafer - Google Patents

Epitaxial wafer

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Publication number
JPS62186524A
JPS62186524A JP2785286A JP2785286A JPS62186524A JP S62186524 A JPS62186524 A JP S62186524A JP 2785286 A JP2785286 A JP 2785286A JP 2785286 A JP2785286 A JP 2785286A JP S62186524 A JPS62186524 A JP S62186524A
Authority
JP
Japan
Prior art keywords
layer
epitaxial
substrate
added
epitaxial wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2785286A
Other languages
Japanese (ja)
Other versions
JPH0834172B2 (en
Inventor
Hitoshi Unno
海野 仁志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61027852A priority Critical patent/JPH0834172B2/en
Publication of JPS62186524A publication Critical patent/JPS62186524A/en
Publication of JPH0834172B2 publication Critical patent/JPH0834172B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To obtain an epitaxial wafer having an epitaxy layer with few defects, by adding a minute amount of gallium in an indium phosphite layer on an indium phosphide substrate. CONSTITUTION:On an indium phosphide substrate, one or more epitaxial layers including at least one indium phosphide layer are grown, and an epitaxial wafer is formed. At this time, a minute amount of gallium is added in the one or more indium phosphide layers. Thus, the epitaxial wafer having the epitaxy layer with few defects is obtained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、燐化インジウム基板上へ燐化インジウムを含
む単層もしくは多層のエピタキシャル成長を行なっ之エ
ピタキシャルウェハに関スル。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an epitaxial wafer in which a single layer or multiple layers containing indium phosphide are epitaxially grown on an indium phosphide substrate.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

ni −v族化会物半導体は、半導体レーザー、フォト
ダイオード、電界効果トランジスタなどの光デバイス、
電子デバイスの材料として使用さnている。化合物半導
体を用いて素子を作製する1a酋一般には燐化インジウ
ム(以下エロPと記す)砒化ガリウム等の単結晶基板上
に化合微生導体薄膜を−F−又は多層エピタキシャル成
長を行なう。エピタキシャル成長を行なう方法としcは
、液相成長法、気相成長法、有機金属熱分解気相成長法
等が知られている。
Ni-V compound semiconductors are used in optical devices such as semiconductor lasers, photodiodes, and field effect transistors;
It is used as a material for electronic devices. In order to fabricate a device using a compound semiconductor, a compound microscopic conductor thin film is generally grown -F- or multilayer epitaxially on a single crystal substrate of indium phosphide (hereinafter referred to as "Ero-P"), gallium arsenide, or the like. Known methods for epitaxial growth include liquid phase growth, vapor phase growth, and organometallic pyrolysis vapor growth.

作製された素子の特性は、エピタキシャル層の品質に太
き(依存し、エピタキシャル層中に転位が存在すると、
特性や歩留り等が悪化する。
The characteristics of the fabricated device greatly depend on the quality of the epitaxial layer, and if there are dislocations in the epitaxial layer,
Characteristics, yield, etc. deteriorate.

エピタキシャル層中の転位は、必らずしも基板の転位と
l対lに対応してはいないが、基板の転位が少なければ
エピタキシャル層中の転位も少ない傾向が一般に認めら
れる。
Although the dislocations in the epitaxial layer do not necessarily have a one-to-one correspondence with the dislocations in the substrate, it is generally recognized that if there are fewer dislocations in the substrate, there will be fewer dislocations in the epitaxial layer.

このためエピタキシャル層の転位を減らし、素子性能、
歩留まりを向上する几めに転位の少ない基板を使用する
事が通常行なわれている。
This reduces dislocations in the epitaxial layer and improves device performance.
In order to improve yield, it is common practice to use a substrate with fewer dislocations.

転位の少ない基板はInPの場合、硫黄や犠鉛を高濃度
にドーピングしたものでしか得られていない。しかし高
濃度にドープされた基板上にエピタキシャル成長を行な
った場合、基板からの不純物拡散や、オートドーピング
などの好ましくない現象が起こる事がある。一方、′I
It界効果トランジスタなどの作製に用いる半絶縁性基
板では、転位密度の指標であるエッチビット密度が数万
/cIIl!であり、素子特性、歩留まり等の向上を計
る上で。
In the case of InP, substrates with few dislocations can only be obtained by doping them with high concentrations of sulfur or sacrificial lead. However, when epitaxial growth is performed on a highly doped substrate, undesirable phenomena such as impurity diffusion from the substrate and autodoping may occur. On the other hand, 'I
In semi-insulating substrates used for manufacturing It field effect transistors, etc., the etch bit density, which is an index of dislocation density, is in the tens of thousands/cIIl! In order to improve device characteristics, yield, etc.

エピタキシャル層において、転位を減少する事が望まれ
る。
It is desirable to reduce dislocations in epitaxial layers.

〔発明の目的〕[Purpose of the invention]

本発明は以上の事に鑑みてなされたもので、欠陥の多い
基板上にエピタキシャル成長を行なった場合においても
、欠陥の少ないエピタキシャル成長層を有するエピタキ
シャルウェハを提供する事を目的とする。
The present invention has been made in view of the above, and an object of the present invention is to provide an epitaxial wafer having an epitaxially grown layer with few defects even when epitaxial growth is performed on a substrate with many defects.

〔発明の概要〕[Summary of the invention]

本発明は、InPをエピタキシャル成長する際に微量の
ガリウム(以下Ga)が添加された。転位密度の小さい
I’nP  エピタキシャル層を一層以上含むエピタキ
シャルウェハに関するものである。
In the present invention, a trace amount of gallium (hereinafter referred to as Ga) is added when epitaxially growing InP. The present invention relates to an epitaxial wafer including one or more I'nP epitaxial layers having a low dislocation density.

本発明に於いて、添加するGaの訛を増してゆくと、I
nPエピタキシャル層とI nP!!i板の格子定数が
ずれてきて、歪が大きくなり、ついには不整合転位が発
生゛fる掛が予想される。実験では。
In the present invention, as the concentration of Ga added is increased, I
nP epitaxial layer and I nP! ! It is expected that the lattice constant of the i-plate will shift, the strain will increase, and eventually mismatched dislocations will occur. In the experiment.

同相中のIII族のうちGaの彼が3%を越えるとGa
をノ用えない場合と同程度のエッチピット密1ffiと
なった事がらGaの添加量としては固相中の■族のうち
、3チを越えない範囲とTべきである。又、Gaを加え
る量が0.08チより少ない時、エッチピット密度の平
均が基板と同程度となった時から。
If Ga exceeds 3% of Group III members in the same phase, Ga
Since the etch pit density was 1ffi, which is the same as that in the case where no etchant is used, the amount of Ga to be added should be within a range not exceeding 3 of the group (3) in the solid phase. Furthermore, when the amount of Ga added was less than 0.08 inch, the average etch pit density became comparable to that of the substrate.

確実な効果を得るためには、添加するOaの量を固相中
の■族のうち、0.08%  より多くする争が望まし
い。
In order to obtain reliable effects, it is desirable to increase the amount of Oa added to more than 0.08% of the group (2) in the solid phase.

〔発明の効果〕〔Effect of the invention〕

本発明を適用したInPエピタキシャル1@ト。 InP epitaxial structure 1 to which the present invention is applied.

従来法のInPエピタキシャル層について、結晶の転位
と対応するエッチビットの密度を比較したところ、基板
のエッチピット密度が約40000 jVcm”の時本
発明を適用したInPエピタキシャル層のエッチピット
密度は従来法によるエロPエピタキシャル層のエッチピ
ット密度の1/2〜1/4であった。
A comparison of the density of etch bits corresponding to crystal dislocations for the conventional InP epitaxial layer revealed that when the etch pit density of the substrate was approximately 40,000 jVcm, the etch pit density of the InP epitaxial layer to which the present invention was applied was higher than that of the conventional method. The etch pit density was 1/2 to 1/4 of the etch pit density of the ERO-P epitaxial layer.

又、本発明を適用したInPエピタキシャル層の上に従
来法の■ロPエピタキシャル噛、GaInAsP層など
をエピタキシャル成長して、最上層のエッチピット密度
を、従来法のみで同じ構造とし友ものと比較し比ところ
、やはり、本発明によるInP層を含むウェハはl/2
以下のエッチピット密度だ−)友。
In addition, we epitaxially grew a GaInAsP layer using the conventional method on the InP epitaxial layer to which the present invention was applied, and compared the etch pit density of the top layer with a similar structure using only the conventional method. In contrast, the wafer containing the InP layer according to the invention is l/2
The etch pit density is below -) Friend.

〔発明の実施例〕[Embodiments of the invention]

本発明の効果を直接観察するために燐酸2:臭化水素酸
1の割合で混合したエツチング液により、Ga添加量の
異なる試料をエツチングしてエッチピット密度の比較を
行qりだ。エッチビットは一般に転位に対応して現れる
ので、その密度は転位の量的指標となる。第1図は、エ
ッチピット密度が約400007cm”のInP鉄ドー
プ半絶縁性基板上に添加するGaの量を変えてInP単
層を数ミクロンエピタキシャル成長し、エッチピット密
度を比較したものである。ご(少量のGaの添加により
、エッチピット密度は太き(減少し、Gaの添加量が2
91+程度まで、あまり変化はなかりた。
In order to directly observe the effects of the present invention, samples with different amounts of Ga added were etched using an etching solution mixed in a ratio of 2 parts phosphoric acid to 1 part hydrobromic acid, and the etch pit densities were compared. Since etch bits generally appear in correspondence with dislocations, their density serves as a quantitative indicator of dislocations. Figure 1 shows a comparison of the etch pit densities obtained by epitaxially growing an InP single layer of several microns by varying the amount of Ga added on an InP iron-doped semi-insulating substrate with an etch pit density of approximately 400,007 cm. (By adding a small amount of Ga, the etch pit density becomes thicker (reduced), and the amount of Ga added is 2
There was not much change until it reached 91+.

しかし3チ付近でエッチピット密度は急増しGRを添加
しない場合と同程度となりた。
However, the etch pit density rapidly increased around 3 inches and became comparable to the case where no GR was added.

第2図、第3図は、それぞれGaの添加量が0チと0.
7%、嗅厚が3.5μmと4μmの試料に室温で40秒
のエツチング処理を行rx ”:)几写真である。
Figures 2 and 3 show that the amount of Ga added is 0 and 0, respectively.
7%, and samples with olfactory thicknesses of 3.5 μm and 4 μm were etched at room temperature for 40 seconds.

第4図、第5Mは、それぞれ第2図、第3図の試料の成
長層を、エツチング除去し基板のエッチピット密度を比
較したものであるが、第2図と第3図で認められ几エッ
チピvト密度の差は、第4図と第5図では見られなかっ
た。
Figures 4 and 5M compare the etch pit densities of the substrates after removing the grown layers of the samples in Figures 2 and 3 by etching, respectively. No difference in etch pit density was seen between FIGS. 4 and 5.

第6図は、エッチピット密度が約300007cm”の
エロP都ドープn型基板上に、本発明によるGa添加I
nPiiを数ミクロン成長し、更に、通常のInP層を
数ミクロン成長した時の下層のInP中のGa添加1゛
に対し、上層のInP層のエッチピット密度をプロット
したものである。多層ウェハにおいても下層へGa添加
102層を入れる事により上層のエッチビットも減少す
る事がわかる。
FIG. 6 shows a Ga-added I layer according to the present invention on an etch pit doped n-type substrate with an etch pit density of approximately 300,007 cm.
This is a plot of the etch pit density of the upper InP layer with respect to Ga addition of 1'' in the lower InP layer when nPii is grown to several microns and then a normal InP layer is grown to several microns. It can be seen that even in a multilayer wafer, by adding the Ga-added 102 layer to the lower layer, the etch bits in the upper layer are also reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明実施列のGaの添加量と、エッチビッ
ト密度の関係を示す図、第2図はGaがIA 7111
1さルていない■ロPエピタキシャルrHの結晶構造(
エッチビット)を顕微鏡写真により表わした図、@3図
はGaが0.7俤添別されたエロPエピタキシャル1−
の結晶構造(エッチビット)を顕微鏡写真により表わし
t図、第4図は第2図のエピタキシャル層をにがした基
板の結晶構造(エッチビット)を顕微鏡写真で表わした
図、第5図μ第3図のエピタキシャル層をはがした基板
の結晶構造(エッチビット)を顕微鏡写真で表わした図
、第6図は、ド1+1に本発明によるGaを含むInP
を成長し、上層に通常のInPを成長し九時の下層に添
加されたGaの量と、上層のエッチビット密度の関係を
示す図である。 代理人 弁理士  則 近 憲 借 間     竹 花 喜久男 0.1           1.0 第1図 第2図 第3図 第4図 第5図
FIG. 1 is a diagram showing the relationship between the amount of Ga added and the etch bit density in the embodiments of the present invention, and FIG.
1. Crystal structure of ROP epitaxial rH (
Figure @3 is a microscopic photograph of the etch bit).
Figure 4 is a micrograph showing the crystal structure (etch bit) of the substrate from which the epitaxial layer of Figure 2 has been removed, and Figure 5 is a micrograph showing the crystal structure (etch bit) of the substrate. Figure 3 is a micrograph showing the crystal structure (etch bit) of the substrate from which the epitaxial layer has been peeled off, and Figure 6 is a micrograph showing the crystal structure (etched bits) of the substrate from which the epitaxial layer has been peeled off.
FIG. 3 is a diagram showing the relationship between the amount of Ga added to the lower layer at 9 o'clock and the etch bit density of the upper layer after growing normal InP on the upper layer. Agent Patent attorney Nori Chika Ken Kikuo Takehana 0.1 1.0 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (2)

【特許請求の範囲】[Claims] (1)燐化インジウム基板の上に少なくとも一層の燐化
インジウム層を含む一層以上のエピタキシャル層を成長
したエピタキシャルウェハにおいて、一層又はそれ以上
の燐化インジウム層に微量のガリウムが添加されている
事を特徴とするエピタキシャルウェハ。
(1) In an epitaxial wafer in which one or more epitaxial layers containing at least one indium phosphide layer are grown on an indium phosphide substrate, a trace amount of gallium is added to one or more indium phosphide layers. An epitaxial wafer featuring:
(2)添加されるガリウムの量が固相比でインジウムに
対し0.08%乃至3%であることを特徴とする特許請
求の範囲第1項記載のエピタキシャルウェハ。
(2) The epitaxial wafer according to claim 1, wherein the amount of gallium added is 0.08% to 3% relative to indium in solid phase ratio.
JP61027852A 1986-02-13 1986-02-13 Epitaxial wafer Expired - Fee Related JPH0834172B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61027852A JPH0834172B2 (en) 1986-02-13 1986-02-13 Epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61027852A JPH0834172B2 (en) 1986-02-13 1986-02-13 Epitaxial wafer

Publications (2)

Publication Number Publication Date
JPS62186524A true JPS62186524A (en) 1987-08-14
JPH0834172B2 JPH0834172B2 (en) 1996-03-29

Family

ID=12232447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61027852A Expired - Fee Related JPH0834172B2 (en) 1986-02-13 1986-02-13 Epitaxial wafer

Country Status (1)

Country Link
JP (1) JPH0834172B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015137373A1 (en) * 2014-03-11 2015-09-17 古河電気工業株式会社 Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60105218A (en) * 1983-11-11 1985-06-10 Nippon Telegr & Teleph Corp <Ntt> 3-5 group compound single crystal semiconductor substrate
JPS6265408A (en) * 1985-09-18 1987-03-24 Sumitomo Electric Ind Ltd Manufacture of epitaxial wafer of compound semiconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60105218A (en) * 1983-11-11 1985-06-10 Nippon Telegr & Teleph Corp <Ntt> 3-5 group compound single crystal semiconductor substrate
JPS6265408A (en) * 1985-09-18 1987-03-24 Sumitomo Electric Ind Ltd Manufacture of epitaxial wafer of compound semiconductor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015137373A1 (en) * 2014-03-11 2015-09-17 古河電気工業株式会社 Semiconductor device
CN106030939A (en) * 2014-03-11 2016-10-12 古河电气工业株式会社 Semiconductor laser element
US9960572B2 (en) 2014-03-11 2018-05-01 Furukawa Electric Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
JPH0834172B2 (en) 1996-03-29

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