JPS62186442U - - Google Patents
Info
- Publication number
- JPS62186442U JPS62186442U JP7557686U JP7557686U JPS62186442U JP S62186442 U JPS62186442 U JP S62186442U JP 7557686 U JP7557686 U JP 7557686U JP 7557686 U JP7557686 U JP 7557686U JP S62186442 U JPS62186442 U JP S62186442U
- Authority
- JP
- Japan
- Prior art keywords
- flat package
- circuit element
- terminals
- utility
- model registration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005452 bending Methods 0.000 claims 1
- 230000037431 insertion Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
Landscapes
- Jigs For Machine Tools (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例を各端子を折り曲
げない状態で示す斜視図、第２図はプリント基板
に対する装着状態を示す一部省略側面図である。
図面中、１はフラツトパツケージ形回路素子、
５はリード端子、６は位置決め用端子、７はプリ
ント基板、８は孔である。
FIG. 1 is a perspective view showing an embodiment of this invention with the terminals not bent, and FIG. 2 is a partially omitted side view showing the state in which the terminals are attached to a printed circuit board. In the drawing, 1 is a flat package type circuit element,
5 is a lead terminal, 6 is a positioning terminal, 7 is a printed circuit board, and 8 is a hole.
Claims (1)
れらリード端がプリント基板の所定位置にハンダ
付けされるフラツトパツケージ形回路素子におい
て、少なくとも前記フラツトパツケージの相対す
る２つの前記側面には前記リード端子と同形状の
任意の本数の位置決め用端子を有し、これら位置
決め用端子は前記プリント基板に設けられた挿入
孔に挿入されることを特徴とするフラツトパツケ
ージ形回路素子。 (2) 実用新案登録請求の範囲第１項において、
前記各側面の前記位置決め用端子の数は非対称に
なつていることを特徴とするフラツトパツケージ
形回路素子。 (3) 実用新案登録請求の範囲第１項において、
前記リード線と前記位置決め用端子はその折り曲
げ形状が異なつていることを特徴とするフラツト
パツケージ形回路素子。[Claims for Utility Model Registration] (1) In a flat package circuit element having a plurality of lead terminals on its side surface, the ends of which are soldered to predetermined positions on a printed circuit board, at least the flat package has an arbitrary number of positioning terminals having the same shape as the lead terminals on the two opposing sides, and these positioning terminals are inserted into insertion holes provided in the printed circuit board. Flat package type circuit element. (2) In paragraph 1 of the claims for utility model registration,
A flat package type circuit element characterized in that the number of the positioning terminals on each side surface is asymmetrical. (3) In paragraph 1 of the claims for utility model registration,
A flat package type circuit element, wherein the lead wire and the positioning terminal have different bending shapes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7557686U JPS62186442U (en) | 1986-05-20 | 1986-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7557686U JPS62186442U (en) | 1986-05-20 | 1986-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62186442U true JPS62186442U (en) | 1987-11-27 |
Family
ID=30921847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7557686U Pending JPS62186442U (en) | 1986-05-20 | 1986-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62186442U (en) |
-
1986
- 1986-05-20 JP JP7557686U patent/JPS62186442U/ja active Pending
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