JPS62183552A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the titled semiconductor device from turning into a state of operation as a thyristor as well as to prevent the semiconductor device from destruction due to latch-up by a method wherein an impurity layer, having the impurity type same as a silicon substrate, is formed on the rear surface of the silicon substrate. CONSTITUTION:The difference between the titled semiconductor device and the device heretofore in use is that the former is formed with P-type impurity layer 10. After the prescribed semiconductor element has been formed on a wafer, the wafer is shaved and polished to the prescribed thickness, and boric ions are implanted on the rear side of the wafer. Then, boric ions are activated by performing a low-temperature annealing by the irradiation of microwaves, for example, and a P-type impurity layer 10 is formed. As a result, the P-type impurity layer 10 can be formed without damaging the semiconductor element already formed. Consequently, the P-type silicon substrate is prevented from turning into an N-type one, and the semiconductor device can also be prevented from breakdown due to the latch-up of a parasitic thyristor.

Description

[Detailed Description of the Invention] [Summary] A semiconductor device in which a semiconductor element is formed on a silicon substrate of one conductivity type with a relatively low impurity concentration, in which a high concentration impurity layer of one conductivity type is formed on the back side of the silicon substrate. This prevents the vicinity of the back surface of the silicon substrate that contacts the die attach from being reversed from one conductivity type to the opposite conductivity type, thereby preventing latch-up due to parasitic thyristors.

[Industrial application field]

The present invention relates to a semiconductor device, and more specifically, to the structure of a semiconductor device in which a bipolar transistor such as an ECL circuit is formed.

[Conventional technology]

FIG. 2 is a circuit diagram of a basic ECL circuit, where R1 and R2 are pull-up resistors for transistors Ql and Q2, respectively, and R3 is an emitter resistor common to each transistor. Generally, the high voltage power supply VCC is at ground level (GND),
Low voltage power supply WEE is set to -5.2V.

Next, the operation of this circuit will be explained. Input voltage VIN
When is higher than the reference voltage VR, Ql is turned on and Q2 is turned off, so that Sl is at a low level and S2 is at a high level. On the other hand, when the input voltage WIN is lower than the reference voltage VR, Ql is turned off and Q2 is turned on, so that Sl is at a high level and S2 is at a low level.

By the way, in order for the ECL circuit to operate as fast as possible,
R1, R to prevent saturation when Ql, Q2 are in the ON state.
2 and R3 are set to optimal values. Also Ql, Q2
Efforts have been made to minimize the capacitance parasitically added to the collector.

FIG. 3 is a sectional view of a conventional semiconductor device forming a transistor Ql to explain this. 1 is a P-type silicon substrate and is at the WEE level.

2 is an N-type epitaxial layer formed thereon;
Configure the collector of Ql. 3 is P for isolation
This is a type impurity region. 4 is a P-type impurity region formed in the N-type epitaxial layer 2, and constitutes the base of Ql. Reference numeral 5 denotes a heavily doped N-type impurity region, which constitutes the emitter of Ql. Further, 6 is an N-type impurity region for contact, which is formed by the same process as 5.

That is, the parasitic capacitance added to the collector of Ql is mainly the junction capacitance CF between the P-type silicon substrate l and the N-type epitaxial layer 2 shown in FIG. 3, and this capacitance must be reduced for high-speed operation of the ECL circuit. That is required.

For this purpose, a P-type silicon substrate of, for example, 20 Ω·cm is conventionally used, and an N-type epitaxial layer of 0.50·cm is formed.

[Problem that the invention seeks to solve]

By the way, in the case of a P-type silicon substrate of 20 Ω·cm, when it is made into a chip and fixed to a die attach, the back surface of the P-type silicon substrate that comes into contact with the die attach may be reversed to an N type, as shown in FIG.

Note that FIG. 4 is a cross-sectional view of the input circuit section of the ECL circuit, where 7 is an input resistor, 8 is a die attach, and 9 is an N-type inversion layer.

In such a case, when a high level voltage is input to the input terminal (IN), a thyristor (7(P・) −
2(N) -1(P) -9(N) ) may latch up, causing a large current to flow and destroying the semiconductor device. Of course, P with a high impurity concentration, for example, 0.5Ω・cm
If a type silicon substrate is used, N-type inversion can be prevented and damage to the semiconductor device can be prevented, but as mentioned above, this increases the collector capacitance of the transistor, making it impossible to achieve faster operation. .

The present invention was created in view of the problems of the prior art, and aims to provide a semiconductor device that is capable of both high-speed operation and prevention of latch-up.

[Means for solving problems]

The present invention provides a semiconductor device in which a semiconductor element is formed on a silicon substrate of one conductivity type with a relatively low impurity concentration, by forming a high concentration impurity layer of one conductivity type on the back side of the silicon substrate. It is characterized by preventing the vicinity of the back surface from being reversed from one conductivity type to an opposite conductivity type.

[Effect]

Since a highly concentrated impurity layer of one conductivity type is formed on the back surface of the silicon substrate, the vicinity of the back surface of the silicon substrate will not be reversed to the opposite conductivity type even when it is made into a chip and fixed to die attach.

Therefore, it is possible to prevent a parasitic thyristor from being formed between the inversion layer and other impurity layers, and it is therefore possible to prevent damage to the semiconductor device due to latch-up of the thyristor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. This figure differs from the conventional semiconductor device shown in FIG. 4 in that a P-type impurity layer IO is formed.

Next, a method for forming this P-type impurity layer IO will be explained. After predetermined semiconductor elements are formed on the wafer,
The wafer is ground and polished to a predetermined thickness. Next, poron ions (Bo) are implanted into the back of the wafer.
For example, poron ions are activated by low temperature annealing using microwave irradiation to form a P-type impurity layer IO. Thereby, the P-type impurity layer IO can be formed on the back surface of the wafer without damaging the semiconductor elements that have already been formed.

Thus, according to embodiments of the invention, e.g.
As a P-type silicon substrate used in L circuits, 2
By using a silicon substrate with a low concentration of 0Ω・cm, it is possible to reduce parasitic capacitance and speed up operation, and the P-type impurity layer IO prevents the P-type silicon substrate from becoming N-type, thereby reducing the parasitic thyristor. Destruction of the semiconductor device due to latch-up can be prevented.

In the embodiment, a semiconductor device in which an ECL circuit is formed has been described, but it is obvious that the present invention can be applied to a semiconductor device in which other bipolar type circuits are formed.

It is also applicable to a semiconductor device in which an MO3 type circuit is formed if there is a risk of it becoming a thyristor.

〔Effect of the invention〕

As explained above, according to one aspect of the present invention, by forming an impurity layer of the same impurity type as the silicon substrate on the back surface of a silicon substrate, it is possible to prevent a semiconductor device from becoming a thyristor, and to prevent the semiconductor device from becoming a thyristor due to latch-up of the thyristor. can prevent the destruction of

At the same time, since the concentration of the silicon substrate can be selected to be the optimum value for the semiconductor element formed thereon, it is possible to form a semiconductor element with a predetermined high performance.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a basic ECL circuit, and FIG. 3 is a sectional view of a conventional semiconductor device. FIG. 4 is a cross-sectional view illustrating problems of a conventional semiconductor device. (Explanation of symbols) 1...P-type silicon substrate, 2...N-type epitaxial layer, 3.4.7...P-type impurity region, 5.6...N-type impurity region, 8...・Die attach, 9...N-type inversion layer, lO...P-type impurity layer. Main house m1lli Messenger 1 Figure 1 ECL basic circuit Figure 2 d Length 1

Claims (1)

[Claims] In a semiconductor device in which a semiconductor element is formed on a silicon substrate of one conductivity type with a relatively low impurity concentration, by forming a high concentration impurity layer of one conductivity type on the back side of the silicon substrate, the area near the back side of the silicon substrate is improved. A semiconductor device characterized by preventing inversion from a conductivity type to an opposite conductivity type.