CN110571212A - Electrostatic protection structure, forming method and working method thereof, and electrostatic protection circuit - Google Patents

Electrostatic protection structure, forming method and working method thereof, and electrostatic protection circuit Download PDF

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Publication number
CN110571212A
CN110571212A CN201810575868.2A CN201810575868A CN110571212A CN 110571212 A CN110571212 A CN 110571212A CN 201810575868 A CN201810575868 A CN 201810575868A CN 110571212 A CN110571212 A CN 110571212A
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region
ith
doping
mth
doping region
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谷欣明
陈捷
朱恺
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An electrostatic protection structure, a forming method and a working method thereof, and an electrostatic protection circuit, wherein the electrostatic protection structure comprises: the first collecting doping region is connected with the power supply end; a first emission doping region to an Mth emission doping region; the first base doping region and the Mth base doping region are connected with the ground terminal, the ith base doping region and the ith collector doping region are connected with the kth emitting doping region and the kth base doping region; the first current injection doping region to the Mth current injection doping region are used for being injected with adjusting current when the power supply end generates transient potential difference. The performance of the electrostatic protection structure is improved.

Description

Electrostatic protection structure, forming method and working method thereof, and electrostatic protection circuit
Technical Field
The invention relates to the field of electrostatic protection, in particular to an electrostatic protection structure, a forming method and a working method thereof, and an electrostatic protection circuit.
Background
in the manufacture and application of integrated circuit chips, with the continuous improvement of super-large-scale integrated circuit process technology, the current CMOS integrated circuit manufacturing technology has entered the deep submicron stage, the size of MOS devices has been continuously reduced, the thickness of gate oxide layer is thinner and thinner, the voltage withstanding capability of MOS devices is significantly reduced, and the damage of Electrostatic Discharge (ESD) to integrated circuits has become more and more significant. Therefore, ESD protection of integrated circuits becomes particularly important.
In order to enhance the protection capability against static electricity, an electrostatic protection circuit is usually connected to an input/output interface (I/O pad) of the chip, and the electrostatic protection circuit provides a discharge path for electrostatic current for internal circuits in the chip to prevent the static electricity from breaking down the internal circuits of the chip.
however, the performance of the conventional electrostatic protection structure is poor.
Disclosure of Invention
The invention provides an electrostatic protection structure, a forming method and a working method thereof, and an electrostatic protection circuit, so as to improve the performance of the electrostatic protection structure.
To solve the above problems, the present invention provides an electrostatic protection structure, including: the semiconductor device comprises a semiconductor substrate, a first isolation layer and a second isolation layer, wherein the semiconductor substrate is internally provided with a plurality of first well regions to Mth well regions which are separated from each other, and the conduction types of the first well regions to the Mth well regions are P-type; the first collecting doping area to the Mth collecting doping area, the conductivity types of the first collecting doping area to the Mth collecting doping area are all N-type, the ith collecting doping area is located in the ith well area, the first collecting doping area is connected with a power supply end, and i is more than or equal to 1 and less than or equal to M; the first emitting doping region to the Mth emitting doping region are all N-type in conductivity type, the ith emitting doping region is located in the ith well region, the Mth emitting doping region is connected with a grounding end, and the ith emitting doping region is located on the side portion of the ith collector doping region; the conductive types of the first base doped region to the Mth base doped region are P type, the ith base doped region is positioned in the ith well region, the ith base doped region and the ith collector doped region are respectively positioned at two sides of the ith emission doped region, the Mth base doped region is connected with a grounding terminal, the kth emission doped region and the kth base doped region are connected with the kth +1 collector doped region, and k is more than or equal to 1 and less than or equal to M-1; the first current injection doping region to the Mth current injection doping region are all of P type in conductivity type, the ith current injection doping region is located in the ith well region, the ith current injection doping region and the ith emission doping region are respectively located on two sides of the ith collection doping region, and the first current injection doping region to the Mth current injection doping region are used for being injected with adjusting current when a power supply end generates an instantaneous potential difference.
optionally, the first current injection doping region to the mth current injection doping region are connected to an external current adjusting circuit, and when the power source terminal generates an instantaneous potential difference, the external current adjusting circuit injects an adjusting current into the first current injection doping region to the mth current injection doping region.
Optionally, the higher the instantaneous potential difference generated by the power supply terminal, the larger the regulating current.
Optionally, the method further includes: the isolation well region is positioned between the kth well region and the (k + 1) th well region, and the conductivity type of the isolation well region is N type; and the isolation doping layer is positioned in the isolation well region, the conductivity type of the isolation doping layer is N-type, and the isolation doping layer is connected with a power supply end.
the invention also provides a forming method of the electrostatic protection structure, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is internally provided with a plurality of first well regions to Mth well regions which are separated from each other, and the conductivity types of the first well regions to the Mth well regions are P type; forming a first collecting doping area to an Mth collecting doping area, wherein the conductivity types of the first collecting doping area to the Mth collecting doping area are all N-type, the ith collecting doping area is positioned in the ith well area, the first collecting doping area is connected with a power supply end, and i is more than or equal to 1 and less than or equal to M; forming a first emission doping region to an Mth emission doping region, wherein the conductivity types of the first emission doping region to the Mth emission doping region are all N-type, the ith emission doping region is positioned in an ith well region, the Mth emission doping region is connected with a grounding end, and the ith emission doping region is positioned on the side part of an ith collector doping region; forming a first base doping region to an Mth base doping region, wherein the conductivity types of the first base doping region to the Mth base doping region are all P type, the ith base doping region is positioned in an ith well region, the ith base doping region and the ith collector doping region are respectively positioned at two sides of an ith emission doping region, the Mth base doping region is connected with a grounding end, the kth emission doping region and the kth base doping region are connected with a kth +1 collector doping region, and k is more than or equal to 1 and less than or equal to M-1; and forming a first current injection doping region to an Mth current injection doping region, wherein the conductivity types of the first current injection doping region to the Mth current injection doping region are all P-type, the ith current injection doping region is positioned in the ith well region, the ith current injection doping region and the ith emission doping region are respectively positioned at two sides of the ith current collection doping region, and the first current injection doping region to the Mth current injection doping region are used for being injected with adjusting current when an instantaneous potential difference is generated at a power supply end.
Optionally, an isolation well region located between the kth well region and the (k + 1) th well region is further disposed in the semiconductor substrate, and a conductivity type of the isolation well region is an N type; the method for forming the semiconductor device further comprises the following steps: and forming an isolation doping layer in the isolation well region, wherein the conductivity type of the isolation doping layer is N type, and the isolation doping layer is connected with a power supply end.
optionally, the first current injection doping region to the mth current injection doping region are connected to an external current adjusting circuit, and when the power source terminal generates an instantaneous potential difference, the external current adjusting circuit injects an adjusting current into the first current injection doping region to the mth current injection doping region.
Optionally, the higher the instantaneous potential difference generated by the power supply terminal, the larger the regulating current.
The present invention also provides an electrostatic protection circuit, including: the first NPN type triode to the Mth NPN type triode, the ith NPN type triode is provided with an ith collector region, an ith emitter region and an ith base region, i is more than or equal to 1 and less than or equal to M, the first collector region is connected with a power supply end, the Mth emitter region is connected with a grounding end, the Mth base region is connected with the grounding end, the kth emitter region and the kth base region are connected with a kth +1 collector region, and k is more than or equal to 1 and less than or equal to M-1; the first parasitic resistor to the Mth parasitic resistor, the ith parasitic resistor is positioned between the ith emitter region and the ith base region, one end of the ith parasitic resistor, which is connected with the ith emitter region, is an ith injection end, and the first injection end to the ith injection end are used for being injected with adjustment current when the power supply end generates instantaneous potential difference.
optionally, the first injection end to the ith injection end are connected to an external current adjusting circuit, and when the power supply end generates an instantaneous potential difference, the external current adjusting circuit injects an adjusting current into the first parasitic resistor to the mth parasitic resistor.
Optionally, the higher the instantaneous potential difference generated by the power supply terminal, the larger the regulating current.
The invention also provides a working method of the electrostatic protection structure, which comprises the following steps: when the external current adjusting circuit detects the instantaneous potential difference of the power supply end, the external current adjusting circuit is triggered by frequency and generates adjusting current, and the external current adjusting circuit injects the adjusting current into the first current injection doping area to the Mth current injection doping area respectively.
Compared with the prior art, the technical scheme of the invention has the following advantages:
In the electrostatic protection structure provided by the technical scheme of the invention, an ith NPN type triode is arranged in an ith well region and comprises an ith collector doping region, an ith emitter doping region and an ith base doping region. The first collecting doped region is connected with a power supply end, the Mth emitting doped region is connected with a grounding end, the Mth base doped region is connected with the grounding end, and the kth emitting doped region and the kth base doped region are connected with the (k + 1) th collecting doped region, so that the first NPN type triode and the Mth NPN type triode are sequentially connected in series. The first NPN type triode to the Mth NPN type triode can divide the voltage and bear the instantaneous potential difference of a power supply end. And selecting a proper number of NPN type triode transistors, namely M takes a proper numerical value, so that under the condition of a certain transient potential difference of a power supply end, the voltage born by a PN junction between the ith collector doping region and the ith well region is smaller than the reverse breakdown voltage of the PN between the ith collector doping region and the ith well region, the PN between the ith collector doping region and the ith well region is ensured not to be reversely conducted, and the leakage between the ith collector doping region and the ith base doping region is avoided. Specifically, when the power supply end generates an instantaneous potential difference, the first current injection doping region is injected into the Mth current injection doping region to adjust current, so that the potential of the ith well region close to the ith emission doping region in the area where the base current path in the ith well region is located is increased, the iNPN transistor is started, and correspondingly, the first NPN transistor is started to the Mth NPN transistor, so that static electricity is released. Therefore, when the electric leakage between the ith collector doping region and the ith base doping region is avoided, the opening of the first NPN type triode to the Mth NPN type triode is prevented from being limited by the instantaneous potential difference generated by the power supply end, and the first NPN type triode to the Mth NPN type triode can be opened in time to release static electricity. In conclusion, the performance of the electrostatic protection structure is improved.
in the method for forming the electrostatic protection structure provided by the technical scheme of the invention, the first current injection doping region to the Mth current injection doping region are formed. Specifically, when the power supply end generates an instantaneous potential difference, the first current injection doping region to the Mth current injection doping region are used for being injected with the adjusting current, so that the potential of the ith well region close to the ith emission doping region in the region where the base current path in the ith well region is located is increased, the iNPN type triode is started, and static electricity is released. Therefore, when the electric leakage between the ith collector doping region and the ith base doping region is avoided, the opening of the first NPN type triode to the Mth NPN type triode is prevented from being limited by the instantaneous potential difference generated by the power supply end, and the first NPN type triode to the Mth NPN type triode can be opened in time to release static electricity.
In the electrostatic protection circuit provided by the technical scheme of the invention, an appropriate number of NPN type triode is selected, namely M is an appropriate value, so that under the condition of an instantaneous potential difference of a certain power supply end, the voltage borne by a PN junction between the ith collector region and the ith well region is smaller than the reverse breakdown voltage of PN between the ith collector region and the ith well region, the PN between the ith collector region and the ith well region is ensured not to be reversely conducted, and the electric leakage between the ith collector region and the ith base region is avoided. One end of the ith parasitic resistor, which is connected with the ith emission region, is an ith injection end, and when the power supply end generates an instantaneous potential difference, the first injection end injects a regulating current to the ith injection end. Therefore, the opening of the ith NPN type triode is controlled by the adjusting current injected by the ith injection end, specifically, when the power supply end generates an instantaneous potential difference, the adjusting current injected by the ith injection end passes through the ith parasitic resistor, so that the potential of the ith emission region close to one side of the ith parasitic resistor is increased, and the ith NPN type triode is opened, so that static electricity is released. Therefore, when the electric leakage between the ith collector region and the ith base region is avoided, the first NPN type triode to the Mth NPN type triode are prevented from being limited by the instantaneous potential difference generated by the power supply end, and the first NPN type triode to the Mth NPN type triode can be started in time to release static electricity. Therefore, the performance of the electrostatic protection circuit is improved.
Drawings
FIG. 1 is a schematic diagram of an electrostatic protection structure;
FIG. 2 is a schematic diagram of another electrostatic protection configuration;
Fig. 3 is a schematic diagram of an electrostatic protection structure according to an embodiment of the invention.
Detailed Description
as mentioned in the background, the performance of existing electrostatic protection structures is poor.
An electrostatic protection structure, please refer to fig. 1 and fig. 2, comprising: the semiconductor substrate 100 is provided with a plurality of mutually-separated first well regions to Mth well regions, the conductivity types of the first well regions to the Mth well regions are N type, the types of the first transistors to the Mth transistors are P type, the ith transistor is provided with an ith grid structure, an ith source region and an ith drain region, the ith grid structure is positioned on the ith well region, the ith source region and the ith drain region are respectively positioned in the ith well regions at two sides of the ith grid structure, i is more than or equal to 1 and less than or equal to 3, the conductivity types of the ith transistor are N type, the first base doping region to the Mth base doping region are positioned in the ith well region, the ith base doping region and the ith drain region are respectively positioned at two sides of the ith source region, the first grid structure and the first base doping region are all connected with a power supply end, the kth drain region is connected with the (k + 1) base doping region, The (k + 1) th source region is connected with the (k + 1) th grid structure, k is more than or equal to 1 and less than or equal to M-1, and the Mth drain region is connected with the grounding end.
In the electrostatic protection structure, the ith well region is provided with an ith parasitic PNP tube, the ith base doping region is used as a base region of the ith parasitic PNP tube, the ith source region is used as an emitter region of the ith parasitic PNP tube, and the ith drain region is used as a collector region of the ith parasitic PNP tube.
For the electrostatic protection structure when M is 3, as shown in fig. 1, the electrostatic protection structure has three parasitic transistors, which are a first parasitic PNP transistor, a second parasitic PNP transistor, and a third parasitic PNP transistor, respectively, and when the voltage at the power supply terminal is 30 volts, the PN between the ith drain region and the ith well region needs to bear a voltage of about 10 volts. If the reverse breakdown voltage of the PN between the ith drain region and the ith well region is 9V, the PN between the ith drain region and the ith well region is conducted reversely, and electric leakage occurs between the ith source region and the ith drain region.
In order to avoid the problem of PN reverse conduction between the ith drain region and the ith well region when the voltage of the power supply terminal is 30 v, one method is: the number of transistors is increased, and the number of parasitic PNP transistors is correspondingly increased, as shown in fig. 2, so that M is 4, and thus the voltage to be borne by the PN between the ith drain region and the ith well region is about 7.5 v, which is less than the reverse breakdown voltage of the PN between the ith drain region and the ith well region.
However, since the number of the parasitic PNP transistors is increased, it is necessary that the voltage of the power supply region is about 44 v, which is greater than 30 v, when each parasitic PNP transistor is turned on, and when the voltage of the power supply terminal is 30 v, the first parasitic PNP transistor to the fourth parasitic PNP transistor cannot be turned on, and static electricity is difficult to discharge.
On this basis, the present invention provides an electrostatic protection structure, comprising: the first collecting doping area is connected with the power end; the first emission doping area to the Mth emission doping area, and the ith emission doping area is positioned in the ith well region; the first base doping region and the Mth base doping region are connected with the ground terminal, the ith base doping region and the ith collector doping region are connected with the kth emitting doping region and the kth base doping region; the first current injection doping region to the Mth current injection doping region, the ith current injection doping region is located in the ith well region, and the first current injection doping region to the Mth current injection doping region are used for being injected with adjusting current when the power supply end generates transient potential difference. The performance of the electrostatic protection structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
an embodiment of the present invention provides an electrostatic protection structure, please refer to fig. 3, which includes:
The semiconductor device comprises a semiconductor substrate 200, wherein a plurality of first well regions 201 to Mth well regions which are mutually separated are arranged in the semiconductor substrate 200, and the conduction types of the first well regions 201 to the Mth well regions are P type;
The first collector doping region to the Mth collector doping region are all N-type in conductivity type, the ith collector doping region is located in the ith well region, the first collector doping region is connected with a power supply end VDD, and i is greater than or equal to 1 and less than or equal to M;
The first emitting doping region to the Mth emitting doping region are all N-type in conductivity type, the ith emitting doping region is located in the ith well region, the Mth emitting doping region is connected with a grounding end, and the ith emitting doping region is located on the side portion of the ith collector doping region;
The conductive types of the first base doped region to the Mth base doped region are P type, the ith base doped region is positioned in the ith well region, the ith base doped region and the ith collector doped region are respectively positioned at two sides of the ith emission doped region, the Mth base doped region is connected with a grounding terminal, the kth emission doped region and the kth base doped region are connected with the kth +1 collector doped region, and k is more than or equal to 1 and less than or equal to M-1;
the first current injection doping region to the Mth current injection doping region are all of P type in conductivity type, the ith current injection doping region is located in the ith well region, the ith current injection doping region and the ith emission doping region are respectively located on two sides of the ith collection doping region, and the first current injection doping region to the Mth current injection doping region are used for being injected with adjusting current when a power supply end generates an instantaneous potential difference.
Specifically, the semiconductor substrate 200 is a P-type doped substrate, and the material of the semiconductor substrate 200 may be single crystal silicon, single crystal germanium, silicon germanium, or silicon carbide, or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); alternatively, the semiconductor substrate 200 may be other materials, such as a III-V compound such as gallium arsenide.
In this embodiment, taking M equal to 4 as an example for explanation, correspondingly, the semiconductor substrate 200 has four mutually-separated first well regions 201, second well regions 202, third well regions 203 and fourth well regions 204. The conductivity types of the first well region 201, the second well region 202, the third well region 203 and the fourth well region 204 are all P-type.
In this embodiment, taking M equal to 4 as an example for explanation, correspondingly, the electrostatic protection structure includes a first collecting doping region 211, a second collecting doping region 212, a third collecting doping region 213, and a fourth collecting doping region 214, the conductivity types of the first collecting doping region 211, the second collecting doping region 212, the third collecting doping region 213, and the fourth collecting doping region 214 are all N-type, the first collecting doping region 211 is located in the first well 201, the second collecting doping region 212 is located in the second well 202, the third collecting doping region 213 is located in the third well 203, and the fourth collecting doping region 214 is located in the fourth well 204.
In this embodiment, taking M equal to 4 as an example for illustration, correspondingly, the electrostatic protection structure includes a first emitting doping region 221, a second emitting doping region 222, a third emitting doping region 223 and a fourth emitting doping region 224, the first emitting doping region 221 is located in the first well 201, the second emitting doping region 222 is located in the second well 202, the third emitting doping region 223 is located in the third well 203, the fourth emitting doping region 224 is located in the fourth well 204, the conductivity types of the first emitting doping region 221, the second emitting doping region 222, the third emitting doping region 223 and the fourth emitting doping region 224 are all N-type, the fourth emitting doping region 224 is connected to the ground terminal VSS, the first emitting doping region 221 is located at a side of the first collector region 211, the second emitting doping region 222 is located at a side of the second collector doping region 212, the third emitting doping region 223 is located at a side of the third collector doping region 213, the fourth emitter doping region 224 is located at the side of the fourth collector doping region 214.
In this embodiment, taking M equal to 4 as an example for explanation, correspondingly, the electrostatic protection structure includes a first base doping region 231, a second base doping region 232, a third base doping region 233 and a fourth base doping region 234, the conductivity types of the first base doping region 231, the second base doping region 232, the third base doping region 233 and the fourth base doping region 234 are all P-type, the first base doping region 231 is located in the first well 201, the second base doping region 232 is located in the second well 202, the third base doping region 233 is located in the third well 203, the fourth base doping region 234 is located in the fourth well 204, the first base doping region 231 and the first collector doping region 211 are respectively located at two sides of the first emitter doping region 221, the second base doping region 232 and the second collector doping region 212 are respectively located at two sides of the second emitter doping region 222, the third base doping region 233 and the third collector doping region 213 are respectively located at two sides of the third emitter doping region 223, the fourth base doping region 234 and the fourth collector doping region 214 are respectively located at two sides of the fourth emitter doping region 224, and the fourth base doping region 234 is connected to the ground terminal VSS.
the kth emitting doping region and the kth base doping region are connected to the kth +1 collector doping region, k is greater than or equal to 1 and less than or equal to M-1, in this embodiment, M is equal to 4, and correspondingly, k is greater than or equal to 1 and less than or equal to 3, the first emitting doping region 221 and the first base doping region 231 are connected to the second collector doping region 212, the second emitting doping region 222 and the second base doping region 232 are connected to the third collector doping region 213, and the third emitting doping region 223 and the third base doping region 233 are connected to the fourth collector doping region 214.
In this embodiment, taking M equal to 4 as an example for explanation, correspondingly, the electrostatic protection structure includes a first current injection doping region 241, a second current injection doping region 242, a third current injection doping region 243 and a fourth current injection doping region 244, the conductivity types of the first current injection doping region 241 to the fourth current injection doping region 244 are all P-type, the first current injection doping region 241 is located in the first well 201, the second current injection doping region 242 is located in the second well 202, the third current injection doping region 243 is located in the third well 203, the fourth current injection doping region 244 is located in the fourth well 204, the first current injection doping region 241 and the first emitter doping region 221 are respectively located on two sides of the first collector doping region 201, the second current injection doping region 242 and the second emitter doping region 222 are respectively located on two sides 243 of the second collector doping region 212, and the third current injection doping region 223 and the third emitter doping region 223 are respectively located on two sides 211 of the third collector doping region 213, the fourth current injection doping region 244 and the fourth emitter doping region 224 are respectively located at two sides of the fourth collector doping region 214.
The ith base doped region, the ith emitter doped region, the ith collector doped region and the ith current injection doped region are separated from each other. In this embodiment, M is 4, the first base doping region 231, the first emitter doping region 221, the first collector doping region 211 and the first current injection doping region 241 are separated from each other, the second base doping region 232, the second emitter doping region 222, the second collector doping region 212 and the second current injection doping region 242 are separated from each other, the third base doping region 233, the third emitter doping region 223, the third collector doping region 213 and the third current injection doping region 243 are separated from each other, and the fourth base doping region 234, the fourth emitter doping region 224, the fourth collector doping region 214 and the fourth current injection doping region 244 are separated from each other.
The first to mth current injection doping regions 241 to 244 are used to inject the adjustment current when the power source terminal VDD generates the transient potential difference, and in particular, in the present embodiment, the first to fourth current injection doping regions 241 to 244 are used to inject the adjustment current when the power source terminal VDD generates the transient potential difference, so that the first to MNPN triacs are turned on, thereby releasing static electricity.
In this embodiment, the first to mth NPN triacs are turned on without being limited by the instantaneous potential difference generated by the power supply terminal, and the power supply terminal VDD is prevented from generating the instantaneous potential difference to turn on the first to mth NPN triacs when the number of NPN triacs is large.
The first to mth current injection doping regions 241 to 241 are connected to an external current adjusting circuit, which injects an adjusting current into the first to mth current injection doping regions 241 to 241 when a power supply terminal Vdd generates an instantaneous potential difference. Specifically, in this embodiment, M is equal to 4, the first current injecting doped region 241 to the fourth current injecting doped region 244 are connected to an external current adjusting circuit, and when the power source generates a transient potential difference, the external current adjusting circuit injects an adjusting current into the first current injecting doped region 241 to the fourth current injecting doped region 244.
in addition, in this embodiment, an appropriate number of NPN type triacs can be selected, that is, M is an appropriate value, so that under a certain transient potential difference of the power source terminal, a voltage that a PN between the ith collector doping region and the ith well region needs to bear is smaller than a reverse breakdown voltage of the PN between the ith collector doping region and the ith well region, which ensures that the PN between the ith collector doping region and the ith well region is not reversely conducted, thereby preventing leakage between the ith collector doping region and the ith base doping region.
In this embodiment, the external current adjusting circuit has a detection connection end, an external injection end, and a ground connection end, the detection connection end is connected to a power supply end Vdd, the ground connection end is connected to a ground terminal VSS, the external injection end includes a first external injection end connected to the mth external injection end, the first external injection end is connected to the first current injection doping region, the mth external injection end is connected to the mth current injection doping region, and the ith external injection end is connected to the ith current injection doping region.
When the external current adjusting circuit detects the instantaneous potential difference of the power supply end Vdd, the external current adjusting circuit is triggered by frequency and generates adjusting current, and the external current adjusting circuit injects the adjusting current into the first current injection doping area to the Mth current injection doping area respectively. Specifically, the adjustment current is injected into the first current injection doping region through the first external injection end, the adjustment current is injected into the mth current injection doping region through the mth external injection end, and the adjustment current is injected into the ith current injection doping region through the ith external injection end.
in this embodiment, the adjustment currents injected into the first current injection doping region to the mth current injection doping region are the same.
In other embodiments, the adjustment currents injected into the first to mth current injection doping regions may be injected respectively through a plurality of external current adjustment circuits, and at this time, the adjustment currents injected into the first to mth current injection doping regions are different.
The higher the instantaneous potential difference generated by the power supply terminal, the larger the regulating current. Such benefits include: the larger the adjusting current is, the faster the first to mth NPN type triacs are turned on, so that the static electricity of the power supply terminal is released more quickly.
the electrostatic protection structure further includes: an isolation well region 250 located between the kth well region and the (k + 1) th well region, wherein the conductivity type of the isolation well region is an N type; the isolation doping layer 251 is located in the isolation well region 250, the conductivity type of the isolation doping layer 251 is N-type, and the isolation doping layer 251 is connected to a power source end VDD.
The isolation doping layer 251 has the function of isolating and preventing latch-up.
In the electrostatic protection structure in this embodiment, since the MOS transistor structure is avoided, there is no problem that the gate dielectric layer is easily broken down when the MOS transistor structure is frequently used for multiple times of turning on and off, and thus the electrostatic protection structure in this embodiment has high reliability.
In the electrostatic protection structure in this embodiment, the turn-on of each NPN type triode belongs to current triggered turn-on, and can combine the advantages of voltage triggered turn-on and frequency triggered turn-on, and specifically, the benefits of current triggered turn-on include: the starting speed is high; the electrostatic discharge path passes through the semiconductor substrate, namely the electrostatic discharge path of the ith NPN type triode is not positioned in the area near the surface of the ith well region, and the electrostatic discharge path of the ith NPN type triode passes through a larger area in the ith well region, so that the heat dissipation is good.
in the electrostatic protection structure in this embodiment, the NPN type triode is used from the first NPN type triode to the mth NPN type triode, and the advantages include: the current carrier of the NPN type triode is electron, the amplification factor beta is larger, the conduction current is larger, and the static electricity discharge is more facilitated; the conducting current of the NPN type triode is larger, so that the occupied area from the first NPN type triode to the Mth NPN type triode is smaller, and the miniaturization of the electrostatic protection structure is facilitated.
Another embodiment of the present invention further provides a method for forming the above electrostatic protection structure, including: providing a semiconductor substrate 200, wherein the semiconductor substrate 200 is provided with a plurality of mutually-separated first well regions to Mth well regions, and the conductivity types of the first well regions to the Mth well regions are P type; forming a first collecting doping area to an Mth collecting doping area, wherein the conductivity types of the first collecting doping area to the Mth collecting doping area are all N-type, the ith collecting doping area is positioned in the ith well area, the first collecting doping area is connected with a power supply end, and i is more than or equal to 1 and less than or equal to M; forming a first emission doping region to an Mth emission doping region, wherein the conductivity types of the first emission doping region to the Mth emission doping region are all N-type, the ith emission doping region is positioned in an ith well region, the Mth emission doping region is connected with a grounding end, and the ith emission doping region is positioned on the side part of an ith collector doping region; forming a first base doping region to an Mth base doping region, wherein the conductivity types of the first base doping region to the Mth base doping region are all P type, the ith base doping region is positioned in an ith well region, the ith base doping region and the ith collector doping region are respectively positioned at two sides of an ith emission doping region, the Mth base doping region is connected with a grounding end, the kth emission doping region and the kth base doping region are connected with a kth +1 collector doping region, and k is more than or equal to 1 and less than or equal to M-1; and forming a first current injection doping area to an Mth current injection doping area, wherein the conductivity types of the first current injection doping area to the Mth current injection doping area are all P-type, the ith current injection doping area is positioned in the ith well region, the ith current injection doping area and the ith emission doping area are respectively positioned at two sides of the ith current collection doping area, and the first injection end to the ith injection end are used for being injected with adjusting current when a power supply end generates an instantaneous potential difference.
The semiconductor substrate 200 further has an isolation well region 250 located between the kth well region and the (k + 1) th well region, and the conductivity type of the isolation well region 250 is N type; the method for forming the semiconductor device further comprises the following steps: an isolation doping layer 251 is formed in the isolation well region 250, the conductivity type of the isolation doping layer 251 is N-type, and the isolation doping layer 251 is connected to a power source terminal VDD.
the first current injection doping region to the Mth current injection doping region are connected with an external current adjusting circuit, and when the power supply end VDD generates an instantaneous potential difference, the external current adjusting circuit injects an adjusting current into the first current injection doping region to the Mth current injection doping region.
The higher the instantaneous potential difference generated by the power supply terminal, the larger the regulating current.
another embodiment of the present invention further provides an electrostatic protection circuit, including:
The first NPN type triode to the Mth NPN type triode, the ith NPN type triode is provided with an ith collector region, an ith emitter region and an ith base region, i is more than or equal to 1 and less than or equal to M, the first collector region is connected with a power supply end, the Mth emitter region is connected with a grounding end, the Mth base region is connected with the grounding end, the kth emitter region and the kth base region are connected with a kth +1 collector region, and k is more than or equal to 1 and less than or equal to M-1;
The first parasitic resistor to the Mth parasitic resistor, the ith parasitic resistor is positioned between the ith emitter region and the ith base region, one end of the ith parasitic resistor, which is connected with the ith emitter region, is an ith injection end, and the first injection end to the ith injection end are used for being injected with adjustment current when the power supply end generates instantaneous potential difference.
The first injection end to the ith injection end are connected with an external current adjusting circuit, and when the power supply end generates an instantaneous potential difference, the external current adjusting circuit injects adjusting current into the first parasitic resistor to the Mth parasitic resistor.
the higher the instantaneous potential difference generated by the power supply terminal, the larger the regulating current.
The invention also provides a working method of the electrostatic protection structure, which comprises the following steps: when the external current adjusting circuit detects the instantaneous potential difference of the power supply end, the external current adjusting circuit is triggered by frequency and generates adjusting current, and the external current adjusting circuit injects the adjusting current into the first current injection doping area to the Mth current injection doping area respectively.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. An electrostatic protection structure, comprising:
The semiconductor device comprises a semiconductor substrate, a first isolation layer and a second isolation layer, wherein the semiconductor substrate is internally provided with a plurality of first well regions to Mth well regions which are separated from each other, and the conduction types of the first well regions to the Mth well regions are P-type;
the first collecting doping area to the Mth collecting doping area, the conductivity types of the first collecting doping area to the Mth collecting doping area are all N-type, the ith collecting doping area is located in the ith well area, the first collecting doping area is connected with a power supply end, and i is more than or equal to 1 and less than or equal to M;
The first emitting doping region to the Mth emitting doping region are all N-type in conductivity type, the ith emitting doping region is located in the ith well region, the Mth emitting doping region is connected with a grounding end, and the ith emitting doping region is located on the side portion of the ith collector doping region;
The conductive types of the first base doped region to the Mth base doped region are P type, the ith base doped region is positioned in the ith well region, the ith base doped region and the ith collector doped region are respectively positioned at two sides of the ith emission doped region, the Mth base doped region is connected with a grounding terminal, the kth emission doped region and the kth base doped region are connected with the kth +1 collector doped region, and k is more than or equal to 1 and less than or equal to M-1;
the first current injection doping region to the Mth current injection doping region are all of P type in conductivity type, the ith current injection doping region is located in the ith well region, the ith current injection doping region and the ith emission doping region are respectively located on two sides of the ith collection doping region, and the first current injection doping region to the Mth current injection doping region are used for being injected with adjusting current when a power supply end generates an instantaneous potential difference.
2. the ESD protection structure of claim 1 wherein the first through Mth current injection doped regions are connected to an external current adjustment circuit, and the external current adjustment circuit injects an adjustment current into the first through Mth current injection doped regions when the power source generates a transient potential difference.
3. The esd structure of claim 1, wherein the adjustment current is larger for higher instantaneous potential difference generated by the power terminals.
4. The electrostatic protection structure of claim 1, further comprising: the isolation well region is positioned between the kth well region and the (k + 1) th well region, and the conductivity type of the isolation well region is N type; and the isolation doping layer is positioned in the isolation well region, the conductivity type of the isolation doping layer is N-type, and the isolation doping layer is connected with a power supply end.
5. A method for forming an electrostatic protection structure, comprising:
Providing a semiconductor substrate, wherein the semiconductor substrate is internally provided with a plurality of first well regions to Mth well regions which are separated from each other, and the conductivity types of the first well regions to the Mth well regions are P type;
Forming a first collecting doping area to an Mth collecting doping area, wherein the conductivity types of the first collecting doping area to the Mth collecting doping area are all N-type, the ith collecting doping area is positioned in the ith well area, the first collecting doping area is connected with a power supply end, and i is more than or equal to 1 and less than or equal to M;
Forming a first emission doping region to an Mth emission doping region, wherein the conductivity types of the first emission doping region to the Mth emission doping region are all N-type, the ith emission doping region is positioned in an ith well region, the Mth emission doping region is connected with a grounding end, and the ith emission doping region is positioned on the side part of an ith collector doping region;
Forming a first base doping region to an Mth base doping region, wherein the conductivity types of the first base doping region to the Mth base doping region are all P type, the ith base doping region is positioned in an ith well region, the ith base doping region and the ith collector doping region are respectively positioned at two sides of an ith emission doping region, the Mth base doping region is connected with a grounding end, the kth emission doping region and the kth base doping region are connected with a kth +1 collector doping region, and k is more than or equal to 1 and less than or equal to M-1;
and forming a first current injection doping region to an Mth current injection doping region, wherein the conductivity types of the first current injection doping region to the Mth current injection doping region are all P-type, the ith current injection doping region is positioned in the ith well region, the ith current injection doping region and the ith emission doping region are respectively positioned at two sides of the ith current collection doping region, and the first current injection doping region to the Mth current injection doping region are used for being injected with adjusting current when an instantaneous potential difference is generated at a power supply end.
6. The method as claimed in claim 5, wherein the semiconductor substrate further has an isolation well region located between the kth well region and the k +1 th well region, and the conductivity type of the isolation well region is N type; the method for forming the semiconductor device further comprises the following steps: and forming an isolation doping layer in the isolation well region, wherein the conductivity type of the isolation doping layer is N type, and the isolation doping layer is connected with a power supply end.
7. The method as claimed in claim 5, wherein the first to Mth current injection doping regions are connected to an external current adjusting circuit, and the external current adjusting circuit injects an adjusting current into the first to Mth current injection doping regions when the power source terminal generates a transient potential difference.
8. The method for forming a semiconductor device according to claim 5, wherein the adjustment current is larger as the transient potential difference generated at the power source terminal is higher.
9. An electrostatic protection circuit, comprising:
The first NPN type triode to the Mth NPN type triode, the ith NPN type triode is provided with an ith collector region, an ith emitter region and an ith base region, i is more than or equal to 1 and less than or equal to M, the first collector region is connected with a power supply end, the Mth emitter region is connected with a grounding end, the Mth base region is connected with the grounding end, the kth emitter region and the kth base region are connected with a kth +1 collector region, and k is more than or equal to 1 and less than or equal to M-1;
The first parasitic resistor to the Mth parasitic resistor, the ith parasitic resistor is positioned between the ith emitter region and the ith base region, one end of the ith parasitic resistor, which is connected with the ith emitter region, is an ith injection end, and the first injection end to the ith injection end are used for being injected with adjustment current when the power supply end generates instantaneous potential difference.
10. The esd protection circuit of claim 9, wherein the first to ith injection terminals are connected to an external current adjusting circuit, and the external current adjusting circuit injects an adjusting current into the first to mth parasitic resistors when the power source terminal generates the transient potential difference.
11. The esd protection circuit of claim 9, wherein the adjustment current is larger the higher the instantaneous potential difference generated by the power terminal.
12. A method of operating an electrostatic protection arrangement according to any of claims 1 to 4, comprising: when the external current adjusting circuit detects the instantaneous potential difference of the power supply end, the external current adjusting circuit is triggered by frequency and generates adjusting current, and the external current adjusting circuit injects the adjusting current into the first current injection doping area to the Mth current injection doping area respectively.
CN201810575868.2A 2018-06-06 2018-06-06 Electrostatic protection structure, forming method and working method thereof, and electrostatic protection circuit Pending CN110571212A (en)

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CN1614779A (en) * 2003-11-05 2005-05-11 三洋电机株式会社 Static electricity damage preventor
US7298599B1 (en) * 2004-08-13 2007-11-20 National Semiconductor Corporation Multistage snapback ESD protection network
US20080062595A1 (en) * 2006-08-30 2008-03-13 Ping Andrew T Electrostatic discharge protection circuit for compound semiconductor devices and circuits
CN104183596A (en) * 2013-05-22 2014-12-03 中芯国际集成电路制造(上海)有限公司 Electrostatic discharge protection structure
US9153571B1 (en) * 2014-07-07 2015-10-06 United Microelectronics Corporation Stacked electrostatic discharge (ESD) protection device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1614779A (en) * 2003-11-05 2005-05-11 三洋电机株式会社 Static electricity damage preventor
US7298599B1 (en) * 2004-08-13 2007-11-20 National Semiconductor Corporation Multistage snapback ESD protection network
US20080062595A1 (en) * 2006-08-30 2008-03-13 Ping Andrew T Electrostatic discharge protection circuit for compound semiconductor devices and circuits
CN104183596A (en) * 2013-05-22 2014-12-03 中芯国际集成电路制造(上海)有限公司 Electrostatic discharge protection structure
US9153571B1 (en) * 2014-07-07 2015-10-06 United Microelectronics Corporation Stacked electrostatic discharge (ESD) protection device

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