JPS62183181A - Field-effect transistor and manufacture thereof - Google Patents

Field-effect transistor and manufacture thereof

Info

Publication number
JPS62183181A
JPS62183181A JP61024365A JP2436586A JPS62183181A JP S62183181 A JPS62183181 A JP S62183181A JP 61024365 A JP61024365 A JP 61024365A JP 2436586 A JP2436586 A JP 2436586A JP S62183181 A JPS62183181 A JP S62183181A
Authority
JP
Japan
Prior art keywords
electrode
electrolytic
substrate
film
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61024365A
Other languages
Japanese (ja)
Inventor
Kenichi Takeyama
竹山 健一
Shigeo Kondo
繁雄 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61024365A priority Critical patent/JPS62183181A/en
Publication of JPS62183181A publication Critical patent/JPS62183181A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40Organic transistors
    • H10K10/46Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462Insulated gate field-effect transistors [IGFETs]
    • H10K10/466Lateral bottom-gate IGFETs comprising only a single gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/10Organic polymers or oligomers
    • H10K85/111Organic polymers or oligomers comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10Deposition of organic active material
    • H10K71/12Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/125Deposition of organic active material using liquid deposition, e.g. spin coating using electrolytic deposition e.g. in-situ electropolymerisation

Abstract

PURPOSE:To enable field effect transistors to be formed formed evenly in high concentration on a large substrate by a method wherein a gate electrode, an insulating film, a semiconductor layer comprising organic high molecule formed by electrolytic polymerication are formed on an insulating substrate and then a source electrode and a drain electrode are formed thereon. CONSTITUTION:A gate electrode 2 is formed on an insulating substrate 1; an insulating film 3 is formed on the gate electrode 2 by electron beam evaporation an electrolytic polymerized film 4 is formed by impressing the insulating periodic reverse bias voltage for specific time using the gate electrode 2 as an anode; and then a source electrode 5 and a drain electrode 6 and formed on the film 4. In order to form the electrolytic polymerized film 4, an electrolytic bath containing electrolyte comprising, e.g., 1.0g of pyrrole, 1.2g of lithium borofluoride and 1,000ml of acetonitride is prepared; platinum sheet as cathode, silane wire as reference electrode are provided; the substrate 1 is impressed with 0.68V as normal bias for reference electrode for two seconds and 0.5V as reverse bias for two seconds to perform the electrolytic polymerization for two hours for cleaning the substrate 1. By means of this electrolytic polymerization, the dispersion of element characteristics can be controlled.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電界効果トランジスタおよびその製造方法に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a field effect transistor and a method for manufacturing the same.

従来の技術 従来、電界効果トランジスタは、半導体としてシリコン
、ゲルマニュウムなどの単結晶基板を用いていた。この
単結晶基板を用いる方法では、半導体製造装置の制約か
ら、大面積化は困難である。
2. Description of the Related Art Conventionally, field effect transistors have used single crystal substrates of silicon, germanium, etc. as semiconductors. With this method using a single crystal substrate, it is difficult to increase the area due to restrictions on semiconductor manufacturing equipment.

また、アモルファスシリコン、ポリシリコンを半導体に
使って電界効果トランジスタを製造する方法力する。ア
モルファスシリコンやポリシリコンはプラズマ堆積法を
使って作られている。電界効果トランジスタなどの能動
素子を均一に、大面積に製造することに、前述のシリコ
ンと同様に半導体製造装置の制約や、プラズマ制御の困
難さなどの欠点を有していた。無機半導体では前述の欠
点を有するので、有機高分子を半導体として使った技術
が提案(例えば特開昭58−114465号公報など)
されている。しかし、この提案されている有機高分子半
導体の製造方法は、大面積の基板に触媒を塗布しその後
原料ガスを基板上に導入する方法である。しかし、触媒
を大面積に均一に塗布することが困難であり、さらに、
原料ガスを大面積に均一に導入することも困難である。
We will also discuss methods for manufacturing field effect transistors using amorphous silicon and polysilicon as semiconductors. Amorphous silicon and polysilicon are made using plasma deposition. Similar to the aforementioned silicon, silicon has drawbacks such as limitations on semiconductor manufacturing equipment and difficulty in plasma control when it comes to uniformly manufacturing active elements such as field effect transistors over a large area. Since inorganic semiconductors have the above-mentioned drawbacks, a technology using organic polymers as semiconductors has been proposed (for example, Japanese Patent Application Laid-Open No. 114465/1982).
has been done. However, this proposed method for producing an organic polymer semiconductor is a method in which a catalyst is applied to a large-area substrate, and then a raw material gas is introduced onto the substrate. However, it is difficult to apply the catalyst uniformly over a large area, and
It is also difficult to introduce raw material gas uniformly over a large area.

発明が解決しようとする問題点 本発明は電界効果トランジスタを大面積基板に高密度お
よび均一に形成しようとするものである。
Problems to be Solved by the Invention The present invention attempts to form field effect transistors uniformly and densely on a large area substrate.

問題点を解決するための手段 絶縁基板上に形成したゲート電極と、前記ゲート電極を
被覆する絶縁膜と、前記絶縁膜上に電解重合法で形成し
た有機高分子からなる半導体層と、前記半導体層上に形
成したソース電極およびドレーン電極とをそなえた電界
効果トランジスタを構成する。
Means for Solving the Problems A gate electrode formed on an insulating substrate, an insulating film covering the gate electrode, a semiconductor layer made of an organic polymer formed on the insulating film by electrolytic polymerization, and the semiconductor A field effect transistor is constructed with a source electrode and a drain electrode formed on the layer.

作用 電解重合法によシ形成される有機高分子膜は、大面積の
場合であっても、均一に作成することが容易である。
Organic polymer films formed by electrolytic polymerization can be easily produced uniformly even if they have a large area.

実施例 発明者らは、電解重合法において、絶縁膜に被覆された
電極に電解重合膜を形成する方法を見いだした。すなわ
ち、電解中に周期的に一定時間逆バイアスを電極に印加
するものである。
EXAMPLE The inventors have discovered a method of forming an electrolytic polymer film on an electrode covered with an insulating film using an electrolytic polymerization method. That is, a reverse bias is periodically applied to the electrode for a certain period of time during electrolysis.

この方法によシミ解重合膜を得ることができる理由は以
下のように推測される。
The reason why a stain depolymerized film can be obtained by this method is presumed to be as follows.

絶縁膜として例えば酸化タングステン(以下WO,) 
 を用いた場合を例示し説明する。
For example, tungsten oxide (hereinafter referred to as WO) can be used as an insulating film.
An example will be explained using the following.

モノマを溶解した極性溶媒の電解液中で、陰極として白
金電極、陽極としてWO3を被覆した電極を用いて、周
期的に一定時間の逆バイアスを印加し電解酸化を行なう
。逆バイアス印加時W03は式1に示すように還元され
る(式中M は水素。
Electrolytic oxidation is carried out in an electrolytic solution of a polar solvent in which a monomer is dissolved, using a platinum electrode as a cathode and an electrode coated with WO3 as an anode, by periodically applying a reverse bias for a certain period of time. When reverse bias is applied, W03 is reduced as shown in formula 1 (in the formula, M is hydrogen.

リチウム、ナトリウムなど一価の陽イオンを示す)。(Indicates monovalent cations such as lithium and sodium).

生成したMWO3は電子伝導性となる。The generated MWO3 becomes electronically conductive.

WO+M”+a  −Q MWO・旧−・1次に正バイ
アス時にMWO,は式2に示すように酸化される。
WO+M"+a -Q MWO/Old-/MWO is oxidized as shown in Equation 2 during the primary positive bias.

MWO3−+  No、+M  +e  =−・−2正
バイアス時にMWO3から電子の引き抜きがおこり、該
膜は電子伝導性から絶縁性へと変化する。
MWO3−+ No, +M +e =−·−2 At the time of positive bias, electrons are withdrawn from MWO3, and the film changes from electron conductivity to insulating property.

この際反応に時間的な遅れがあり、電子伝導性を保持し
ている間に該膜表面で会合し重合する。
At this time, there is a time delay in the reaction, and while electron conductivity is maintained, the molecules aggregate and polymerize on the membrane surface.

本発明を適用しうる絶縁膜としては、WO3のほかに、
酸化モリブデン(MOO3)+酸化チタン(Tie)、
酸化タンタル(Ta、O,)、酸化ニオブ(Wb205
)l酸化シリコン(S10□)、酸化スズ(SnO□)
、五酸化バナジウム(v205)など陽イオンのインタ
カレション可能な酸化物は全て挙げることができる。ま
た、酸化膜としては熱酸化法、抵抗加熱蒸着法、スパッ
タ蒸着法、電子ビーム蒸着法、プラズマ堆積法、光分解
気相堆積法、熱分解気相堆積法および電解酸化法などに
よって得られる膜が有効に作用することは自明である。
Insulating films to which the present invention can be applied include, in addition to WO3,
Molybdenum oxide (MOO3) + titanium oxide (Tie),
Tantalum oxide (Ta, O,), niobium oxide (Wb205
)l Silicon oxide (S10□), tin oxide (SnO□)
, vanadium pentoxide (v205), and other oxides capable of intercalating cations. In addition, the oxide film may be a film obtained by thermal oxidation method, resistance heating evaporation method, sputter evaporation method, electron beam evaporation method, plasma deposition method, photolytic vapor deposition method, pyrolytic vapor deposition method, electrolytic oxidation method, etc. It is obvious that this works effectively.

さらに、本発明は電解重合しうるモノマすべてに適用可
能であるが、とくに例示すると以下のとおりである。す
なわち、ピロール、チオフェン、N−メチルピロール、
3メチルチオフエン。
Furthermore, although the present invention is applicable to all electrolytically polymerizable monomers, the following are particularly exemplified. That is, pyrrole, thiophene, N-methylpyrrole,
3-methylthiophene.

ナフトチオフェンなどの五員環化合物、アニリン。Five-membered ring compounds such as naphthothiophene, aniline.

フェノールなどで代表される芳香族化合物、ジペンゾク
ラウンエーテル、ビニルピリジンなどのビニル基を含む
化合物などを挙げることができる。
Examples include aromatic compounds typified by phenol, compounds containing vinyl groups such as dipenzocrown ether, and vinylpyridine.

この様に絶縁膜上に、電解重合膜を形成できることによ
り、電界効果トランジスタの製造を容易にするとともに
、従来の欠点である大面積基板に、高密度に電解効果ト
ランジスタを集積できるものである。
By being able to form an electrolytically polymerized film on an insulating film in this way, it is possible to easily manufacture field effect transistors and to integrate field effect transistors at high density on a large area substrate, which is a disadvantage of the conventional method.

以下、図面を用いて本発明の電界効果トランジスタにつ
いて説明する。
Hereinafter, the field effect transistor of the present invention will be explained using the drawings.

第1図は本発明の一実施例である電界効果トランジスタ
の素子断面図であシ、1は絶縁基板、2はゲート電極、
3は絶縁膜、4は半導体層を構成する電解重合膜、6,
6はソース電極およびドレイン電極である。
FIG. 1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention, in which 1 is an insulating substrate, 2 is a gate electrode,
3 is an insulating film, 4 is an electrolytic polymer film constituting a semiconductor layer, 6,
6 is a source electrode and a drain electrode.

絶縁基板1上にグー11極2を形成し、ゲート電極2上
に電子ビーム蒸着法で絶縁膜3を形成し、ゲート電極2
を陽極として、周期的に一定時間逆バイアス印加する方
法で電解重合膜4を形成し、電解重合膜4上にソース電
極5およびドレーン電極6を形成する。
A goo 11 electrode 2 is formed on an insulating substrate 1, an insulating film 3 is formed on the gate electrode 2 by electron beam evaporation, and the gate electrode 2 is formed.
An electrolytic polymer film 4 is formed by applying a reverse bias periodically for a certain period of time using the anode as an anode, and a source electrode 5 and a drain electrode 6 are formed on the electrolytic polymer film 4.

以上の如くにして、電界効果トランジスタを形成する事
が可能となることが判明した。
It has been found that it is possible to form a field effect transistor in the manner described above.

以下、実施例をもとにして本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail based on examples.

実施例1 絶縁基板1としてガラス基板を用い、アルミニュウムを
蒸着し、次に公知のホトリソグラフ法でパターニングし
、ゲート長60μm、ゲート幅6顛のゲート電極を形成
した。次に、ゲート電極2上に絶縁膜3として、電子ビ
ーム蒸着法で酸化タングステン膜を2000人形成した
。次に、電解液トしてピロール1.0g、ホウフッ化リ
テユウム1.2g、アセトニトリル1oornlを入れ
た電解浴を準備し、陰極として白金板、参照電極として
銀線を設置した。陽極に前述の基板を設置し、正バイア
スとして、参照電極に対して0・SSVを2秒、逆バイ
アスとして−0,6vを2秒間印加し、2時間電解重合
を行なった。次に、アセトニトリルついで、水で基板を
洗浄し、未反応モノマおよび電解質をのぞいた。次に、
金からなるソース電極5およびドレーン電極6を形成し
た。
Example 1 A glass substrate was used as the insulating substrate 1, and aluminum was vapor-deposited and then patterned by a known photolithography method to form a gate electrode with a gate length of 60 μm and a gate width of 6 times. Next, 2,000 tungsten oxide films were formed as insulating films 3 on the gate electrodes 2 by electron beam evaporation. Next, an electrolytic bath containing 1.0 g of pyrrole, 1.2 g of lithium borofluoride, and 100 ml of acetonitrile was prepared as an electrolytic solution, and a platinum plate was installed as a cathode and a silver wire was installed as a reference electrode. The aforementioned substrate was placed on the anode, and a positive bias of 0.SSV was applied to the reference electrode for 2 seconds, and a reverse bias of -0.6 V was applied for 2 seconds to carry out electrolytic polymerization for 2 hours. Next, the substrate was washed with acetonitrile and then water to remove unreacted monomer and electrolyte. next,
A source electrode 5 and a drain electrode 6 made of gold were formed.

このようにして製造した電界効果トランジスタの出力特
性を第2図に示す。
FIG. 2 shows the output characteristics of the field effect transistor manufactured in this manner.

実施例2 実施例1における電界効果トランジスタに用いた絶縁膜
3として、酸化タングステンのかわりに酸化チタンを用
いた以外は実施例1と全く同様に構成した。但し、電解
重合膜の形成条件は、酸化タングステンの時とは異なり
、逆バイアスを−1、OVとし、他は全く同一条件とし
た。こうして得られたトランジスタの出力特性は実施例
1とほとんど同一のものが得られた。
Example 2 The structure was exactly the same as in Example 1 except that titanium oxide was used instead of tungsten oxide as the insulating film 3 used in the field effect transistor in Example 1. However, the conditions for forming the electropolymerized film were different from those for tungsten oxide, except that the reverse bias was -1 and OV, and the other conditions were exactly the same. The output characteristics of the transistor thus obtained were almost the same as in Example 1.

なお絶縁基板としては、ガラス、プラスチックフィルム
など、どのようなものも使用可能である。
Note that any material such as glass or plastic film can be used as the insulating substrate.

発明の効果 本発明によれば、有機高分子膜を電解重合法を用いて絶
縁膜上に簡単にそして均一に形成することができる。
Effects of the Invention According to the present invention, an organic polymer film can be easily and uniformly formed on an insulating film using an electrolytic polymerization method.

その結果、容易に電界効果トランジスタを大面積基板に
、高密度に得ることができる。
As a result, field effect transistors can be easily formed on a large substrate with high density.

また、電解重合法を用いたため、素子の特性上のバラツ
キを制御することが可能である。
Furthermore, since an electrolytic polymerization method was used, it is possible to control variations in device characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の電界効果トランジスタの素
子断面図、第2図は同実施例の電界効果トランジスタの
出力特性を示す図である。 1・・・・・・絶縁基板、2・・・・・・ゲ°−ト電極
、3・・・・・・絶縁膜、4・・・・・・電解重合膜、
6・・・・・・ソース電極、6・・・・・・トレー7電
極。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 oz4   乙  13   t。 VDCボルト)
FIG. 1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention, and FIG. 2 is a diagram showing output characteristics of the field effect transistor according to the same embodiment. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3... Insulating film, 4... Electrolytic polymerization film,
6... Source electrode, 6... Tray 7 electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 oz4 Otsu 13t. VDC volt)

Claims (3)

【特許請求の範囲】[Claims] (1)絶縁基板上に形成したゲート電極と、前記ゲート
電極を被覆する絶縁膜と、前記絶縁膜上に直接電解重合
法で形成した有機高分子膜からなる半導体層と、前記半
導体層に接して設けたソース電極およびドレーン電極と
を備えたことを特徴とする電界効果トランジスタ。
(1) A gate electrode formed on an insulating substrate, an insulating film covering the gate electrode, a semiconductor layer consisting of an organic polymer film formed directly on the insulating film by electrolytic polymerization, and a semiconductor layer in contact with the semiconductor layer. A field effect transistor comprising a source electrode and a drain electrode.
(2)絶縁基板上にゲートとなる電極を形成する工程と
、絶縁膜を前記ゲート電極上に形成する工程と、有機高
分子膜を前記絶縁膜上に電解重合法で形成する工程と、
ソース電極・ドレーン電極を前記有機高分子膜上に形成
する工程とを含むことを特徴とする電界効果トランジス
タ製造方法。
(2) forming an electrode to serve as a gate on an insulating substrate; forming an insulating film on the gate electrode; and forming an organic polymer film on the insulating film by electrolytic polymerization;
A method for manufacturing a field effect transistor, comprising the step of forming a source electrode and a drain electrode on the organic polymer film.
(3)有機高分子膜を前記絶縁膜上に電解重合法で形成
する工程において、周期的に一定時間逆バイアスを印加
することを特徴とする特許請求の範囲第2項記載の電界
効果トランジスタ製造方法。
(3) Manufacturing a field effect transistor according to claim 2, wherein in the step of forming an organic polymer film on the insulating film by electrolytic polymerization, a reverse bias is periodically applied for a certain period of time. Method.
JP61024365A 1986-02-06 1986-02-06 Field-effect transistor and manufacture thereof Pending JPS62183181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61024365A JPS62183181A (en) 1986-02-06 1986-02-06 Field-effect transistor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61024365A JPS62183181A (en) 1986-02-06 1986-02-06 Field-effect transistor and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS62183181A true JPS62183181A (en) 1987-08-11

Family

ID=12136166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61024365A Pending JPS62183181A (en) 1986-02-06 1986-02-06 Field-effect transistor and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS62183181A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02194664A (en) * 1989-01-24 1990-08-01 Fujitsu Ltd Superconducting device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114465A (en) * 1981-12-26 1983-07-07 Nippon Telegr & Teleph Corp <Ntt> High molecular semiconductor field effect transistor and manufacture thereof
JPS6285467A (en) * 1985-10-09 1987-04-18 Mitsubishi Electric Corp Field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114465A (en) * 1981-12-26 1983-07-07 Nippon Telegr & Teleph Corp <Ntt> High molecular semiconductor field effect transistor and manufacture thereof
JPS6285467A (en) * 1985-10-09 1987-04-18 Mitsubishi Electric Corp Field effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02194664A (en) * 1989-01-24 1990-08-01 Fujitsu Ltd Superconducting device

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