JPS62183180A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the resistance values of a gate electrode, source and drain regions of MISFET while preventing oxidation from occuring by a method wherein high melting point metallic films and a non-oxidizable metallic film are formed on the gate electrode, source and drain regions to make the high melting point metals, the non-oxidiable metal and silicon combine with one another so that high melting point metallic silicide films may be formed on the upper parts of respective elements. CONSTITUTION:A field insulating film 2, a p-type channel stopper region 3, a gate insulating film 4 are formed on the surface of a p<-> type substrate 1 and then a polycrystalline silicon film (gate electrode) 5 is formed into specified shape by etching process in a gate electrode forming forming region. Next, an n-type semiconductor region 7 is formed in a source.drain forming region. Then, in the process of forming insulating films 8 (sidewalls) on the sides of film 5 from the sidewalls of film 5 with excellent controllability of film thickness and self alignment with the film 5, the surface of film 5 and the main surface of semiconductor region 7 are exposed to be successively laminated with a high melting point metallic film 6C and non-oxidizable metallic film 6D. Next, a high melting point metallic silicide film 6A is formed on the film 5 to complete an electrode G, besides, n-type impurity is led to the main surface of substrate 1 through another high melting point metallic silicide film 6b formed on the region 7 and finally a source region S and a drain region D comprising a semiconductor region 9 and the semiconductor region 7 are formed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device.

The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with a MISFET.

[Conventional technology]

In a semiconductor integrated circuit device equipped with an MI S FET,
There is a trend toward increasing the operating speed of MIS FETs.

Therefore, from June 25 to 26, 1985, the International VLSI Multilevel Interconnection Conference (1985
IEEE 2nd International VLS
I Multilevel Interconnect
ion Conference, June 25-
The technique described in 26) is known. This technology is
This is intended to reduce the resistance values of the gate electrode, source region, and drain region, and to increase the operating speed of the MISFET:T. Specifically, it can be formed by the following manufacturing method.

First, a gate electrode made of polycrystalline silicon film is formed,
An absolute # film (sidewall) with good film thickness controllability is formed on the sides of this gate electrode. After this.

A high melting point metal film, such as a tungsten (W) film, is formed by selective CVD on the main surface of the semiconductor substrate in the gate electrode and the source and drain region formation regions. Then, heat treatment is performed to combine silicon and tungsten, and a tungsten silicide film is formed on the gate electrode and on the source region and drain region formation regions. The tungsten silicide film has a specific resistance value lower than that of the polycrystalline silicon film, the source region, and the drain region, and can reduce the resistance values thereof.

The MISFET formed in this way has a structure on the gate electrode,
Since the tungsten silicide film can be formed on the source region and the drain region in the same manufacturing process, the manufacturing process can be reduced.

[Problem that the invention seeks to solve]

As a result of experiments and studies on this technology, the inventor found that the following problems occurred.

The high melting point metal film such as the tungsten film is very easily oxidized during the heat treatment process, for example, its silicidation process.The oxidation rate is faster than the silicide formation rate between the high melting point metal and silicon. Since most of the melting point metal film is formed as an oxide film, the resistance values of the gate electrode, source region, and drain region cannot be made sufficiently low.

In other words, the operating speed of the MI S FET cannot be increased as much as in Figure 9.

On the other hand, in order to solve the above problems, it is conceivable to form an insulating film for preventing oxidation on the gate electrode, the source region formation region, and the drain region formation region. However, a trace amount of oxygen is mixed in during the process of forming an insulating film for oxidation prevention.

As mentioned above, the high melting point metal film is oxidized.

Further, in the silicidation process, in order to prevent oxidation of the high melting point metal film, it is necessary to form a thick insulating film for preventing oxidation. For this reason.

When connecting the gate electrode, source region, and drain region to the upper layer wiring, a step of removing an insulating film for preventing oxidation is required, which increases the number of manufacturing steps.

The purpose of the present invention is to prevent oxidation of high melting point metal films and
An object of the present invention is to provide a technique that can reduce the resistance values of a gate electrode, source region, and drain region of an FET.

Another object of the present invention, in addition to the above object, is to
An object of the present invention is to provide a technology that can reduce the number of manufacturing steps for a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device equipped with a MISFET, a high-melting point metal film and an oxidation-resistant metal film are formed on the gate electrode, the source region, and the drain region, and the high-melting point metal, the oxidation-resistant metal, and silicon are combined. Then, a high melting point metal silicide film is formed on top of each.

[For production]

According to the above means, the oxidation-resistant metal film can prevent the high melting point metal film from being oxidized, so the resistance values of the gate electrode, source region, and drain region of the MISFET can be reduced. In other words, the operating speed of the MI S FET can be increased.

In addition, since the oxidation-resistant metal is formed on the high-melting point metal silicide, it is possible to reduce the resistance value and prevent the oxidation of the high-melting point metal film, thereby eliminating the step of removing the oxide. According to the latter, manufacturing steps can be reduced.

〔Example〕

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

In all the figures, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.

MI of a semiconductor integrated circuit device which is an embodiment of the present invention
The S FET is shown in FIG. 1 (cross-sectional view of main parts).

In FIG. 1, 1 is a p-type semiconductor substrate (or well region) made of single crystal silicon, 2 is a field insulating film, and 3 is a p-type channel stopper region. The field insulating film 2 and the channel stopper region 3 are provided on the main surface of the semiconductor substrate 1 in the semiconductor element formation region, and are configured to electrically isolate the semiconductor elements.

The n-channel MISFET is provided on the main surface of the semiconductor substrate l in a region surrounded by the field insulating film 2. That is, the MISFET consists of a semiconductor substrate 1, a gate insulating film 4
．． It is composed of a gate electrode G, a source region S, and a drain region.

The gate electrode G is composed of a polycrystalline silicon film 5 doped with an impurity (for example, phosphorus or arsenic) that reduces the resistance value, and a high melting point metal silicide film 6A provided on top of the polycrystalline silicon film 5. The high melting point metal silicide film 6A has a lower specific resistance value than the polycrystalline silicon film 5, and contributes to increasing the operating speed of the MISFET.

The source region S and the drain region are composed of an n-type (low concentration) semiconductor region 7 and an n'-type (high concentration) semiconductor region 9. The semiconductor region 7 is provided between the semiconductor region 9 and the channel forming region, and is located at WLD.
It forms a D (Light, once-operated-rain) structure. A high melting point metal silicide film 6 is formed on the main surfaces of the source region S and the drain region.
B is provided. This high melting point metal silicide film 6B
is configured to reduce the substantial resistance value of the source region S and drain region, and contributes to increasing the operating speed of the MISFET.

Reference numeral 8 denotes an insulating film provided on the side of the gate electrode G, and is configured to prevent short-circuiting between the high melting point metal silicides 1i6A and 6B when they are formed. Further, the insulating film 8 constitutes a mask for introducing impurities to form the semiconductor region 9.

Reference numeral 10 denotes a glabella insulating film covering the M I S FET, 11 a contact hole provided in the interlayer insulating film 10, and 12 a wiring connected to the source region S or drain region through the contact hole 11.

Next, a method for manufacturing the MISFET configured as described above will be explained using FIGS. 2 to 7 (cross-sectional views showing each manufacturing process).

First, a field insulating film 2 and a p-type channel stopper region 3 are formed on the main surface of an n-type semiconductor substrate l made of single crystal silicon.

Thereafter, a gate insulating film 4 is formed on the main surface of the semiconductor substrate 1 in the semiconductor element formation region.

As shown in FIG. 2, a polycrystalline silicon film (gate electrode) is formed on the upper part of the gate insulating film 4 in the gate electrode formation region.
form 5. Polycrystalline silicon film.

After forming by CVD, an impurity to reduce the resistance value is introduced by thermal diffusion or ion implantation, and then etching is performed to form a predetermined shape. The polycrystalline silicon film 5 is, for example,
It is formed with a film thickness of about 3000 to 4000 [λ].

After the step of forming the polycrystalline silicon film 5 shown in FIG. 2, as shown in FIG. 3, an n-type semiconductor region 7 is formed on the main surface of the semiconductor substrate 1 in the source region and drain region formation region. The semiconductor region 7 is formed using an n-type impurity (for example,
It can be formed by introducing phosphorus) using ion implantation technology.

After the step of forming the semiconductor region 7 shown in FIG.
As shown in the figure, there are no gaps 811 on the sides of the polycrystalline silicon film 5.
18 (side wall) is formed. The insulating film 8 is formed, for example, by performing anisotropic etching such as reactive ion etching on a silicon oxide film formed by CvD and having a thickness of about 4,000 to 5,000 ml. The insulation [8] formed in this manner has good controllability in film thickness from the sidewall of the polycrystalline silicon rIA5.

Moreover, it is formed in self alignment with the polycrystalline silicon film 5. Note that in the step of forming the insulating film 8, the upper surface of the polycrystalline silicon film 5 and the main surface of the semiconductor region 7 are exposed.

After the step of forming the insulating film 8 shown in FIG.

As shown in FIG. 5, a high melting point metal film 6C and an oxidation-resistant metal film 6D are sequentially laminated to cover the exposed polycrystalline silicon film 5 and semiconductor region 7 so as to be in contact with them.

The high melting point metal film 6C is made of, for example, molybdenum (Mo) or tantalum (Ta) so that the gate electrode can be silicided.
, titanium (T i ), tungsten (W), or a combination thereof. The high melting point metal film 6c.

For example, it is formed by CVD or sputtering, and
It is formed with a film thickness of about 00 [λ]. Also, 1 ton of high melting point metal! I6C is a polycrystalline silicon film 5. It may be formed by selective CVD, which is selectively formed on silicon such as the semiconductor region 7.

The oxidation-resistant metal film 6D is made of, for example, platinum (pt) or nickel (Ni) to prevent oxidation of the high melting point metal film 6C.
), palladium (Pd), gold (Au), and other noble metals. The oxidation-resistant metal film 6D is, for example,
It is formed by sputtering to a film thickness of about several tens to several hundreds [λ]. Oxidation resistant metal! Although ll6D is preferably a material that combines with silicon, it is not necessarily limited to this.

High melting point metal film 6C and oxidation-resistant metal film 6D shown in FIG.
After the step of forming , high melting point metal silicide films 6A and 6B are formed on the polycrystalline silicon film 5'' and the main surface of the semiconductor region 7, as shown in FIG. By forming this high melting point metal silicide film 6A, a gate consisting of the polycrystalline silicon film 5 and the high melting point metal silicide film 6A is formed.
, polar G is completed. The high melting point metal silicide l1g6
A and 6B are the silicon of the polycrystalline silicon film 5 or the semiconductor region 7 which has been subjected to a heat treatment of about 900 to 1000 ['c].

It can be formed by combining a high melting point metal and an oxidation resistant metal.

Note that the high melting point metal film 6C and the oxidation-resistant metal film 6D formed on the insulating film 8 and the field insulating film 2 do not combine with silicon.

After the step of forming the high melting point metal silicide films 6A and 6B shown in FIG. 6, the high melting point metal film 6C and the oxidation-resistant metal 11ff6D that do not combine with silicon are removed.

Then, n-type impurities are introduced into the main surface of the semiconductor substrate 1 through the high melting point metal silicide film 6B.

As shown in FIG. 7, an n-type semiconductor region 9 is formed. The semiconductor region 9 can be formed by introducing impurities by ion implantation using the gate electrode G, the insulating film 8, and the field isolation #C film 2 as masks for impurity introduction. By forming this semiconductor region 9, a source region S and a drain region made up of the semiconductor region 9 and the semiconductor region 7 are completed, and a MISFET is also completed.

In this way, the oxidation-resistant metal film 6D is formed on the high melting point metal film 6C, and then the top of the polycrystalline silicon film 5 and the main surface of the semiconductor region 7 are silicided to form the high melting point metal film Since oxidation of 6C can be prevented and most of the high melting point metal film 6C can be silicided, the resistance values of the gate electrode G, source region S, and drain region of the MISFET can be reduced. That is, MISFETr
The operating speed can be increased.

Furthermore, since the oxidation-resistant metal film 6D is formed as the high melting point metal silicide films 6A and 6B, the resistance values of the gate electrode G, source region S, and drain region can be further reduced.

Further, since the oxidation-resistant metal film 6D can prevent the high melting point metal film 6C from being oxidized, the process of removing the oxide can be eliminated, and the manufacturing process can be reduced.

After the step of forming the semiconductor region 9 shown in FIG. 7, a one-layer insulating film 10° connection hole 11 and wiring 12 are formed as shown in FIG.

The semiconductor integrated circuit device of this example is completed.

Although the invention made by the present inventor has been specifically explained above based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in one aspect of the present invention, the source region S and drain region of the MISFET may be formed only by the semiconductor region 9 without employing the LDD structure. In this case, in the source region S and drain region forming regions, the high melting point metal silicide film 6B is formed on the main surface of the semiconductor substrate l before the step of forming the semiconductor region 9.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly explained below.

In a semiconductor integrated circuit device equipped with an MIS FET, a high-melting point metal film and an oxidation-resistant metal film are formed on the gate electrode, the source region, and the drain region, and the high-melting point metal, oxidation-resistant metal, and silicon MIS
The resistance values of the gate electrode, source region, and drain region of the FET can be reduced.

Furthermore, since the oxidation-resistant metal film can prevent the high-melting point metal film from being oxidized, the process of removing the oxide can be eliminated and the number of manufacturing steps can be reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of a MISFET of a semiconductor integrated circuit device which is an embodiment of the present invention, and FIGS. 2 to 7 are MISFETs of a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of an S FET showing each manufacturing process. In the figure, 1... semiconductor substrate, 4... gate insulating film, 5
... Polycrystalline silicon film, 6A, 6B... High melting point metal silicide film, 6C... High melting point metal film, 6D... Oxidation-resistant metal film, 7, 9... Semiconductor region, G. . . . gate electrode, S . . . source region, D . . . drain region. l.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device equipped with a MISFET having a semiconductor region constituting a source region or a drain region and a gate electrode, the method comprising: A step of sequentially forming a high melting point metal film and a non-oxidizing metal film on the surface and on the gate electrode made of silicon, and combining the high melting point metal, the non-oxidizing metal and silicon to form the upper part of the gate electrode and the semiconductor region. or forming a high melting point metal silicide film on the main surface of the formation region. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the high melting point metal film is Mo, Ti, Ta, or W. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the non-oxidizing metal film is made of Pt, Ni, Pd, or Au.