JPS6218054A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6218054A JPS6218054A JP15590185A JP15590185A JPS6218054A JP S6218054 A JPS6218054 A JP S6218054A JP 15590185 A JP15590185 A JP 15590185A JP 15590185 A JP15590185 A JP 15590185A JP S6218054 A JPS6218054 A JP S6218054A
- Authority
- JP
- Japan
- Prior art keywords
- film
- opening
- inorganic
- plasma cvd
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は微細なスルホール加工方法に係り、特に、無機
物と有機物の積層膜に対するスルホール加工に好適な半
導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for processing fine through holes, and particularly to a method for manufacturing a semiconductor device suitable for processing through holes in a laminated film of inorganic and organic materials.
ＬＳＩの多層線の層間絶縁膜には無機膜或いは有機膜の
みが用いられていた。しかし、無機膜では平坦化が困難
であるという欠点がある。一方、有機膜では耐湿性に弱
いという欠点がある。これに対処する方法として有機膜
と無機膜の積層構造が提案されている。これらの層間絶
縁膜に微細な孔を開口した後、この開口−に金属を埋め
込み第一層の配線と導通をとる必要がある。この導通を
確保するための眉間絶縁膜に微細な孔を開口する技術に
ついて、眉間絶縁膜が無機膜の場合にば５ｏｌｉｄ ５
ｔａｔｅ ｔｅｃｈｎｏｌｏｇｙの’、８４Ｊｕｌｙの
Ｐ６６〜Ｐ７４ に於けるり、Ｈｃｈｏｅ、 Ｃ−Ｋ
ｎａｐｐ、 Ａ、 Ｊａ−ｃｕｂによる“生産用Ｒ，Ｉ
Ｅ、 誘電膜の選択エツチング′と題する論文に、有
機膜の場合にはＳｅｍ１−ｃｏｎｄｕｃｔｏｒ 工ｎｔ
ｅｒｎａｔｉｏｎａｌの’８５ ＴｅｂのＰ８２〜８５
に於けるＣ、 Ｈ，Ｔｉｎｇ 、 Ｓ、Ｙｅｉ、に、
Ｌ、 Ｌｉａｎｗによる” ３１ｏｐｅｄ Ｖｉａｓ
ｉｎ ｐｏｌｙｉｍｉｄｅｓ ｂｙＲＩＥ″と題する
論文に於いて論じられている。第２図は有機膜上に無機
膜の積層した眉間絶縁膜に対する微細な孔を開口する方
式の従来例を示す。シリコン基板２０上に酸化膜２０、
第１アルミニウム電極３０、有機膜４０、無機膜５０が
形成されている。さらにその上に微細な孔を開口するた
めの開ロア０のパターンのついたホトレジスト６０が形
成されている（ａ）。次に、ホトレジスト６０をマスク
として無機膜のみをエツチングするガスで無機膜５（ｌ
開ロア０を設ける（ｂ）。次に、エツチングガスを酸素
に変えて無機膜５０をマスクとしてエツチングし、有機
膜４０ｖｃ開ロア０を形成する（Ｃ）。Only inorganic or organic films have been used as interlayer insulating films for multilayer lines in LSIs. However, an inorganic film has the drawback that planarization is difficult. On the other hand, organic films have the disadvantage of poor moisture resistance. A laminated structure of an organic film and an inorganic film has been proposed as a method to deal with this problem. After opening fine holes in these interlayer insulating films, it is necessary to fill the openings with metal to establish conduction with the first layer wiring. Regarding the technology of opening fine holes in the glabellar insulating film to ensure this conduction, if the glabellar insulating film is an inorganic film, 5olid 5
tate technology', 84 July, P66-P74, Hchoe, C-K
“Production R,I” by Knapp, A. and Ja-cub.
E. In the paper entitled 'Selective etching of dielectric films', in the case of organic films, Sem1-conductor engineering
ernational'85 Teb P82-85
C, H, Ting, S, Yei, in
31oped Vias by L. Lianw
2 shows a conventional example of a method for opening fine holes in a glabella insulating film in which an inorganic film is laminated on an organic film. oxide film 20,
A first aluminum electrode 30, an organic film 40, and an inorganic film 50 are formed. Furthermore, a photoresist 60 with an open lower pattern 0 for opening fine holes is formed thereon (a). Next, using the photoresist 60 as a mask, the inorganic film 5 (l) is etched with a gas that etches only the inorganic film.
An open lower 0 is provided (b). Next, the etching gas is changed to oxygen and etching is performed using the inorganic film 50 as a mask to form the organic film 40vc open lower 0 (C).
この時、有機膜４０がアンダーエツチングされ、）無機
膜５０のひさしが生じるという欠点がある。At this time, there is a drawback that the organic film 40 is under-etched, resulting in an overhang of the inorganic film 50.
このようなひさしがあると次に第２層のアルミニウム配
線８０を形成した時、ひさしの部でアルミニウムの断線
９０が生じる（ψ。以上のように従来法で有機膜上に無
機膜を積層した膜に微細な孔を開口すると無機膜のオー
パーツ・ンクが生じるという欠点がある。If there is such an eaves, when the second layer of aluminum wiring 80 is formed, the aluminum wire 90 will be broken at the eaves (ψ). There is a drawback that when fine pores are opened in the membrane, opacity of the inorganic membrane occurs.
本発明は、上記した従来技術の欠点を解消する′ために
な嘔れたもので、その目的とするところは有機膜の上に
無機膜を積層した構造にオーバーハングのない微細な孔
を開口する方法を提供することにある。The present invention was made to solve the above-mentioned drawbacks of the prior art, and its purpose is to open fine holes without overhang in a structure in which an inorganic film is laminated on an organic film. The goal is to provide a way to do so.
本発明はまず、ホトレジストと無機膜の両者をエツチン
グするガスで無機膜を開口し、無機膜にテーパー状の開
口を形成した後、無機膜と有機膜の両者をエツチングす
るガスで有機膜を開口すると、無機膜に対して異方性の
あるガスであっても無機膜が後退するので、無機膜にオ
ーバー・・ングがなく、有機膜に微細な開口を形成する
ことができる。In the present invention, first, an inorganic film is opened with a gas that etches both the photoresist and the inorganic film, a tapered opening is formed in the inorganic film, and then an organic film is opened with a gas that etches both the inorganic film and the organic film. Then, even if the gas is anisotropic with respect to the inorganic film, the inorganic film recedes, so there is no overhang in the inorganic film, and fine openings can be formed in the organic film.
以下、本発明の一実施例を第１図によシ説明する。半導
体基板１０上に酸化膜２０、第１アルミニウム電極３０
、有機膜４０、具体的にはポリイミド膜、無機膜５０、
具体的ＶＣはプラズマ・ＣＶＤ酸化膜が形成されている
。さらにその上に微細な開口を形成するための開ロア０
のパターンのついたホトレジスト６０が形成されている
（ａ）。次に、ホトレジスト６０をマスクにしてＣＨＦ
３と０２の混合ガスで、プラズマＣＶＤ酸化膜５０ｖｃ
開ロア０を形成する。この際、ＣＨＦ、とＯ３の比率を
変えるとプラズマＣＶＤ酸化膜５０の開ロア０のテーパ
ー角度を変えることができる。ざらに、ホトレジスト６
０の膜厚とＣＨＦ、 と０２の比率を適当に制御する
とプラズマＣＶＤ酸化ｌｌ１Ｅ５０Ｖｃ開ロア０が形成
すれると同時にホトレジスト６０が除さしくｂ）の如く
なる。次に、プラズマＣＶＤ酸化膜５０をマスクとして
ＣＨＦ、とＯ６の混合ガスで、ポリイミド膜４０に開ロ
ア０を形成する（Ｃ）。ＣＨＦ、と０２の比率を変える
ことによシポリイミド膜４０の開ロア０のテーパー角を
変えられる。しかし、プラズマＣＶＤ酸化膜５０を最終
的には残す必要があるのでプラズマＣＶＤ酸化膜５０の
エツチング速度を余力大きくできない。従って、プラズ
マ“ＣＶＤ酸化膜５０を余り後退させることができない
のでポリイミド膜４０の開ロア０に大きなテーパーはつ
けにくい。これが、プラズマＣＶＤ酸化膜５０の開ロア
０にテーパーを形成する理由である。プラズマＣＶＤ酸
化膜５Ｇの開ロア０にテーパーを形成しておかないとプ
ラズマＣＶＤ酸化膜５０の開ロア０の後退けほとんど起
こらなく、プラズマＣＶＤ酸化膜５０のオーバーハング
が生じる。次に、第２アルミニウム８０を形成すると（
ｄ）の如く、第２アルミニウムの断線は生じない。本実
施例によれば、プラズマＣＶＤ酸（ｆ［ｏオーバーハン
グがないので、第２アルミニウムの断線が生じない。ざ
らに、プラズマＣＶＤ酸化膜の開口をホトレジストの除
去によりモニターできるので、プラズマＣＶＤ酸化膜の
エツチング不足やオーバーエツチングを防止することが
できる。An embodiment of the present invention will be explained below with reference to FIG. An oxide film 20 and a first aluminum electrode 30 are formed on the semiconductor substrate 10.
, an organic film 40, specifically a polyimide film, an inorganic film 50,
Specifically, the VC has a plasma/CVD oxide film formed thereon. Furthermore, the opening lower 0 to form a minute opening on top of it.
A photoresist 60 with a pattern is formed (a). Next, using the photoresist 60 as a mask, CHF
Plasma CVD oxide film 50vc with mixed gas of 3 and 02
An open lower 0 is formed. At this time, by changing the ratio of CHF and O3, the taper angle of the open lower part 0 of the plasma CVD oxide film 50 can be changed. Roughly, photoresist 6
By appropriately controlling the film thickness of 0 and CHF, and the ratio of 02 and 02, the plasma CVD oxidized 11E50Vc open lower 0 is formed and at the same time the photoresist 60 is removed, as shown in b). Next, using the plasma CVD oxide film 50 as a mask, an open lower portion 0 is formed in the polyimide film 40 using a mixed gas of CHF and O6 (C). By changing the ratio of CHF and 02, the taper angle of the open lower part 0 of the polyimide film 40 can be changed. However, since it is necessary to leave the plasma CVD oxide film 50 in the end, the etching rate of the plasma CVD oxide film 50 cannot be increased as much as possible. Therefore, since the plasma CVD oxide film 50 cannot be retreated very much, it is difficult to form a large taper in the open lower part 0 of the polyimide film 40. This is the reason why the open lower part 0 of the plasma CVD oxide film 50 is formed with a taper. Unless a taper is formed in the open lower part 0 of the plasma CVD oxide film 5G, the open lower part 0 of the plasma CVD oxide film 50 will hardly recede, and an overhang of the plasma CVD oxide film 50 will occur. When aluminum 80 is formed (
As in d), the second aluminum does not break. According to this embodiment, since there is no overhang in the plasma CVD oxide film (f[o), disconnection of the second aluminum does not occur. Insufficient etching and over-etching of the film can be prevented.
本発明によれば、有機膜上に無機膜を積層した膜の微細
な孔を無機膜のオーバーハングなしに開口できるので、
配線の断線が生じないという効果がある。According to the present invention, fine pores in a film in which an inorganic film is laminated on an organic film can be opened without overhanging the inorganic film.
This has the effect of preventing wire breakage.
第１図は本発明の一実施例の製造方法を説明する製作工
程図、第２図は従来の製造方法を説明する製作工程図で
ある。
１０・・・半導体基板、２０・・・酸化膜、３０・・・
第１アルミニウム、４０・・・有機膜、５０・・・無機
膜、６０・・・ホトレジスト、７０・・・開口。FIG. 1 is a manufacturing process diagram illustrating a manufacturing method according to an embodiment of the present invention, and FIG. 2 is a manufacturing process diagram illustrating a conventional manufacturing method. 10... Semiconductor substrate, 20... Oxide film, 30...
First aluminum, 40... Organic film, 50... Inorganic film, 60... Photoresist, 70... Opening.
Claims (1)
る方法に於いて、ホトレジストと無機膜の両者をエッチ
ングするガスでドライエッチングし、無機膜にテーパー
状の孔を開口する第１の工程と無機膜と有機膜の両者を
エッチングするガスでドライエッチングし、有機膜に開
口する第２の工程とからなることを特徴とする半導体装
置の製造方法。1. In the method of forming fine holes in a film in which an inorganic film is laminated on an organic film, the first step is to perform dry etching with a gas that etches both the photoresist and the inorganic film to open tapered holes in the inorganic film. 1. A method for manufacturing a semiconductor device, comprising the steps of step 1 and dry etching using a gas that etches both an inorganic film and an organic film to form an opening in the organic film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15590185A JPS6218054A (en) | 1985-07-17 | 1985-07-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15590185A JPS6218054A (en) | 1985-07-17 | 1985-07-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6218054A true JPS6218054A (en) | 1987-01-27 |
Family
ID=15615988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15590185A Pending JPS6218054A (en) | 1985-07-17 | 1985-07-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6218054A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63104338A (en) * | 1986-10-08 | 1988-05-09 | インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション | Method of forming aperture with inclination in composite insulating layer |
| JPH0221640A (en) * | 1987-06-12 | 1990-01-24 | Yokogawa Hewlett Packard Ltd | Semiconductor device |
| EP0525942A2 (en) * | 1991-05-31 | 1993-02-03 | AT&T Corp. | Integrated circuit fabrication process using a bilayer resist |
| US5212114A (en) * | 1989-09-08 | 1993-05-18 | Siemens Aktiengesellschaft | Process for global planarizing of surfaces for integrated semiconductor circuits |
-
1985
- 1985-07-17 JP JP15590185A patent/JPS6218054A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63104338A (en) * | 1986-10-08 | 1988-05-09 | インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション | Method of forming aperture with inclination in composite insulating layer |
| JPH0221640A (en) * | 1987-06-12 | 1990-01-24 | Yokogawa Hewlett Packard Ltd | Semiconductor device |
| US5212114A (en) * | 1989-09-08 | 1993-05-18 | Siemens Aktiengesellschaft | Process for global planarizing of surfaces for integrated semiconductor circuits |
| EP0525942A2 (en) * | 1991-05-31 | 1993-02-03 | AT&T Corp. | Integrated circuit fabrication process using a bilayer resist |
| EP0525942A3 (en) * | 1991-05-31 | 1994-03-02 | American Telephone & Telegraph |
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