JPH11145278A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming fine viaholes of neat shape in an org. layer insulation film. SOLUTION: This manufacturing method comprises the steps of forming a metal wiring layer 102 on a semiconductor substrate 101, forming an org. layer insulation film 103, forming a plasma nitride film 105, forming a photoresist pattern 106 aligned with lines of a metal wiring 10 using lithography, anisotropically etching a plasma oxide film 105 selectively to the lower plasma nitride layer 104 with the resist pattern 106 used as a mask, anisotropically etching after stripping the resist pattern, the lower plasma nitride film 104 with the plasma oxide film 105 used as a mask, and anisotropically etching the org. layer insulation film 103, using the plasma oxide film 105 and the nitride film 104 as a mask, thereby forming viaholes 107 communicating with the metal wiring layer 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as an LSI device having a structure in which a via hole communicating with a metal wiring layer is formed in an organic interlayer film as an interlayer insulating film between metal wiring layers. About the method.

[0002]

2. Description of the Related Art Conventionally, in an LSI device, a metal wiring layer is formed on a semiconductor substrate, and an interlayer insulating film between metal wiring layers is formed over the entire surface of the semiconductor substrate on which the metal wiring layer is formed. The structure is such that a via hole communicating with the metal wiring layer is formed in the film. As an interlayer insulating film between such metal wiring layers, a silicon oxide film formed by a plasma CVD method is mainly used.

However, when a silicon oxide film is used for such an interlayer insulating film, it is difficult to reduce the capacitance between the metal wiring layers by miniaturizing the pitch between the metal wiring layers. A situation occurred in which the speed could not be increased.

[0004] In order to cope with such a situation, various low inductive conductivity films have been studied. Such a low induction power film can be roughly divided into an organic film and an inorganic film.
Of the organic film and the inorganic film, the inorganic film can be formed in the same process as the conventional silicon oxide film,
There is a problem that an effective low induction power cannot be obtained. On the other hand, the organic film has an advantage that an effective low inductive power can be obtained as compared with the inorganic film. In recent years, the organic film has been adopted as the interlayer insulating film.

Next, a method of manufacturing a conventional LSI device using an organic interlayer film as an organic film as the interlayer insulating film will be described. FIG. 5 is a process sectional view briefly showing a conventional LSI device manufacturing method. The method of manufacturing an LSI device shown in FIG. 5 is a method of forming a via hole communicating with a metal wiring layer in an organic interlayer film.

First, as shown in FIG. 5A, a metal wiring layer 302 is formed on a semiconductor substrate 301 (metal wiring layer forming step). Next, as shown in FIG. 5B, an organic interlayer film 303 is formed as an interlayer insulating film of the metal wiring layer 302 over the entire surface of the semiconductor substrate 301 on which the metal wiring layer 302 is formed (organic interlayer film forming step). A resist pattern 30 for forming a via hole aligned with the metal wiring layer 302 on the organic interlayer film 303.
6 is formed (lithography step).

Next, using the resist pattern 306 as a mask, as shown in FIG.
Is anisotropically etched by dry etching (organic interlayer film etching step). Next, using the organic interlayer film 303 as a mask, an oxygen plasma process or a wet stripping process is performed to remove the resist pattern 306 as shown in FIG. A via hole 307 communicating with the wiring layer 302 can be formed (resist pattern stripping step).

FIG. 6 shows another manufacturing method. Next, another conventional manufacturing method will be described with reference to FIG.

First, as shown in FIG. 6A, a metal wiring layer 402 is formed on a semiconductor substrate 401 (metal wiring layer forming step). Next, as shown in FIG. 6B, an organic interlayer film 403 is formed as an interlayer insulating film of the metal wiring device 402 over the entire surface of the semiconductor substrate 401 on which the metal wiring layer 402 is formed (organic interlayer film forming step).

A plasma oxide film 405 is formed on the organic interlayer film 403 (plasma oxide film forming step). A resist pattern 406 for forming a via hole aligned with the metal wiring layer 402 is formed on the plasma oxide film 405 (lithography step).

Next, using the resist pattern 406 as a mask, as shown in FIG.
05 is anisotropically etched by dry etching (plasma oxide film etching step).

Further, an oxygen plasma treatment or a wet stripping treatment is performed using the plasma oxide film 405 as a mask, thereby forming a resist pattern 4 as shown in FIG.
06 is stripped (resist pattern stripping step). After the resist pattern removing step, the plasma oxide film 40 is removed.
5 is used as a mask, the organic interlayer film 403 is anisotropically etched.
Can be formed (organic interlayer film etching step).

[0013]

However, according to the conventional method of manufacturing a semiconductor device shown in FIG.
The resist pattern 306 is stripped in the resist pattern stripping step as shown in FIG. 5, but the organic interlayer film 303 may be etched by the oxygen plasma processing or the wet stripping processing in the resist pattern stripping step. If the organic interlayer film 303 is exposed during the pattern peeling step, the exposed portion of the organic interlayer film 303 is side-etched, so that the diameter of the via hole 307 formed in the organic interlayer film 303 is reduced. As a result, there is a problem that it is impossible to form a fine via hole as the resist pattern 306.

According to the conventional method for manufacturing a semiconductor device shown in FIG. 6, the organic interlayer film 403 is side-etched in the resist pattern stripping step as shown in FIG. There is a problem that the plasma oxide film 405 overhangs and the upper metal wiring layer 402 is disconnected.

The present invention has been made in view of the above problems, and an object of the present invention is to stably form a fine via hole communicating with a metal wiring layer as in a resist pattern in an organic interlayer film. It is to provide a method for manufacturing a semiconductor device which can be formed.

[0016]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a metal wiring layer on a semiconductor substrate; An organic interlayer film forming step of forming an organic interlayer film over the entire surface of the semiconductor substrate on which the wiring layer is formed; a plasma nitride film forming step of forming a plasma nitride film on the organic interlayer film; A plasma oxide film forming step of forming a plasma oxide film, a lithography step of forming a resist pattern on the plasma oxide film for forming a via hole aligned with the metal wiring layer, and using the resist pattern as a mask. A plasma oxide film etching step of selectively anisotropically etching the plasma oxide film with respect to a plasma nitride film. A resist pattern removing step of removing the resist pattern using the plasma oxide film as a mask, and a plasma nitride film etching step of anisotropically etching the plasma nitride film using the plasma oxide film as a mask after removing the resist pattern; An organic interlayer film etching step of anisotropically etching the organic interlayer film using the plasma oxide film and the plasma nitride film as a mask to form a via hole communicating with the metal wiring layer.

The organic interlayer film corresponds to an interlayer insulating film between the metal wiring layers. Further, the plasma nitride film refers to an S film formed by a plasma CVD method.
It corresponds to an i3 N4 or SiON film. Also,
The plasma oxide film and the plasma nitride film formed on the organic interlayer film have an etching selectivity with each other.

In the lithography step, for example, KrF
This corresponds to a step of forming a resist pattern on a plasma oxide film using excimer lithography.
The plasma oxide film etching step is performed in a C4F8 / CO / Ar / O2 mixed gas as an etching gas, for example, using a parallel plate narrow gap RIE apparatus. Further, the resist pattern peeling step is performed by a plasma oxygen treatment or a wet peeling treatment.

In the plasma nitride film etching step, HB as an etching gas is
It is performed in r gas. The organic interlayer film etching step is performed in a Cl2 / O2 mixed gas as an etching gas using, for example, a low-pressure, high-density etching apparatus equipped with an ECR plasma source.

Therefore, according to the method of manufacturing a semiconductor device according to the first aspect of the present invention, a plasma nitride film and a plasma oxide film having an etching selectivity are sequentially laminated on an organic interlayer film. After forming a resist pattern on the film, the plasma oxide film is selectively etched with respect to the plasma nitride film using the resist pattern as a mask, and further, the organic interlayer film is not exposed by the mask of the plasma nitride film. After performing the resist pattern stripping step in this state, the plasma nitride film is anisotropically etched, and the organic interlayer film etching step of forming a via hole in the organic interlayer film is performed.
A mask for the organic interlayer film etching step can be formed without exposing the organic interlayer film, and further, by forming the mask, fine via holes can be stably formed in the organic interlayer film.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a metal wiring layer on a semiconductor substrate; An organic interlayer film forming step of forming an organic interlayer film; a plasma oxide film forming step of forming a plasma oxide film on the organic interlayer film; and selectively forming the plasma oxide film on the plasma oxide film. A metal layer forming step of forming an etchable metal layer, a lithography step of forming a resist pattern on the metal layer for forming a via hole aligned with the metal wiring layer, and using the resist pattern as a mask. A metal layer etching step of selectively anisotropically etching the metal layer with respect to a plasma oxide film; A resist pattern stripping step of stripping a resist pattern using the layer as a mask, a plasma oxide film etching step of anisotropically etching a plasma oxide film using the metal layer as a mask after stripping the resist pattern; An anisotropic etching of the organic interlayer film using the oxide film as a mask, and an organic interlayer film etching step of forming a via hole communicating with the metal wiring layer.

The organic interlayer film corresponds to an interlayer insulating film between the metal wiring layers. The metal layer may be any metal film as long as it can be selectively etched with respect to the plasma oxide film and has good compatibility with the metal buried in the via hole.
It is composed of Cu, Ti, TiN, W or a laminated film of these. The plasma oxide film and the metal layer formed on the organic interlayer film can have an etching selectivity with each other.

In the lithography step, for example, KrF
This corresponds to a step of forming a resist pattern on a metal layer using excimer lithography. Also,
The metal layer etching step is performed in a Cl2 gas as an etching gas using, for example, a low-pressure, high-density etching apparatus equipped with an ECR plasma source as an etching apparatus.

The resist pattern peeling step is performed by a plasma oxygen treatment or a wet peeling treatment. The plasma oxide film etching step is performed in a C4F8 / CO / Ar / O2 mixed gas as an etching gas, for example, using a parallel plate narrow gap RIE apparatus. The organic interlayer film etching step is performed in a Cl2 / O2 mixed gas as an etching gas using, for example, a low-pressure, high-density etching apparatus equipped with an ECR plasma source.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, a plasma oxide film and a metal layer having an etching selectivity are sequentially laminated on an organic interlayer film. After the formation of a resist pattern, the metal layer is selectively etched with respect to the plasma oxide film using the resist pattern as a mask. After performing the pattern stripping step, the plasma oxide film is anisotropically etched, and the organic interlayer film etching step of forming a via hole in the organic interlayer film is performed, so that the organic interlayer film is not exposed. A mask for the organic interlayer film etching step can be formed. Fine via holes can be stably formed.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, since a plasma nitride film having a high dielectric constant is not used as an etching stopper layer at the time of forming a mask pattern, the capacitance between the upper and lower wiring layers is reduced. Can be lowered.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 and 2 are process sectional views briefly showing a method of manufacturing a semiconductor device according to a first embodiment. FIG. 1A shows a metal wiring layer forming step, FIG. 1B shows an organic interlayer film forming step, a plasma nitride film forming step, a plasma oxide film forming step, and a lithography step.
FIG. 1C shows a plasma oxide film etching step, and FIG.
2A is a sectional view of a resist pattern removing step, FIG. 2B is a sectional view of a plasma nitride film etching step, and FIG. 2C is a sectional view of an organic interlayer film etching step.

First, as shown in FIG. 1A, a metal wiring layer 102 is formed on a semiconductor substrate 101 (metal wiring layer forming step). Next, as shown in FIG. 1B, the metal wiring layer 102 is formed to a thickness of, for example, 1000 nm over the entire surface of the semiconductor substrate 101 on which the metal wiring layer 102 is formed.
An organic interlayer film 103 is formed as an interlayer insulating film therebetween (organic interlayer film forming step).

On the organic interlayer film 103, for example, 50 n
A plasma nitride film 104 is formed with a thickness of m (plasma oxide film forming step). Further, the plasma nitride film 104
A plasma oxide film 105 having a thickness of, for example, 150 nm
Is formed (plasma oxide film forming step). The plasma nitride film 104 and the plasma oxide film 105 can have an etching selectivity with each other.

Subsequently, on this plasma oxide film 105,
A resist pattern 106 for forming a via hole aligned with the metal wiring layer 102 is formed (lithography step). Note that this resist pattern 106
Has an opening diameter of, for example, about 0.2 μm for forming a via hole by using KrF excimer lithography.

Next, using the resist pattern 106 as a mask, as shown in FIG. 1C, the plasma oxide film 105 is selectively anisotropically etched with respect to the plasma nitride film 104 by dry etching. (Plasma oxide film etching step). In this plasma oxide film etching step, a parallel plate type narrow gallop RIE apparatus was used, and C4 F8 / CO /
It is performed in an Ar / O2 mixed gas.

Next, as shown in FIG. 2A, the resist pattern 106 is subjected to an oxygen plasma treatment to remove the resist pattern 106 (resist pattern removing step). In this resist pattern stripping step, the plasma nitride film 104 masks the organic interlayer film 103 and the organic interlayer film 103 is not exposed, so that the organic interlayer film 103 is not etched. .

Further, after the resist pattern stripping step, the plasma oxide film 105 is used as a mask to
As shown in (b), the plasma nitride film 104 is anisotropically etched (plasma nitride film etching step). In this plasma nitride film etching step, an RIE apparatus was used as an etching apparatus, and HBr was used as an etching gas.
It shall be performed in gas.

Next, using the plasma nitride film 104 and the plasma oxide film 105 as masks, as shown in FIG.
The organic interlayer film 103 is anisotropically etched to form a via hole 107 communicating with the metal wiring layer 102 (organic interlayer film etching step). This organic interlayer film etching step is performed in a Cl2 / O2 mixed gas as an etching gas using a low pressure, high density etching apparatus equipped with an ECR plasma source as an etching apparatus.

According to the above-described first embodiment, the plasma nitride film 104 and the plasma oxide film 105 having an etching selectivity with respect to each other are sequentially laminated on the organic interlayer film 103. After forming the resist pattern 106, the plasma oxide film 105 is formed using the resist pattern 106 as a mask.
4 and a resist pattern stripping step is performed in a state where the organic interlayer film 103 is not exposed with the mask of the plasma nitride film 104, and then the plasma nitride film 104 is anisotropically etched. And
Since an organic interlayer film etching step of forming a via hole 107 in the organic interlayer film 103 is performed, a mask for the organic interlayer film etching step can be formed without exposing the organic interlayer film 103, Furthermore, by forming the mask, fine via holes 107 can be stably formed in the organic interlayer film 103.

(Embodiment 2) Next, a method of manufacturing the semiconductor device according to the second embodiment will be described. 3 and 4 are process cross-sectional views briefly showing the method of manufacturing the semiconductor device according to the second embodiment. FIG. 3A is a step of forming a metal wiring layer, and FIG. 3B is a step of forming an organic interlayer film. FIG. 3 (c) is a metal layer forming step, FIG. 4 (a) is a resist pattern stripping step, FIG. 4 (b) is a plasma oxide film etching step, FIG. FIG. 4 (c) is a process sectional view of an organic interlayer film etching step.

First, as shown in FIG. 3A, a metal wiring layer 202 is formed on a semiconductor substrate 201 (metal wiring layer forming step). Next, as shown in FIG. 2B, the metal wiring layer 202 is formed to a thickness of, for example, 1000 nm over the entire surface of the semiconductor substrate 201 on which the metal wiring layer 202 is formed.
An organic interlayer film 203 is formed as an interlayer insulating film therebetween (organic interlayer film forming step).

On this organic interlayer film 203, for example, 50 n
A plasma oxide film 208 is formed with a thickness of m (plasma oxide film forming step). Further, the plasma oxide film 208
A titanium nitride film 209 having a thickness of, for example, 50 nm is formed thereon (a titanium nitride film forming step). This titanium nitride film forming step corresponds to a metal layer forming step of forming a titanium nitride film 209 by a sputtering method. The plasma oxide film 208 and the titanium nitride film 209 are
The etching selectivity can be obtained with each other.

Subsequently, a resist pattern 206 for forming a via hole aligned with the metal wiring layer 202 is formed on the titanium nitride film 209 (lithography step). Note that this resist pattern 206
Has an opening diameter of, for example, about 0.2 μm for forming a via hole by using KrF excimer lithography.

Then, using the resist pattern 206 as a mask, as shown in FIG. 3C, the titanium nitride film 209 is etched by dry etching to form a plasma oxide film 208.
Is selectively anisotropically etched (titanium nitride film etching step). This titanium nitride film etching step is performed in a Cl2 gas as an etching gas using a low-pressure, high-density etching apparatus equipped with an ECR plasma source as an etching apparatus.

Next, as shown in FIG. 4A, the resist pattern 206 is subjected to an oxygen plasma treatment to peel off the resist pattern 206 (resist pattern peeling step). In the resist pattern stripping step, the plasma oxide film 208 masks the organic interlayer film 203 and the organic interlayer film 203 is not exposed, so that the organic interlayer film 203 is not etched. .

Further, after this resist pattern stripping step, using the titanium nitride film 209 and the organic interlayer film 203 as a mask, as shown in FIG.
08 is anisotropically etched (plasma oxide film etching step). In addition, this plasma oxide film etching step
Parallel plate narrow gap RIE as etching equipment
C4 F8 / CO as etching gas using the apparatus
/ Ar / O2 mixed gas.

Next, using the titanium nitride film 209 and the plasma oxide film 208 as a mask, as shown in FIG. 4C, the organic interlayer film 203 is anisotropically etched to form a via hole 207 communicating with the metal wiring layer 202. Is formed (an organic interlayer film etching step). This organic interlayer film etching step is performed in a Cl2 / O2 mixed gas as an etching gas using a low-pressure, high-density etching device equipped with an ECR plasma source as an etching device.

According to the second embodiment, a plasma oxide film 208 and a titanium nitride film 209 having an etching selectivity are sequentially laminated on the organic interlayer film 203,
After a resist pattern 206 is formed on the titanium nitride film 209, the titanium nitride film 209 is selectively etched with respect to the plasma oxide film 208 using the resist pattern 206 as a mask. After performing a resist pattern stripping step in a state where the organic interlayer film 203 is not exposed in step (a), the plasma oxide film 208 is anisotropically etched, and an organic interlayer film etching step of forming a via hole 207 in the organic interlayer film 203 is performed. Since the process is executed, the organic interlayer film 20 is formed.
A mask for the organic interlayer film etching step can be formed without exposing 3, and fine via holes 207 can be stably formed in the organic interlayer film 203 by this mask formation.

Further, according to the second embodiment, since a plasma nitride film having a high dielectric constant is not used as an etching stopper layer when forming a mask pattern, the capacitance between the upper and lower wiring layers can be reduced.

In the second embodiment, the titanium nitride film 209 is employed as a metal layer serving as a mask when forming the via hole 207 in the organic interlayer film etching step. Any metal film may be used as long as it can be etched and has good compatibility with the metal to be embedded in the via hole 207. For example, AlCu, Ti, TiN, W, or a laminated film of these materials may be used. Is also good.

[0048]

According to the method of manufacturing a semiconductor device according to the present invention having the above-described structure, a mask forming step for etching an organic interlayer film can be performed without exposing the organic interlayer film. Fine via holes can be stably formed in the film.

According to the method of manufacturing a semiconductor device according to the present invention, not only the effects described in claim 1 above, but also of course,
Since a plasma nitride film having a high dielectric constant is not used as an etching stopper layer when forming a mask pattern, the capacitance between the upper and lower wiring layers can be reduced.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. a) metal wiring layer forming step, b) organic interlayer film forming step, plasma nitride film forming step, plasma oxide film forming step and lithography step c) plasma oxide film etching step

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in the first embodiment of the present invention. a) resist pattern stripping step b) plasma nitride film etching step c) organic interlayer film etching step

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention. a) metal wiring layer forming step, b) organic interlayer film forming step, plasma oxide film forming step, metal layer forming step and lithography step c) metal layer forming step

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention. a) resist pattern stripping step b) plasma oxide film etching step c) organic interlayer film etching step

FIG. 5 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device. a) metal wiring layer forming step b) organic interlayer film forming step and lithography step c) organic interlayer film etching step d) resist pattern stripping step

FIG. 6 is a process sectional view showing a conventional method for manufacturing a semiconductor device. a) metal wiring layer forming step b) organic interlayer film forming step, plasma oxide film forming step, lithography step and plasma oxide film etching step c) resist pattern stripping step and organic interlayer film etching step

[Explanation of symbols]

 101, 201 Semiconductor substrate 102, 202 Metal wiring layer 103, 203 Organic interlayer film 104 Plasma nitride film 105, 208 Plasma oxide film 106, 206 Resist pattern 107, 207 Via hole 209 Titanium nitride film (metal layer)

Claims (4)

[Claims] A metal wiring layer forming step of forming a metal wiring layer on a semiconductor substrate; an organic interlayer film forming step of forming an organic interlayer film over the entire surface of the semiconductor substrate on which the metal wiring layer is formed; A plasma nitride film forming step of forming a plasma nitride film on the interlayer film; a plasma oxide film forming step of forming a plasma oxide film on the plasma nitride film; A lithography step of forming a resist pattern for forming aligned via holes, and a plasma oxide film etching step of selectively anisotropically etching the plasma oxide film with respect to a plasma nitride film using the resist pattern as a mask And a resist pattern removing step of removing the resist pattern using the plasma oxide film as a mask. After the resist pattern is stripped, a plasma nitride film etching step of anisotropically etching the plasma nitride film using the plasma oxide film as a mask, and an anisotropic organic interlayer film using the plasma oxide film and the plasma nitride film as a mask An organic interlayer film etching step of forming a via hole communicating with the metal wiring layer by reactive etching. 2. The plasma nitride film formed in the plasma nitride film forming step is formed of Si3 formed by a plasma CVD method.
2. The method according to claim 1, wherein the semiconductor device is an N4 or SiON film. A metal wiring layer forming step of forming a metal wiring layer on the semiconductor substrate; an organic interlayer film forming step of forming an organic interlayer film over the entire surface of the semiconductor substrate on which the metal wiring layer is formed; A plasma oxide film forming step of forming a plasma oxide film on the interlayer film; a metal layer forming step of forming a metal layer selectively etchable on the plasma oxide film on the plasma oxide film; A lithography step of forming a resist pattern for forming a via hole aligned with the metal wiring layer on the metal layer; and using the resist pattern as a mask, selectively forming the metal layer with respect to a plasma oxide film. A metal layer etching step for anisotropic etching, and a resist for removing the resist pattern using the metal layer as a mask A pattern stripping step, after the resist pattern stripping, a plasma oxide film etching step of anisotropically etching the plasma oxide film using the metal layer as a mask, and a different organic interlayer film using the metal layer and the plasma oxide film as a mask. An organic interlayer film etching step of forming a via hole communicating with the metal wiring layer by anisotropic etching. 4. The method according to claim 1, wherein the metal layer in the metal layer forming step includes A
4. The method of manufacturing a semiconductor device according to claim 3, wherein said method is made of lCu, Ti, TiN, W or a laminated film thereof.