JPH10154752A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control damages to a shallow connection hole at etching, for improved reliability in a semiconductor device. SOLUTION: Relating to the method, an inter-layer insulation film 104 is formed on a semiconductor substrate 101, and connection holes 105a and 105b of different depth which are electrically connected to a metal wiring layer 108 formed on the inter-layer insulation film 104 are simultaneously formed on the inter-layer insulation film 104 by dry-etching. The diameter of a shallow connection hole 105a is that of connection hole which causes an etching stop, with the diameter of deep connection hole 105b at least larger than that of the shallow connection hole while being the diameter of connection hole not causing etching stop, etching is performed number etching stop condition to form connection holes 105a and 105b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a connection hole.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices are generally manufactured as follows. First, as shown in FIG. 6, a gate electrode 203 is provided on an active region of a silicon substrate 201 and on an element isolation layer 202 formed by a LOCOS oxidation method, respectively. After forming the region, the interlayer insulating film 2
04 is provided. In order to provide a connection hole for connecting to a wiring provided on the interlayer insulating film 204, the connection holes 205a and 205b are formed using a photoresist mask 206.
Is formed by dry etching or the like.

A substrate 201 and an element isolation layer 202
Since there is a step, the connection hole 205a provided on the gate electrode 203 provided on the element isolation layer 202 and the connection hole 205b provided on the substrate 201 are different in the depth of the connection hole.

Conventionally, fine connection holes 205a having different depths have been used.
When the holes 205b are formed at the same time,
The etching is performed according to the depth 207b of b. For this reason, as shown in FIG. 6, in the connection hole 205a having a shallow depth 207a, even after the underlying gate electrode layer 203 is exposed, the connection hole 205a is exposed to extra plasma by a difference from the deep connection hole 205b, thereby causing damage due to charging and etchant. Ion irradiation damage is caused.

In particular, in the interlayer insulating film 204 planarized by, for example, CMP (chemical mechanical polishing), the depth 207a of the shallow connection hole 205a and the depth 2 of the deep connection hole 205b
Since the difference of 07b is twice or more, the influence of the damage to the base is serious, which also causes the reliability of the semiconductor device to deteriorate.

As shown in FIG. 7, when the etch rate selectivity between the underlying gate electrode film 203 and the insulating film 204 at the time of etching the connection hole is small, the gate electrode film 203 below the shallow connection hole 205a is not gated at the time of etching. The electrode 203 is scraped, and if it is severe, it penetrates and becomes defective. This effect becomes more remarkable as the thickness of the underlying gate electrode 203 becomes thinner with miniaturization.

In order to eliminate the above-mentioned problem of over-etching when connecting holes are simultaneously formed in portions having different thicknesses of the interlayer insulating film, the first interlayer insulating film formed on the silicon semiconductor substrate has It has been proposed to use an insulating film (silicon nitride film) having different etching selectivity as an etching stopper. For example, Japanese Patent Application Laid-Open
JP-A-13434, JP-A-3-78227, JP-A-3-187220, JP-A-5-243520, JP-A-6-151352, JP-A-7-22
Various methods have been proposed, such as Japanese Patent No. 1194.

[0008]

However, as described above, when films having different etching rates are sandwiched between interlayer insulating films and used as an etching stopper, the process of forming the interlayer insulating film becomes complicated, and the etching process becomes difficult. The process also has the disadvantage that several steps of processing are required.

It is an object of the present invention to control damage to a shallow connection hole due to the above-described etching, and to improve the reliability of a semiconductor device.

[0010]

According to the present invention, an interlayer insulating film is formed on a semiconductor substrate, and connection holes having different depths for electrically connecting to a metal wiring layer formed on the interlayer insulating film are formed. In a method of manufacturing a semiconductor device in which an interlayer insulating film is simultaneously formed by dry etching, a diameter of a shallow connection hole is defined as a diameter of a connection hole causing an etching top, and a diameter of a deep connection hole is at least larger than a diameter of the shallow connection hole. The diameter of the connection hole does not cause an etching stop, and etching is performed under the etching stop condition to form a connection hole.

The diameter of the deep connection hole is at least 0.05 μm larger than the diameter of the shallow connection hole.

Further, according to the present invention, in the etching stop condition, the etching is stopped at a desired depth smaller than the diameter of a certain connection hole, and the etching is advanced at a diameter of the connection hole larger than a certain connection hole. Control to continue.

Further, the etching stop condition is as follows:
In a shallow connection hole accompanied by an etching stop, the etching is controlled so as to stop at a depth where the underlying conductive layer is not exposed.

Further, according to the present invention, in the case of a shallow connection hole, after the connection hole is etched under the condition that the etching stops at a depth where the underlying conductive layer is not exposed, the connection hole is formed under the condition that the etching stop does not occur at each connection hole diameter. The remaining insulating film may be controlled so as to be etched until the underlying conductive layer is exposed.

The etching in the present invention is characterized in that the etching stop condition is controlled by the mixing ratio of the kind of etching gas used.

According to the present invention, the etching gas species is C
It is preferable to use a gas containing an F-based gas.

In the present invention, it is preferable to use, as the etching gas species, at least a gas species which reacts with a substance containing carbon deposited on the semiconductor device and generates a reaction product having a high vapor pressure.

Further, in the present invention, it is preferable to use oxygen as the etching gas species.

Further, in the etching according to the present invention, etching stop conditions can be controlled by operating pressure.

Further, according to the present invention, a first insulating film having a generally low etching rate is deposited on a semiconductor substrate under the same etching conditions, and a relatively high etching rate is formed on the first insulating film. It is preferable that the second insulating film be deposited.

The first insulating film is a silicon nitride film,
Preferably, the insulating film is made of a silicon oxide film.

According to the above configuration, since the diameter of the deep connection hole is larger than the diameter of the shallow connection hole, if the distance between the connection hole and the gate electrode is reduced due to miniaturization, the gap between the gate electrode and the gate electrode is reduced due to misalignment during photolithography. A short circuit of the connection hole may occur.

Therefore, by depositing an etching stopper on the first layer of the interlayer insulating film, a short circuit between the fine connection hole and the gate electrode during etching can be prevented.

As described above, the present invention can solve the problem of over-etching by controlling only the etching conditions, so that the cost and the manufacturing period can be reduced.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention.

As shown in FIG. 1, on a semiconductor substrate 101,
Silicon acid of 450 nm thickness by the well-known LOCOS method
An element isolation layer 102 made of an oxide film is formed, and has a thickness of 8 nm.
Silicon oxide film and 300nm thick polysilicon
Of the semiconductor substrate 101
Provided on the active region and the element isolation layer 102, respectively.
You. TEOS (tetraethyl) is formed on the gate electrode 103.
Orthosilicate), O _ThreeBy CVD method using
800 nm thick composed of a laminated film of BPSG and NSG film
An interlayer insulating film 104 is formed. This interlayer insulating film 104
Are flattened by reflow of heat treatment.

Since the interlayer insulating film 104 is flattened, the gate electrode 10 provided on the element isolation layer 102
3, the depth 107a of the shallow connection hole 105a is smaller than the depth 107b of the deep connection hole 105b on the semiconductor substrate 101.

As shown in FIG. 1C, the interlayer insulating film 10
A photoresist mask 106 is provided on the interlayer insulating film 104 and electrically connected to the interlayer insulating film 104 by dry etching in order to electrically connect the metal wiring 108 provided on the substrate 4 to the gate electrode 103 and the semiconductor substrate 101. Holes 105a and 105b need to be formed.

A fine connection hole 105a is formed simultaneously on the gate electrode 103 provided on the element isolation layer 102 of the interlayer insulating film 104 and a fine connection hole 105b on the semiconductor substrate 101 by dry etching. At this time, the gate electrode 1
The fine connection hole 105a on the semiconductor substrate 101 has a fine connection hole diameter D1 smaller than the diameter D of the connection hole where the etching stop occurs, as shown in FIGS.
5b is a fine connection hole diameter D2 larger than the connection hole diameter D at which the etching stop occurs. The etching stop does not occur in the connection hole 105b having the connection diameter D2.

For example, the diameter D1 of the connection hole 105a is set to 0.
The diameter D2 of the connection hole 105b is set to 0.40 μm. Here, as shown in FIG. 3, the etching stop depth ED can be controlled to an arbitrary depth by controlling the oxygen flow rate or the operating pressure under the etching conditions. For example,
Condition A for the etching stop depth of A, condition B for the etching stop depth of B, condition C for the etching stop depth of C, and so on.
Etching may be performed under each condition.

For example, as shown in FIG. 1A, the etching stop depth ED is equal to the depth 10 of the fine connection hole 105a.
5b, the interlayer insulating film 104 in the deep fine connection hole 105b is completely etched, and the semiconductor substrate 101
Etching is completed when is exposed.

As shown in FIG. 1B, the etching stop depth ED is equal to the depth 107 of the fine connection hole 105a.
If it is shallower than a, as the first step of etching,
Etching is performed until the interlayer insulating film 104 in the deep fine connection hole 105b is completely etched and the semiconductor substrate 101 is exposed.
The etching condition is switched to an etching condition as shown in FIG. 4, which does not cause the etching stop, and the interlayer insulating film 104 remaining in the fine connection hole 105a is etched.

Here, as an example of the etching that causes an etching stop, for example, magnetron RIE (reactive ion etching) using a mixed gas system of C ₄ F ₈ , CO, Ar, and O ₂ as a reactive gas. , O ₂ flow rate, and decreasing the O ₂ flow rate causes an etching stop characteristic. Also, the etching stop characteristic can be generated by increasing the operation pressure.

As one specific example, the operating pressure is 40 mTo
rr, RF power 1500 W, C ₄ F ₈ 25 sccm,
Etching stop occurs when CO is 25 sccm, Ar is 100 sccm, and O ₂ flow rate is 16 sccm or less.

Further, the RF power is 1500 W and C ₄ F ₈ is 1
8 sccm, CO 300 sccm, Ar 400 sc
Etching stop occurs when the operating pressure is 40 mTorr or more at 1 cm / cm ₂ and 1 sccm.

Referring to FIG. 5, a second embodiment of the present invention will be described.

As in the case of the first embodiment, the semiconductor substrate 10
An element isolation layer 102 made of a silicon oxide film having a thickness of 450 nm is formed on the substrate 1, and a gate oxide film made of a silicon oxide film having a thickness of 8 nm is formed on the active region of the substrate 101 and the element isolation layer 102. A gate electrode 103 having a laminated structure made of polysilicon is formed.

Next, a silicon nitride film 109 having a thickness of 100 nm is deposited by the CVD method, a BPSG film 110 formed by the CVD method is formed, and the BPSG film 110 is flattened by a reflow of heat treatment, and an interlayer insulating film 104 having a thickness of 700 nm is formed. Form. At this time, since the interlayer insulating film 104 is flattened, the thickness (107a) on the gate electrode 103 on the interlayer insulating layer 102 becomes smaller than the thickness (107a) on the semiconductor substrate 101.
b) Thinner.

As in the first embodiment, the metal wiring 108
The gate electrode 103 of the interlayer insulating film 104 is electrically connected to the gate electrode 103 and the semiconductor substrate 101.
A fine connection hole 105a is formed thereon and a fine connection hole 105b is formed on the semiconductor substrate 101 by dry etching.

At this time, the fine connection hole 105a on the gate electrode 103 has a fine connection hole diameter D1 smaller than the hole diameter D at which the etching stop occurs, as shown in FIGS. 2 and 3, and the fine connection hole D2 on the semiconductor substrate 101 has the etching stop. The diameter of the fine connection hole where no occurrence occurs is made larger than D.

As in the first embodiment, the etching is performed under the etching condition in which the etching stops at the diameter D1 of the fine connection hole 105a on the gate electrode 103, and the interlayer insulating film 104 in the fine connection hole 105b is completely etched. Etch until done. In this etching, first, as shown in FIG. 5A, as the first step of the etching, the BPSG film 110 is completely etched.
The etching is performed until the silicon nitride film 104 is exposed, and then, as shown in FIG. 5B, the silicon nitride film 104 is etched as a second step.

At this time, since the silicon nitride film 109 is provided below the interlayer insulating film 104, the etching stop depth is sufficient up to the depth of the fine connection hole 105a.
The etching depth is set so that the interlayer insulating film 104 does not remain in the fine connection hole 105a.

As described above, the deep connection hole 105b
Since the connection hole diameter is larger than the shallow connection hole diameter 105a, if the distance between the connection hole 105b and the gate electrode 103 is reduced with miniaturization, a short circuit between the gate electrode 103 and the connection hole 105b may occur due to misalignment during photolithography.

In the second embodiment, the silicon nitride film 109 is deposited on the first layer of the interlayer insulating film 104 as an etching stopper, so that the fine connection hole 105b and the gate electrode 103 during etching are formed.
Short circuit can be prevented.

[0045]

As described above, according to the present invention, since the fine connection hole is not etched beyond the predetermined etching depth, the amount of overetch of the shallow connection hole can be reduced, and the problem of overetch can be eliminated. The reliability of the device can be improved.

Conventionally, as a means for solving the problem of over-etching due to etching, a film having a different etching rate is used as an insulating film as an interlayer insulating film and used as an etching stopper. However, the process of forming the interlayer insulating film becomes complicated. In addition, the etching process also requires several steps of processing. On the other hand, according to the present invention, the problem of over-etching can be solved by controlling only the etching conditions, so that the manufacturing period can be shortened.

Further, by depositing a silicon nitride film as an etching stopper on the first layer of the interlayer insulating film,
It is possible to prevent misalignment due to miniaturization and short circuit between the fine connection hole and the gate electrode.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an etching time and an etching depth.

FIG. 3 is a diagram showing a relationship between an etching time and an etching depth.

FIG. 4 is a diagram showing a relationship between an etching time and an etching depth.

FIG. 5 is a sectional view showing a second embodiment of the present invention.

FIG. 6 is a sectional view showing a conventional semiconductor device.

FIG. 7 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 element isolation layer 103 gate electrode 104 interlayer insulating film 105a connection hole 105b connection hole

Claims (12)

[Claims] An interlayer insulating film is formed on a semiconductor substrate, and connection holes having different depths for making electrical connection with a metal wiring layer formed on the interlayer insulating film are simultaneously formed in the interlayer insulating film by dry etching. In the method of manufacturing a semiconductor device to be formed, the diameter of a shallow connection hole is defined as the diameter of a connection hole that causes etching top, and the diameter of a deep connection hole is at least larger than the diameter of the shallow connection hole and does not cause etching stop. A method of manufacturing a semiconductor device, wherein etching is performed under an etching stop condition to form a connection hole. 2. The method according to claim 1, wherein the diameter of the deep connection hole is at least 0.05 μm larger than the diameter of the shallow connection hole. 3. The etching stop condition is characterized in that etching is stopped at a desired depth smaller than the diameter of a certain connection hole, and the etching continues at a connection hole diameter larger than the certain connection hole. The method for manufacturing a semiconductor device according to claim 1, wherein 4. The semiconductor according to claim 1, wherein the etching stop condition is such that etching is stopped at a depth where the underlying conductive layer is not exposed in a shallow connection hole accompanied by the etching stop. Device manufacturing method. 5. In a shallow connection hole, after the connection hole is etched under the condition that the etching stops at a depth where the underlying conductive layer is not exposed, the insulation remaining in the shallow connection hole under the condition that the etching stop does not occur at each connection hole diameter. The method according to claim 4, wherein the film is etched until the underlying conductive layer is exposed. 6. The method according to claim 1, wherein an etching stop condition is controlled by a mixing ratio of an etching gas used. 7. The method according to claim 1, wherein an etching stop condition is controlled by an operation pressure in the etching. 8. A first insulating film having a generally low etching rate is deposited on a semiconductor substrate under the same etching conditions, and a second insulating film having a relatively high etching rate is formed on the first insulating film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a film is deposited. 9. The method according to claim 8, wherein the first insulating film is made of a silicon nitride film, and the second insulating film is made of a silicon oxide film. 10. The method for manufacturing a semiconductor device according to claim 1, wherein a CF-based gas is contained as an etching gas species. 11. The semiconductor according to claim 6, wherein the etching gas species includes at least a gas species that reacts with a substance containing carbon deposited on the semiconductor device to generate a reaction product having a high vapor pressure. Device manufacturing method. 12. The method according to claim 11, wherein oxygen is used as the etching gas species.