DE10394263B4 - Method for producing an integrated circuit - Google Patents

Abstract

A method (600) of forming an integrated circuit comprising:
Depositing an underlayer (214) (320) over a semiconductor device (213) (317) and a first semiconductor substrate (201);
Etching down to the underlayer (214) (320) a first opening (228) (338) (402) to a first depth in a dielectric material (216) (322) over the semiconductor device (213) (317) and the first Semiconductor substrate (202), and underlayer (214) (320);
Etching down to the underlayer (214) (320) a second opening (230) (340) (404) to a second depth different from the first depth in the dielectric material (216) (322) over the first semiconductor substrate (202) wherein the first and second openings (228) (338) (402) (230) (340) (404) are dimensioned differently such that up to the first and second depths in approximately the same time due to the etch delay etched;
Removing the underlayer (214) (320) from the openings; and
Filling the ...

Description

BACKGROUND

TECHNICAL AREA

The present invention relates generally to integrated circuits and, more particularly, to contacts formed down to active regions under a dielectric layer.

BACKGROUND OF THE INVENTION

Most electronic devices, such as computers, radio receivers, televisions, cell phones, etc. use integrated circuits. At the heart of these integrated circuits are semiconductor devices, which may be transistors, diodes, capacitors, and the like. The semiconductor devices are generally fabricated on semiconductor substrates and covered by insulating or dielectric materials.

For example, transistors are formed by implanting spaced source / drain regions into the semiconductor substrate and forming control gate electrodes over the semiconductor substrate over the distance between the source / drain regions. A dielectric is then deposited over the transistors. Since electrical connections to the source / drain regions and to the control gate electrodes must be made, metal contacts are formed through the dielectric layer to the tops of the control gate electrodes and to the surface of the semiconductor substrate. Since the tops of the control gate electrodes and the surface of the semiconductor material are at different levels in the dielectric layer, the contacts are referred to as multilevel contacts, and more particularly as two-level contacts.

As the electronics industry manufactures an ever-increasing number of semiconductor devices in a single integrated circuit, manufacturers are seeking better ways to reduce the size of devices by reducing component geometries or feature sizes.

A new technology for size reduction of device geometries is the so-called "silicon on insulator" or SOI technology. The SOI technology relates to the fabrication of semiconductor devices on a layer of semiconductor material disposed over an insulating layer in a semiconductor substrate. A common embodiment of the SOI structure is a single active layer of silicon overlying a layer of silicon dioxide insulator material in a silicon substrate.

In SOI technology, additional contacts to the silicon of the substrate are required, which is at a level below the bottoms of the control gate electrodes and the surface of the silicon active layer. Therefore, the SOI technology requires multi-level contacts, which in this case are three-level contacts. In the JP 10-154752A and the JP 2003-45 963 A For example, etching processes for producing contact openings having different etching depths are described.

In the fabrication of multi-level contacts in SOI technology, an etch process is used wherein contact holes are patterned to have the same diameter. The etching through the dielectric layer strikes the topmost layer, i. H. the top of the gate electrode is reached earlier than on the active silicon layer and much earlier than the underlying silicon in the substrate. Since the duration of the etch process must be sufficient to reach the deepest levels, considerable re-etching of the least deep levels occurs. To reduce the re-etching, a sub-layer or an etch-stop layer is provided over the gate electrodes, the source / drain regions, and the substrate silicon. The underlayer is a dielectric etch stop layer or a gate material (silicon / metal) and a substrate silicon (active and / or SOI substrate).

However, the immunity or selectivity of the underlayer is limited with respect to the etching process. As a result, a significant portion of the underlayer is removed during a long-lasting re-etching. The required thickness of the underlayer is determined by the maximum post etch time and the etch rate for the underlayer, which in turn is associated with the selectivity. Multi-level contacts require a much longer etch than a single-level contact.

Disadvantageously, the thickness of an underlayer is limited by geometric aspects. This is especially true for CMOS technologies with high gate electrode density. Since contacts to the active silicon are often made between two gate electrodes, the thickness of the underlayer must be less than half the distance between the gate sidewall spacers disposed around the gates and where the contact is formed. If the thickness of the underlayer is greater than one-half of the pitch, the underlayer areas of the two gate electrodes will "fuse" and form an increased thickness of the underlayer, which will then prevent proper etching.

Also, if the etch requirement for a given thickness of the underlayer is above the maximum thickness of the underlayer that is acceptable by geometrical constraints, then disadvantageously, the multilayer contacts may not be formed in a single etch process. This requires several etching processes and a separate structuring of the individual different plane contacts. For example, if two separate structuring steps are required, it is necessary to mask the shallower contacts, then etch, mask the deep contacts, and then etch again. This leads to increased process complexity and increased costs.

While it is desirable to be able to apply a maximum thickness sublayer to accomplish the etch within comfortable process limits, this presents problems. The typically used sublayers are made of materials such as silicon nitride and silicon oxynitride which have a dielectric constant greater than that of the pre-metallization dielectric layers. This results in increased parasitic capacitance in areas such as the gate contact area, the gate edge zone and the gate first metallization layer area.

Some SOI technologies do not use a sublayer. In these situations, noticeable re-etching occurs on the active silicon during multilevel contact etch, and particularly during etching down to the substrate silicon. Since the selectivity to silicon is limited, this leads to etching into the active silicon. Accurate control of the etch is required to avoid shorting the source / drain regions. This requires improved process control and increased costs.

SOI technology offers the prospect of improved device isolation, reduced footprint, and reduced parasitic capacitance, low power consumption, and increased performance, but these problems prevent them from being realized.

A solution to these problems has long been sought in this area.

OVERVIEW OF THE INVENTION

The present invention provides a method of fabricating an integrated circuit comprising:
Depositing an underlayer over a semiconductor device and a first semiconductor substrate;
Etching to the underlayer of a first opening to a first depth in a dielectric material over the semiconductor device and the first semiconductor substrate and the underlayer;
Etching to the underlayer of a second opening to a second depth different in depth from the first depth in the dielectric material over the first semiconductor substrate, wherein the first and second openings are differently dimensioned so that up to the first and second depths in FIG etched at approximately the same time due to the etch delay;
Removing the underlayer from the openings; and
Filling the first and second openings with a conductive material;
the method further comprising:
Determining etch delays for multiple openings by:
Etching a plurality of different sized and deep openings in the dielectric material, including a calibration opening dimensioned like the first opening;
Measuring the plurality of depths obtained from the etching of the plurality of openings; and
Calculating the plurality of etch delays equal to one minus the ratio of the depth of the calibration aperture to the plurality of depths; and determining an optimal etch delay by:
Calculating one minus the ratio of the first depth to the second depth; and
Sizing the second aperture based on the size of the aperture with the etch delay closest to the optimal etch delay.

Certain embodiments of the present invention have further advantages in addition to or in lieu of the aforementioned advantages. These advantages will become apparent to those skilled in the art upon reading the following detailed description in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

1 FIG. 12 is an aspect ratio dependent etching (ARDE) calibration structure with an etchable material; FIG.

2 Fig. 12 is a view of a two-level etched contact structure according to the present invention;

3 Fig. 12 is a view of a three-level etched contact structure according to the present invention;

4 Fig. 12 is a view of an alternative embodiment of a three-level etched contact structure in accordance with the present invention;

5 Fig. 12 is a view of a three-level etched contact structure according to the present invention; and

6 Fig. 10 is a flowchart showing a method of manufacturing an integrated circuit according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

While studying the multilevel contact problem, the inventors recognized that an undesirable phenomenon in the contact etch process can be advantageously exploited.

A phenomenon called "aspect ratio dependent etching" (ARDE) causes different feature sizes in a photoresist to be etched at different rates in a dielectric layer. Under the same process conditions, smaller aperture structural members etch more slowly than larger aperture structural members, and under other process conditions etch larger apertures more slowly than smaller aperture structural members.

For example, when a reactive ion etch (RIE) process is used in a plasma reactor to perform a plasma dry etch, the phenomenon known as "RIE" delay or etch delay occurs, especially when feature sizes (apertures in a photoresist) are below 0.25 μm lie. The RIE delay causes structural elements with smaller openings in a dielectric material to etch slower than structural elements with large openings. This is undesirable because each etch step is generally intended to etch to a common depth, regardless of feature size. At present, those skilled in the art are saying that the etching process should be optimized by minimizing the RIE delay. When optimizing a plasma desalting process to minimize the RIE delay, there is usually some compromise to be made, such as lower selectivity to the etch stop layers.

The term "horizontal" as used herein is defined as a plane parallel to the conventional plane or surface of a disk or substrate, regardless of their orientation. The term "vertical" refers to a direction perpendicular to the horizontal direction as just defined. Terms such as "on," "over," "under," "beside, or side" (as in "sidewall"), "higher," "lower," "above," "below," "flat," and "deep." are defined in terms of the horizontal plane.

As used herein, the term "processing" includes depositing a material or photoresist, patterning, exposing, developing, etching, cleaning and / or removing the material or photoresist as described to produce one Structure is required.

In 1 is a calibration structure 100 for aspect ratio dependent etching (ARDE). A dielectric calibration material 102 has formed thereon a photoresist 104 on.

The photoresist 104 is processed to form a plurality of features over a range of sizes from a minimum photolithographic diameter to a multiple of that diameter; For example, the minimum diameter may be 100 nm and the range may be up to a maximum contact diameter of 1000 nm. For purposes of illustration, a first, a second, and a third opening 106 . 108 and 110 shown having a plurality of dimensions, for example, a corresponding first, a second and a third dimension 112 . 114 and 116 , The dimensions or dimensions of the structural elements are dimensioned such that the first dimension 112 smaller than the second dimension 114 is, in turn, smaller than the dimension 116 is; ie the third dimension 116 is larger than the second dimension 114 , which in turn is larger than the first dimension 112 is.

The dimensions of the features in the photoresist represent the initial dimensions of the features included in the dielectric calibration material 102 be etched.

In situations where the phenomenon of etch delay occurs, the first, second, and third openings form 106 . 108 and 110 a corresponding first, second and third structural element 118 . 120 and 122 in the dielectric calibration material 102 , During a single etch or a single time period, the first, second, and third features feature 118 . 120 and 122 correspondingly a first, a second and a third depth 124 . 126 and 128 , ARDE is generally a non-linear effect. Since the structural elements in their size starting from the first dimension 112 up to the third dimension 116 increase, take the depths starting from the first depth 124 and the third depth 128 to; ie larger structural elements etch faster and reach a greater depth during the same time.

While contact openings may take on various configurations when the structural elements are intended for cylindrical contact openings, the first, second and third dimensions are 112 . 114 and 116 in the photoresist 104 the Diameter of the tops of the contact openings in the dielectric calibration material 102 ,

In most etching processes, the features tend to taper in size with increasing depth in the dielectric calibration material 102 in that the underside of the contact holes has a smaller diameter than the upper side.

In 2 is a contact structure etched in two levels 200 shown in accordance with the present invention.

A first semiconductor substrate 202 or a substrate silicon is formed by implanting with source / drain regions 204 and 206 provided with a gate dielectric 208 over a distance between the source / drain regions 204 and 206 is provided. A gate 210 is above the gate dielectric 208 arranged and is of a gate spacing element 212 surrounded to thereby the upper portion of a semiconductor device 213 to build. An underclass 214 is over the first semiconductor substrate 202 arranged so that the gate spacer 212 and the gate 210 to be covered.

A dielectric pre-metal layer 216 is above the lower class 214 deposited and a photoresist layer 218 becomes over the dielectric pre-metal layer 216 deposited.

The photoresist 218 is machined to a first and a second opening 220 and 222 with a first and a second diameter respectively 224 and 226 exhibit. Applying a single etching process for a fixed period of time becomes a gate contact 228 and an area contact 230 formed the lower layer 214 reach at about the same time, with no or minimal re-etching into the underlayer 214 he follows.

In practice, first the minimum contact diameter is formed; for example, the first diameter 224 for the gate contact 228 , In practice, this value is often determined by the minimum aperture that can be reliably resolved in a photoresist through the applied photolithographic process. The minimum contact diameter is used for contacts of the least deep level.

Second, the etch delay of the etch process is accomplished using the techniques described in U.S. Pat 1 shown calibration structure 100 determined by forming structure openings over a range of sizes from the minimum contact diameter to a multiple of that diameter; for example, the minimum diameter may be 100 nm and the range may extend up to the maximum contact diameter of 1000 nm.

L

= Ätzverzögerung ist;

D_min

= Tiefe des Kontakts mit dem minimalen Durchmesser ist;

D

= Tiefe eines Kontakts mit einem anderen Durchmesser ist.

Third, a timed etch is performed and the depths of the resulting etched apertures are calculated to determine the etch delay according to the equation: L = 1 - (D _min / D) (Equation 1) in which:

L

= Etch delay;

D _min

= Depth of contact with the minimum diameter;

D

= Depth of a contact with a different diameter.

The etch delay in the above illustration is not necessarily linear to the diameter and depth.

L_Optimal

= optimale Ätzverzögerung ist;

CD_Shallow

= Abmessung für die kleinste Kontakttiefe ist;

CD_Deep

= Abmessung für die größte Kontakttiefe ist.

Fourth, an optimal etch delay for the different contact depths desired in the final integrated circuit is calculated according to the equation: L _Optimal = 1 - (CD _Shallow / CD _Deep ) (Equation 2) in which:

L _Optimal

= optimum etch delay;

CD _Shallow

= Dimension for the smallest contact depth;

CD _Deep

= Dimension for the largest contact depth.

Fifth, using the smallest feature size becomes the calibration structure 100 is used to select pattern opening sizes based on the desired etch depths at which the pattern etch delay most closely approximates the optimal etch delay. A diameter is selected as the diameter which gives an etch delay closest to the optimum etch delay. With such a selection of the contact diameter, the process reaches the bottoms of both the shallow and deep contacts at approximately the same time.

In 3 is a contact structure etched in three levels 300 shown in accordance with the present invention.

A second semiconductor substrate 302 or a substrate silicon has an insulator 304 which is deposited on it and which is the first semiconductor substrate 306 or contains active silicon. The first Semiconductor substrate 306 has implanted source / drain regions therein 308 and 310 on.

Above and above the source / drain regions 308 and 310 is a gate dielectric 312 educated. Above the gate dielectric 312 is a gate 314 arranged, which has a gate spacer 316 formed around it, so as to the upper portion of a semiconductor device 317 to build. A ditch 318 is in the insulator 304 etched, and an undercoat 320 is so deposited that the insulator 304 , the first semiconductor substrate 306 , the gate spacer 316 and the gate 314 are covered.

A pre-metal dielectric layer 322 is above the lower class 320 deposited.

A photoresist 324 is above the pre-metal dielectric layer 322 deposited and processed so that a first, a second and a third contact opening 326 . 328 and 330 are formed. The first, the second and the third contact opening 326 . 328 and 330 have correspondingly a first, a second and a third diameter 332 . 334 and 336 , The first diameter 332 is smaller than the second diameter 334 and the second diameter 334 is smaller than the third diameter 336 ,

The contact structure etched in three levels 300 has the optimum etch delay and the contact diameter, which is calculated separately for the very deep and the medium depth contact. The resulting contact dimensioning enables the etching process for the first, second and third contact openings 338 . 340 and 342 the lower class 320 reached at about the same time for all three contact depths. Thus, the amount of post etching time required is minimized, which in turn minimizes the required thickness of the underlayer.

4 shows an alternative embodiment of an etched in three levels contact structure 400 according to the present invention. Elements that are equal to the elements in 3 , have the same reference numerals.

The contact structure etched in three levels 400 has a first, a second and a third contact opening 402 . 404 and 406 with a corresponding first, second and third diameters 408 . 410 and 412 , The first diameter 408 and the second diameter 410 own the same size. The second diameter 410 is smaller than the third diameter 412 , The first and the second diameter 408 and 410 are provided with the same size to simplify the circuitry and the mask generation. At the same time, this can prevent the chip size of the integrated circuit from increasing.

Since the distance between the first and second planes is small compared to the third plane, the etching process continues until the second contact opening 404 the lower class 320 reached. At this point you can expect the first and the third contact opening 402 and 406 slightly in the lower layer 320 when Nachätzen bring, as by the first and third Nachätzbereich 414 and 416 is marked. This minor etching is considered acceptable in order to obtain the benefits of having the first and second diameters 408 and 410 are of the same size.

In 5 is a contact structure etched in three levels 500 shown as obtained according to the present invention. The same elements that are in 3 are shown, also here have the same reference numerals.

After a selective etch to remove the remaining undercoat 320 from the contact openings 338 . 340 and 342 , the openings are filled with conductive material to the first, the second and the third contact 502 . 504 and 506 to build. The first, the second and the third contact 502 . 504 and 506 are corresponding to the gate 314 , the first semiconductor substrate 306 and the second semiconductor substrate 302 in connection. The first, the second and the third contact 502 . 504 and 506 have correspondingly a first, a second and a third contact diameter 508 . 510 and 512 ,

In various embodiments, the first, second and third contacts are 502 . 504 and 506 made of refractory materials, such as tantalum (Ta), titanium (Ti), tungsten (W), alloys thereof and compounds thereof. When the contacts are formed of highly conductive materials such as copper (Cu), gold (Au), silver (Ag), alloys thereof and compounds thereof having one or more of the above elements, the aforementioned refractory materials surround the highly conductive materials. The dielectric pre-metal layer 322 is made of a dielectric material such as silicon oxide (SiO _x ), tetraethyl orthosilicate (TEOS), boron phosphosilicate (BPSG) glass, etc. having dielectric constants of 4.2 to 3.9, or are made of dielectric materials having a small dielectric constant , such as fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), diacetoxy-diarylbutyoxysilane (DADBS), etc., having dielectric constants below 3.9. The lower class 320 when used, is made of a material such as silicon nitride (Si _x N _x ) or silicon oxynitride (SiON).

In 6 a flow chart is shown, wherein a method 600 for producing an integrated circuit according to the present invention. The procedure 600 includes: a step 602 for etching a first opening to a first depth in a dielectric material disposed over a semiconductor device on a first semiconductor substrate; a second step 604 for etching a second opening to a second depth in the dielectric material over the first semiconductor substrate, wherein the first and second openings are differently dimensioned to correspondingly to the first and second depths in approximately the same time due to the etch delay to etch; and a step 606 for filling the first and second contact openings with conductive material.

Claims (5)

Procedure ( 600 ) for forming an integrated circuit comprising: depositing an underlayer ( 214 ) ( 320 ) over a semiconductor device ( 213 ) ( 317 ) and a first semiconductor substrate ( 201 ); Etching to the lower layer ( 214 ) ( 320 ) a first opening ( 228 ) ( 338 ) ( 402 ) to a first depth in a dielectric material ( 216 ) ( 322 ) over the semiconductor device ( 213 ) ( 317 ) and the first semiconductor substrate ( 202 ), and the lower class ( 214 ) ( 320 ); Etching to the lower layer ( 214 ) ( 320 ) a second opening ( 230 ) ( 340 ) ( 404 ) to a second depth different from the first depth in the dielectric material ( 216 ) ( 322 ) over the first semiconductor substrate ( 202 ), wherein the first and the second opening ( 228 ) ( 338 ) ( 402 ) ( 230 ) ( 340 ) ( 404 ) are dimensioned differently such that etching is up to the first and second depths in approximately the same time due to the etch delay; Removal of the lower layer ( 214 ) ( 320 ) from the openings; and filling the first and second openings ( 228 ) ( 338 ) ( 402 ) ( 230 ) ( 340 ) ( 404 ) with a conductive material; the method further comprising: determining etch delays for a plurality of apertures by: etching a plurality of different sized and deep apertures into the dielectric material ( 102 ), wherein a calibration opening ( 118 ), which is dimensioned like the first opening ( 228 ) ( 338 ) ( 402 ); Measuring the plurality of depths obtained from the etching of the plurality of openings; and calculating the plurality of etch delays equal to one minus the ratio of the depth of the calibration aperture ( 118 ) to the several depths; and determining an optimal etch delay by: calculating one minus the ratio of the first depth to the second depth; and dimensioning the second opening ( 230 ) ( 340 ) ( 404 ) based on the size of the aperture with the etch delay closest to the optimum etch delay. Procedure ( 600 ) according to claim 1, further comprising: sizing the second opening ( 230 ) ( 340 ) ( 404 ) with respect to the first opening ( 228 ) ( 338 ) ( 402 ), so that a non-linear relationship with the etching delay of the second opening ( 230 ) ( 340 ) ( 404 ) and the etching delay of the first opening ( 228 ) ( 338 ) ( 402 ) consists. Procedure ( 600 ) according to claim 1, further comprising: etching a third opening ( 342 ) ( 406 ) to a third depth different from the first and second depths ( 128 ) ( 128 ) in the dielectric material ( 322 ) over a second semiconductor substrate ( 302 ) ( 302 ) and the first semiconductor substrate ( 306 ), wherein the first, second and third openings are dimensioned differently to correspond to the first, second and third depths ( 128 ) ( 128 ) due to the etching delay in about the same time; and filling the third opening ( 342 ) ( 406 ) with conductive material. Procedure ( 600 ) according to claim 3, further comprising: sizing the third opening ( 342 ) ( 406 ) with respect to the first opening ( 228 ) ( 338 ) ( 402 ) such that a non-linear relationship corresponding to the etching delay of the third opening ( 342 ) ( 406 ) and the etching delay of the first opening ( 228 ) ( 338 ) ( 402 ) consists. Procedure ( 600 ) according to claim 3, further comprising: determining a second optimum etching delay by calculating one minus the ratio of the first depth to the third depth ( 128 ) ( 128 ); and dimensioning the third opening ( 342 ) ( 406 ) based on the size of the aperture having an etch delay closest to the third optimal etch delay.

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