DE60211915T2 - Semiconductor structure using surgery materials and related manufacturing methods - Google Patents

Semiconductor structure using surgery materials and related manufacturing methods

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Publication number
DE60211915T2
DE60211915T2 DE60211915T DE60211915T DE60211915T2 DE 60211915 T2 DE60211915 T2 DE 60211915T2 DE 60211915 T DE60211915 T DE 60211915T DE 60211915 T DE60211915 T DE 60211915T DE 60211915 T2 DE60211915 T2 DE 60211915T2
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Prior art keywords
metallized
semiconductor device
plurality
dielectric
copper
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DE60211915T
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German (de)
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DE60211915D1 (en
Inventor
Yehiel Fremont GOTKIS
Rodney Los Gatos KISTLER
David Fremont WEI
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Lam Research Corp
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Lam Research Corp
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Priority to US09/821,415 priority Critical patent/US6984892B2/en
Priority to US821415 priority
Application filed by Lam Research Corp filed Critical Lam Research Corp
Priority to PCT/US2002/009617 priority patent/WO2002103791A2/en
Application granted granted Critical
Publication of DE60211915D1 publication Critical patent/DE60211915D1/en
Publication of DE60211915T2 publication Critical patent/DE60211915T2/en
Active legal-status Critical Current
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/1042Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

  • BACKGROUND THE INVENTION
  • 1st area the invention
  • The The present invention relates generally to manufacturing technologies for semiconductor devices and techniques for improving the performance of semiconductor devices. In particular, the present invention relates to the use of Sacrificial materials to improve the performance of semiconductor devices to improve.
  • 2. Description of the related technology
  • As is known, the semiconductor industry is moving towards the use of larger substrates, the one higher Have density with devices with smaller designs. Around To fulfill the task Millions of transistors are made up of multilayer layers metallized interconnections, insulating dielectric layers and conductive via structures and on a wafer substrate produced. Originally The metallized wires and vias were mainly out Made of aluminum because it is relatively inexpensive, easy to etch and has a relatively low resistance, while the insulators mainly out Silica were produced. By reducing the size of part features, Vias and contact openings and the distance between the metallized connecting lines In connection with the development of on-chip systems, there is an increased demand on improving the performance of semiconductor devices by replacing the materials used in semiconductor manufacturing be used. So far this has been a double task.
  • At first was instead of aluminum copper for the connecting leads, vias and contact openings used. The replacement of aluminum by copper was beneficial because the copper had a lower resistance and better conductivity and electromigration properties has as aluminum. However, replacement of aluminum with copper has been problematic because there are fundamental changes in the formation of metal compounds required. While aluminum fasteners in particular by etching away from unprotected places the thin, the surface a substrate covering aluminum layer can be made Connectors made of copper by applying copper in vias and trenches etched in dielectric layers. As a result Of these, in a semiconductor device, the copper interconnection elements a planarization process is performed on the surface of the substrate, for excess copper remove from areas of the dielectric that do not have trenches, Vias or contact pins included.
  • Secondly Instead of silicon dioxide, lower dielectric materials were used permittivity or dielectric materials of a so-called low K value used as insulators. Dielectric materials with low K value are preferred because firstly they have the capacity of connecting line to reduce connection line, since the coupling capacity between two metalized interconnections that are very close together are arranged, in direct proportion to the dielectric constant of the dielectric insulating material used. Second, reduce low-K dielectric materials, the crosstalk noise, because the lower the dielectric constant of a dielectric The lower the probability of signal interference by intersecting metallized lines. While that most often used dielectric, silicon dioxide, for example, a dielectric Constant of about 4.0, air has the lowest dielectric constant of 1.0 and other low K dielectric materials of about 1.5 to about 3.5. Since it was recognized that air is the lowest dielectric constant There has been a tendency in semiconductor manufacturing technology to to process dielectric materials with dielectric constants, close to those of air.
  • So far, such attempts have led to the production of very porous dielectric materials. However, both the low mechanical strength of such porous dielectric materials and the current state of semiconductor fabrication technology prevent their use in the semiconductor fabrication process. In particular, the low mechanical strength of low K dielectric materials is problematic when the chemical mechanical planarization (CMP) process is performed on the metallized copper lines. As is well known, in a CMP process, the substrate is forced against a moving polishing pad, thereby removing the excess metal from the surface of the substrate. However, performing a CMP process on a semiconductor device having low K porous dielectric material is complicated because pressing the surface of the substrate against the polishing pad may cause areas of the semiconductor structure to collapse or crack, thereby increasing performance is reduced or even required to discard the semiconductor wafer produced. It can be seen that the production rate of good chips in case of occurrence of these problems during the semiconductor manufacturing process, in addition to the reduction of the Wafer throughput can decrease dramatically.
  • The document US 5,034,799 A discloses an integrated circuit device having a hollow multilayered line structure.
  • in view of the above statements a need for semiconductor structures using conventional Techniques can be made that provide good structural support during CMP operations, yet devices can be made which, as in use of low K dielectric materials, low capacitive delays exhibit.
  • SUMMARY THE INVENTION
  • Generally spoken fulfilled the present invention solves this need by providing the manufacture of Semiconductor structures using standard dielectric materials allows the usual in the chemical-mechanical planarization mechanical loads and pressures can resist. In a preferred embodiment A sacrificial material is used to make any layer of copper compounds a semiconductor structure which is later etched away and by an insulator replaced by a low dielectric constant (low K value) Has. In another embodiment a plurality of trunnions are formed in each sacrificial layer, thereby continuously formed supporting columns when the victim material is etched away. It goes without saying that the present invention in numerous ways, including as Process, as a device, as a system, as a device or as a process can be realized. Several inventive embodiments The present invention will be described below.
  • In an embodiment For example, a semiconductor device is disclosed. The semiconductor device comprises a substrate with transistor devices and multiple metallized Connecting leads and conductive vias made of copper. The several metallized connecting lines and conductive vias are made of copper in each of a plurality of connection levels of the semiconductor device formed so that the multiple metallized connecting lines and conductive vias of copper are insulated from each other by an air dielectric. The semiconductor device further comprises a plurality of trunnions, each of these trunnions being designed to form a support column, extending through the multiple interconnect levels of the semiconductor device extends.
  • In another embodiment For example, a semiconductor device is disclosed. The semiconductor device includes a substrate with transistor devices and multiple metallized ones Connecting leads and conductive vias made of copper. The several metallized interconnections and conductive vias made of copper are in each of several connection planes of the semiconductor device formed so that the plurality of metallized connecting lines and conductive vias of copper through a porous dielectric material isolated from each other. The semiconductor device further comprises a plurality of trunnions, each of these trunnions being so formed is that it forms a support column, extending through the multiple interconnect levels of the semiconductor device extends.
  • In yet another embodiment For example, a method of manufacturing a semiconductor device is disclosed. The method begins with the formation of transistor structures a substrate. Thereafter, metallized connection structures formed in multiple levels by applying a sacrificial layer is done, a double damascene process is done to trenches and vias to etch, and filled the trenches and vias and planarized. After that, the sacrificial layer becomes in all of the several Etched away levels of metallized interconnect structures, wherein the etching leaves a free metallized connection structure. The free metallized connection structure is then covered with a dielectric Material filled with low K value, leaving a metallized Connection structure is formed with low K value.
  • at yet another embodiment discloses a method of manufacturing a semiconductor device. The method begins with the formation of transistor structures a substrate, followed by the formation of metallized interconnect structures in several levels. The metallized connection structures become formed by applying a sacrificial layer, a double damascene process is performed, to etch trenches, vias and cones, and the trenches, vias and cones are filled and planarized. Subsequently becomes the sacrificial layer in all of the multiple levels of metallized Etched connection structures away, wherein a free metallized connection structure and trunnions be left behind.
  • The present invention has numerous advantages. Most notably, while the semiconductor structure of the present invention ultimately uses low-K air or dielectric materials as a dielectric, the semiconductor structure of the present invention resists the structural stresses and pressures encountered during CMP and other operations. In this way, the disadvantages associated with the use of air or dielectric materials are with low K value in semiconductor manufacturing processes are substantially eliminated, while minimizing the dielectric capacitance between the metals and allowing faster integrated circuit elements to be fabricated.
  • Semiconductor devices and methods of making these devices are disclosed in U.S. Patent Nos. 5,194,954 independent claims 1, 5, 7 and 13 indicated. Further embodiments of the invention are in the subclaims specified.
  • Other Aspects and advantages of the invention will become apparent from the following detailed Description in conjunction with the accompanying drawings, which based on embodiments explain the principles of the invention.
  • SHORT DESCRIPTION THE DRAWINGS
  • The The present invention is explained by the following detailed description in connection with the attached Drawings in which like reference numerals refer to like components denote, easy to understand.
  • 1A is a simplified partial, exploded and sectional view of a semiconductor structure according to an embodiment of the present invention, in which a di electrical intermediate layer (ILD) is formed over a substrate comprising a plurality of active devices.
  • 1B is a simplified partial, exploded and sectional view of the semiconductor structure of 1A according to another embodiment of the present invention, further comprising a first sacrificial layer having a plurality of metallized lines, vias and trunnions formed therein.
  • 1C is a simplified partial, exploded and sectional view of the semiconductor structure of 1B according to yet another embodiment of the present invention, wherein a plurality of sacrificial layers have been made, each comprising a plurality of trunnions.
  • 1D FIG. 4 is a simplified partial, exploded and sectional view of a semiconductor structure according to yet another embodiment of the present invention having multiple layers after the etching process using air as the dielectric material. FIG.
  • 1E FIG. 12 is a simplified partial, exploded and sectional view of the multi-layer semiconductor structure using an air dielectric after the etching process according to an aspect of the present invention, further comprising a passivation capping layer. FIG.
  • 1F-1 is a simplified partial, exploded and sectional view of the multilayer semiconductor structure of 1D after the etching process filled with a low K porous dielectric material according to another aspect of the present invention.
  • 1F-2 is a simplified partial, exploded and sectional view of the low-K dielectric filled semiconductor structure of FIG 1F after the etching process covered with a passivation capping layer according to another aspect of the present invention.
  • 2 FIG. 10 is a flow chart of the process steps performed to fabricate a semiconductor structure using an air dielectric according to another aspect of the present invention having a plurality of metallized leads and trunnions made of copper.
  • 3 Figure 4 is a general flow chart of the operations of the method of fabricating a semiconductor structure according to another embodiment of the present invention having a low K porous dielectric having multiple metallized leads of copper.
  • PRECISE DESCRIPTION THE EXEMPLARY EMBODIMENTS
  • It Be exemplary embodiments for producing semiconductor structures that describe the performance optimize the semiconductor by changing the dielectric capacitance between the metals is minimized. In a preferred embodiment is during making each layer of copper compounds a sacrificial material used, then etched away and replaced by an insulator having a low dielectric constant having. In another embodiment a plurality of pins are formed in the sacrificial layer, thereby almost continuous support columns are generated when the sacrificial layer is etched away becomes. In preferred embodiments, the cones are made of cones essentially continuous support columns designed so that they from the passivation layer to a passivation capping layer extend, whereby a semiconductor structure is formed, which is a high structural integrity and a reduction in capacity-induced delays having. In a preferred embodiment, the plurality of pins made of copper. In another embodiment, the sacrificial layer is a dielectric and the low K dielectric material is a porous one dielectric material.
  • In the following description, numerous specific details are described for a to provide a comprehensive understanding of the present invention. However, it will be understood by one of ordinary skill in the art that the present invention may be practiced without some or all of these specific details. In other instances, well-known method steps have not been described in detail so as not to unnecessarily obscure the present invention.
  • 1A is a sectional view of a semiconductor structure 100 according to one embodiment of the present invention, wherein a dielectric interlayer (ILD) over a multi-transistor substrate 102 is trained. As shown, each of the generated transistors includes multiple source / drain diffusion regions 103 that are in the substrate 102 are formed. Each of the transistors further includes a conductive polysilicon gate 120 , each through a dielectric gate oxide 118 from the substrate 102 is disconnected. In one embodiment, the source / drain zones 103 , also known as P-zones or N-zones, are formed by a doping process using impurities such as boron or phosphorus. As shown, the source / drain zones are 103 through several shallow-trench isolation zones 104 also in the substrate 102 are formed, separated. As shown, the shallow trench isolation zones become 104 made of a non-conductive material (eg, silicon dioxide, silicon nitride, etc.). Multiple dielectric spacers (spacers) 122 are along each of the sidewalls of each gate oxide 118 and polysilicon gates 120 educated.
  • Further, a dielectric interlayer (ILD) 106 in their formation above the substrate 102 shown. In preferred embodiments, the ILD 106 made of silicon oxide. However, one skilled in the art will understand that the ILD 106 can be made of any other suitable dielectric material, if this material is sufficiently robust and provides sufficient insulation. The interlayer dielectric layers are usually abbreviated as ILD 1, ILD 2 and so on. Intermetal dielectric (IMD) or pre-metal dielectric (PMD) for the first dielectric layer behind the devices are also commonly used to describe the integrated circuit architecture.
  • In the ILD 106 are several contact holes 108 formed, which are filled with a conductive material (ie, that a pin is formed), so that a substantially direct electrical connection between the metallized lines and the transistors (ie, the active components) is made possible. In one embodiment, the contact pins are formed by applying a layer of tungsten and then applying the excess tungsten from the top surface of the ILD 106 is planed off.
  • Although the contact holes 108 in this embodiment are filled with tungsten, it is obvious to a person skilled in the art that the contact holes 108 can be filled with any conductive material, if its function of making electrical connection between the metal interconnections and the active components directly from one layer to another can be achieved. Although in this example a CMP process is used to remove the excess material, it will be further understood by those skilled in the art that any other method of planarization or material removal may be used.
  • After the process of planarization becomes a passivation layer 116 over the ILD 106 formed to protect active components from corrosion and chemical reactions during subsequent manufacturing operations. In one embodiment, the passivation layer becomes 116 made of silicon nitride (SiN).
  • 1B shows the semiconductor structure 100 from 1A in that, according to an embodiment of the present invention, it further comprises a first sacrificial layer 110a comprising a plurality of metallized lines formed therein 115 , Holes for vias 112 and tenon openings 124a includes. As shown, the passivation layer becomes 116 from the first sacrificial layer 110a superimposed, which can be generated in one embodiment by chemical vapor deposition (CVD). The first sacrificial layer 110a is preferably silicon dioxide (SiO 2 ) that can be applied using any suitable deposition method. In one embodiment, the silica may be applied by decomposing a reactant of tetraethylorthosilicate "TEOS" Si (OC 2 H 5 ) 4 using any suitable deposition method. Suitable deposition methods can be chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), chemical atmospheric pressure chemical vapor deposition (APCVD), chemical subatmospheric chemical vapor deposition (SACVD), plasma assisted chemical vapor deposition (PECVD) and so on. Although the sacrificial layer was made of silicon dioxide in this embodiment, the sacrificial layer 110a in another embodiment, each material is made of copper-inert material that is mechanically strong enough to be used during the manufacturing process.
  • After the formation of the first sacrificial layer 110a a copper-double damascene process is performed to metallized Zwischenschichtlei tions and leading vias in the first sacrificial layer 110a to build. In one embodiment, first several holes for vias 112 educated. This task is solved by the first sacrificial layer 110a provided with a photoresist coating and then etched, after which the unprotected areas of the first sacrificial layer 110a down to the surface of the passivation layer 116 and up to the contact openings 108 to be removed down.
  • In preferred embodiments, in addition to the holes for vias 112 several mortise holes 124a in the first sacrificial layer 110a formed for the almost the same procedure as for the holes for vias 112 Application finds. That is, a plurality of peg-like shaped stencils are applied to the surface of the first sacrificial layer 110a are applied, which are then etched and down to the surface of the passivation layer 116 be removed. Thereafter, using the same technique, multiple trenches 114 in the first sacrificial layer 110a formed so that each of the several trenches 114 essentially on one of the covered holes for vias 112 is aligned.
  • At this time, a metal layer is applied to the surface of the first sacrificial layer 110a and in the trenches 114 , Holes for vias 112 and mortise holes 124a applied. In one embodiment, the trenches 114 filled with copper by sputtering and electroplating processes, resulting in multiple metallized interconnections 115 and conductive vias are formed. In one embodiment, prior to depositing the metal, a barrier layer (not shown in this figure) is applied over the surface of the first sacrificial layer 110a and the several holes for vias 112 and trenches 114 deposited. Exemplary metals that may be used to form a barrier layer typically include tantalum or tantalum nitride materials or a combination of both. Thereafter, a copper seed layer (also not shown in this drawing) may be applied to the barrier layer to surround the inner walls and surfaces of the plurality of vias 112 and trenches 114 undress. The seed layer is formed to allow good electrical contact for a subsequent electrodeposited copper deposition process.
  • After manufacture, the function of each of the several pins 125a therein, the multi-layered structure of the semiconductor structure 100 to wear. Unlike the multiple conductive vias 113 , which are provided to establish an electrical connection between different interconnected layers, the function of the pins 125a therefore, to provide a semiconductor structure with a high structural integrity. Accordingly, it will be understood that a semiconductor device may include any number of pins 125 which are distributed so that the best possible structural arrangement is achieved. Although the mortise holes 124a In this embodiment, it is possible to fill with copper, in another embodiment it is possible to use the mortise holes 124a with any non-etchable material or metal, provided that the material used is robust enough to form a subsequently formed passivation capping layer 118 to wear.
  • After the formation of the metallized connecting lines 115 , conductive vias 113 and cones 125a a CMP process is performed on the copper layer overlying the surface of the first sacrificial layer 110a lies around the excess copper from the surface of the sacrificial layer 110a to remove.
  • Now reference is made 1C taken that the semiconductor structure 100 from 1B according to an embodiment of the present invention having a plurality of deposited sacrificial layers 110b - 110g shows, each several pins 125b - 125g include. In one embodiment, the second, third, fourth, fifth, sixth and seventh sacrificial layers become 110b - 110g and their respective trenches 114 , metallized wires 115 , Holes for the vias 112 , conductive vias 113 , Mortise holes 124b - 125g and cones 125b - 125g formed in the same way and from the same material as in the case of the first sacrificial layer 110a and their corresponding trenches 114 , metallized wires 115 , Holes for the vias 112 , conductive vias 113 , Mortise holes 124a and cones 125a ,
  • As shown, the plurality of pins 125b - 125g each in the first to seventh sacrificial layer 110b - 110g designed so that each of the several cones 125b - 125g each on one of the several pins 125a are aligned. That is, each of the several cones 125g along with his group of aligned cones that reside in each of the sacrificial layers 110a - 110f are formed, forms a substantially continuous support column, each extending from the surface of the passivation layer 116 to the surface of the seventh sacrificial layer 110b extends. In this way, the pins form 125a - 125g a suitable support for a passivation topcoat formed thereafter 118 ,
  • 1D is a cross-sectional view of a semiconductor structure 100 ' according to an embodiment of the present invention with multiple layers after the etching process, wherein air is used as the dielectric material. As shown, the sacrificial layers became 110a - 110g of in 1C dargestell th semiconductor 100 etched away. For example, the sacrificial layers 110a - 110g be removed by a wet etching process involving a mixture of hydrofluoric acid (HF) and deionized water (ie, diluted HF (DHF)) on the sacrificial layers 110a - 110g is applied, which makes the conductive vias 113 , metallized wires 115 and cones 125a - 125g surrounding sacrificial material is removed. In an embodiment, the sacrificial material may be removed by applying the semiconductor structure 100 first immersed for a period of time in a container containing a mixture of hydrofluoric acid and deionized water. Thereafter, the mixture of hydrofluoric acid and deionized water is removed by adding the semiconductor structure 100 is rinsed, followed by a Spinspülvorgang is performed. In another embodiment, immersion etching may be enhanced by the use of heaters and movers (eg agitators, ultrasound, hypersonic, etc.). In an alternative embodiment, the semiconductor structure 100 not immersed, but the etching process by spraying the mixture of hydrofluoric acid and deionized water on the semiconductor structure 100 be performed, creating a free metallized connection structure is created. In a further embodiment, however, the proposal is made to remove the sacrificial material by oxide plasma etching.
  • Preferably is the concentration of hydrofluoric acid in the mixture of hydrofluoric acid and about deionized water 0.1% to 5.0%. For However, it is obvious to a person skilled in the art that the concentration hydrofluoric acid in the mixture of hydrofluoric acid and deionized water Any suitable concentration can take as long as the mixture is able to remove the sacrificial layers without the damaged metallized lines become. Although a mixture of hydrofluoric acid and deionized water for the implementation the etching process it is also self-evident that any suitable etchant, having a suitable concentration can be used as long as the etchant is able to remove the sacrificial material.
  • It must be noted that the cones 125a - 125g , the leading vias 113 and the metallized wires 115 are formed so that they are not affected by the etching process. That means the cones 125a - 125g , the leading vias 113 and the metallized wires 115 are made of materials that do not react with the mixture of hydrofluoric acid and deionized water. Furthermore, the removal of the sacrificial material does not affect the electrical performance of the active components as it passes through the passivation layer 116 to be protected. In addition, although air was used as an insulator in this embodiment, it is possible to use any gas having a low K dielectric value (eg, nitrogen, etc.) or any inert gas (eg, neon, argon, etc.) to replace the sacrificial material.
  • It will be up now 1E Referring to the multilayer, an air dielectric using semiconductor structure 100 ' from 1D in accordance with an embodiment of the present invention after the etching process, further comprising a passivation capping layer 118 includes. As shown, the passivation capping layer 118 in one embodiment, several vaults 116b 1 and 116b 2 include, which are formed substantially in the vacant spaces, by the removal of the sacrificial layer 125g have arisen.
  • As shown, the passivation capping layer closes 118 the generated semiconductor structure 100 ' essentially one and accomplishes two tasks. In addition to their function as a sealing passivation layer, so the corrosion and chemical reactions within the semiconductor structure 100 ' prevents the Passivierungsdeckschicht acts 118 also as a cover for the semiconductor structure 100 ' , Here are the several, essentially contiguous and from the pins 125a - 125g formed columns sufficient support for the Passivierungsdeckschicht 118 , In this type of preparation form the Passivierungsdeckschicht 118 , the several cones 125a - 125g containing several metallized wires 115 containing several conductive vias 113 and the substrate 102 a semiconductor structure that has high structural integrity along with a reduced capacitive delay.
  • 1F-1 FIG. 12 is a cross-sectional view of the multilayer semiconductor structure of FIG 1D after the etching process comprising low K dielectric layers according to an embodiment of the present invention. As shown, the sacrificial layers became 110a - 110g through dielectric layers 110a ' - 110g ' replaced, made of a dielectric material 111 were produced with low K value. The dielectric material 111 Low K value is a highly porous dielectric material with a dielectric constant that is substantially close to that of air. As such, the low K dielectric material includes multiple air filled pores 111 ' , In an embodiment, the dielectric material 111 Low K value Nanoglass from AppliedSignal Electronic Materials of Los Gatos, California, which is an air filled pore silica material that is no more than 10 nanometers in diameter. In another embodiment, each dielectric material low-K value spin-on polymer, CVD-coated organo-silicate glass (OSG), spin-on polymer, along with CVD-coated OSG, spin-on polymer in combination with gas phase evaporation technique, spin On polymer in combination with supercritical drying techniques, porous silica aerogels, hydrogen silsesquioxane-based porous XLK dielectrics from Dow Corning, silicon deposition by evaporation / oxidation in argon / oxygen atmosphere, etc.). For porous materials, the effective dielectric constant is between the dielectric constant of air (ie, 1) and the dielectric constant of the Dow Corning XLK dense material (ie, 2.2). Thus, in preferred embodiments, the dielectric constant of the low K porous dielectric material is in the range of about 1 to about 4.
  • In one embodiment, the semiconductor structure 100 ' after the etching process with the dielectric material 111 with low K value filled by a spin-on process or a CVD process. Preferably, the dielectric material becomes 111 low K value, which is in the form of a liquid, under pressure into the etched semiconductor structure 100 ' brought in. In this way, the dielectric material penetrates 111 low K value through almost all etched areas of the semiconductor structure 100 ' down to about the first dielectric layer 110a ' , In this procedure, the etched areas of the semiconductor structure 100 ' with the dielectric material 111 be filled with low K value so that essentially all existing free areas with the material 111 be filled with low K value. However, it will be understood by one skilled in the art that the dielectric material 111 with low K value depending on the required mechanical strength of the semiconductor structure 100 ' and the low K dielectric material into the semiconductor structure 100 ' can be introduced that after the filling process still remain some free areas. In one aspect, the etched semiconductor structure 100 ' For example, be filled so that substantially the upper dielectric layers with the dielectric material 111 be filled with low K value, while the lower dielectric layers remain almost free.
  • After the introduction of the dielectric material 111 with low K value, as in 1F-2 is shown, the etched-off dielectric semiconductor structure 100 '' low K value according to an embodiment of the present invention having a passivation capping layer 118 ' covered. As shown, the passivation capping layer functions 118 ' both as a sealing passivation layer and as a cover. As has been explained form the passivation topcoat 118 ' , the first to seventh dielectric layer 110a ' - 110g ' and the substrate 102 a semiconductor structure 100 '' with high structural integrity with low capacitive delay.
  • Although the sacrificial layers 110a - 110g In these embodiments, it has been understood by those skilled in the art that any material inert to copper, with the mechanical strength required during the manufacturing process, may be used to form the sacrificial layers. It should be noted that the function of the sacrificial layers is to provide good mechanical support during fabrication of the multilayer interconnect structures. This mechanical support is required so that the connection structures can withstand the structural stresses and pressures that occur during the CMP process or other operations.
  • It will be up now 2 Reference is made to a flow chart 200 5 shows the process steps that are performed in accordance with one embodiment of the present invention to produce a semiconductor structure with an air dielectric having multiple metallized leads and trunnions of copper. The procedure begins at step 202 in which an active region substrate is provided. After that, in step 204 Shallow trench isolation zones formed in the substrate, followed by the step 206 follows, are formed in the transistor structures in the active regions.
  • If the transistors have been formed, the process goes to step 208 in which the ILD is formed over the surface of the substrate. After that, in step 210 Contact studs of tungsten are formed in the ILD to make direct accesses between the metallized leads and the transistors. The formation of tungsten contact studs requires the application of tungsten to both the surface of the ILD and the vias to form tungsten tabs. Accordingly, the tungsten overlying the ILD surface becomes the subsequent step 212 planarized to remove the excess tungsten. This step is followed by step 214 in that a passivation layer is formed over the ILD to protect the active components of the substrate from contaminants.
  • At this point, the procedure goes to step 216 in which a sacrificial layer is formed over the previously formed layer. After that, in step 218 Holes formed for vias and trenches in the sacrificial layer. Preferably, this is done by a via-first, trench-first or buried-via double damascene process. After Formation of holes for vias and trenches will be in step 220 Pit holes formed in the sacrificial layer, so that the multilayer semiconductor structure is supported. In this way, the trunnions are formed in each sacrificial layer, thus providing support for a subsequently formed passivation capping layer. In some cases, the pin holes may be formed simultaneously with the holes for the vias.
  • After the formation of holes for vias, trenches and peg holes, copper will step in 222 applied to the surface of the sacrificial layer and in the holes for vias, trenches and mortise holes so that the trenches, holes for vias and mortise holes are filled. When copper is introduced into the holes for vias, trenches, and pin holes, excess copper remains on the surface of the sacrificial layer. Accordingly, the excess copper in step 224 is planarized, and the surface of the substrate is cleaned, whereby all remaining on the surface of the substrate impurities are removed. Preferably, the excess copper is planarized by a chemical mechanical planarization (CMP) process. It is important to note that the bond structure is very stable during the CMP process because the sacrificial material is still present.
  • After that, the procedure goes to step 226 in which it is determined whether additional metallized lines must be formed. If it is determined that additional metallized lines are required, the method returns to step 216 back, in which a sacrificial layer is formed over the previously formed layer. Conversely, if it is determined that there is no need for the formation of additional metallized lines, the method goes to step 228 in which the sacrificial layers, which are not protected by the passivation layer, are etched away and removed. Removal of the sacrificial material is achieved by applying a mixture of HF and deionized water to the multilayer semiconductor structure. Finally, the procedure goes to step 230 in which a passivation capping layer is formed over the last copper-metallized layers, thereby completing the manufacturing process.
  • Another embodiment of the present invention will become apparent from the flowchart 300 from 3 understandable, which is a flow chart 300 5 shows the process steps involved in fabricating a semiconductor structure according to an embodiment of the present invention with metallized copper lines and a low K porous dielectric. This procedure starts at step 302 in which an active region substrate is provided. After that, in step 304 Shallow trench isolation zones formed in the substrate, followed by the step 306 follows, are formed in the transistor structures in the active regions. When the transistor structures have been formed, the ILD in step 308 formed over the surface of the substrate, followed by the formation of contact pins of tungsten in the ILD in step 310 , Thereafter, the excess tungsten overlying the ILD surface is planarized. This step is followed by step 314 in that a passivation layer is formed over the ILD to protect the active components of the substrate.
  • After forming the passivation layer, a sacrificial layer becomes in step 316 formed over the previously formed layer, followed by the formation of vias and trench vias in the sacrificial layer in step 318 , After that, copper is in step 320 applied to the surface of the sacrificial layer, filling the trenches and holes for the vias. In step 322 Subsequently, a planarization and cleaning process is carried out to remove excess copper and impurities from the surface of the substrate.
  • When proceeding with step 324 it is determined whether additional metallized lines must be formed. If it is determined that an additional metallized line is needed, the method goes to step 316 further. Alternatively, the procedure goes to step 326 in which sacrificial layers not protected by the passivation layer are etched away and removed. Removal of the sacrificial layers is achieved by applying a mixture of HF and deionized water or any other chemical capable of dissolving the sacrificial layers down to the multilayer semiconductor structure. After that, the sacrificial layers are in step 328 replaced by porous low-K dielectric material. Finally, a passivation topcoat is added in step 330 formed over the last copper-metallized layer, whereby the manufacturing process is completed.
  • It should be re-noted that the connection structure during each single CMP process is mechanically stable, since the dense sacrificial material still exists. If there is no need for further CMP operations, the sacrificial material is removed. After removing the connection structure be filled with the low-K dielectric materials or released as an air dielectric. The dielectric with low K value or the air thus creating faster integrated Circuit elements.
  • Although the present invention has been described in some detail for the purposes of clarity of understanding, it will be obvious certain changes and modifications can be made within the scope of the appended claims. For example, the embodiments described herein are directed primarily to the fabrication of semiconductor structures with metallized copper leads; however, it is to be understood that the fabrication methods of the present invention are also well suited to the fabrication of semiconductor structures having a different type of metallized lead (eg, aluminum, tungsten, and other metals or alloys). Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given therein, but modifications and substitutions may be made within the scope of the appended claims.

Claims (17)

  1. Semiconductor device comprising: a substrate ( 102 ) with transistor devices; A plurality of metallized connecting lines ( 115 ) and conductive vias ( 112 ) formed in each of a plurality of connection planes of the semiconductor device, the plurality of metallized connection lines ( 115 ) and conductive vias ( 112 ) are isolated from each other by an air dielectric; - several trunnions ( 125 ), each of the plurality of trunnions ( 125 ) is formed so as to form a support pillar extending through the plurality of connection planes of the semiconductor device; and characterized in that the metallized connection lines and conductive vias are made of copper and that the plurality of support pins ( 125 ) with the plurality of metallized connecting lines ( 115 ) and conductive vias ( 112 ) are not electrically connected to copper.
  2. A semiconductor device according to claim 1, wherein said plurality of metallized interconnection lines ( 115 ) and conductive vias ( 112 ) made of copper double damascene structures.
  3. A semiconductor device according to claim 1, further comprising: - a passivation layer ( 118 ) located above a topmost layer of the metallized interconnecting lines ( 115 ) and conductive vias ( 112 ) is formed of copper.
  4. A semiconductor device according to claim 3, wherein the plurality of trunnions ( 125 ) also the passivation layer ( 118 ) wear.
  5. Semiconductor device comprising: - a substrate ( 102 ) with transistor devices; A plurality of metallized connecting lines ( 115 ) and conductive vias ( 112 ) in each of several connection levels ( 110 ) of the semiconductor device, wherein the plurality of metallized connecting lines ( 115 ) and conductive vias ( 112 ) of copper by a dielectric material ( 111 ) are isolated from each other; - several trunnions ( 125 ), each of the plurality of trunnions ( 125 ) is formed so that it forms a support column which extends through the plurality of connection levels ( 110 ) of the semiconductor device; and characterized in that the dielectric material is a porous dielectric material, and that the metallized interconnection lines and conductive vias are made of copper, and that the plurality of trunnions ( 125 ) with the plurality of metallized connecting lines ( 115 ) and conductive vias ( 112 ) are not electrically connected to copper.
  6. A semiconductor device according to claim 5, further comprising: - a passivation layer ( 118 ) located above a topmost layer of the metallized interconnecting lines ( 115 ) and conductive vias ( 112 ) is formed of copper.
  7. A method of manufacturing a semiconductor device, comprising: - forming transistor structures on a substrate ( 102 ); Forming multi-level metallized interconnect structures, wherein forming the metallized interconnect structures comprises: depositing a sacrificial layer ( 110 ); Performing a double damascene process to create trenches ( 114 ) and vias ( 112 ), and - filling and planarizing the trenches ( 114 ) and vias ( 112 ); - etching away the sacrificial layer ( 110 ) in all of the multiple levels of metallized interconnect structures, wherein the etch leaves a free metallized interconnect structure, and - filling the free metallized interconnect structure with either a porous dielectric material only ( 111 ) or with a mixture of a porous dielectric material ( 111 and a gaseous dielectric, wherein the fill forms a porous dielectric metallized interconnect structure having a low K dielectric constant.
  8. A method of manufacturing a semiconductor device according to claim 7, further comprising: - forming a passivation layer ( 118 ) on the filled free metallized connection structure.
  9. Method for producing a semiconductor device according to claim 7, in which the sacrificial layer ( 110 ) is a dielectric.
  10. A method of manufacturing a semiconductor device according to claim 9, wherein the dielectric is silicon dioxide (SiO 2 ).
  11. A method of manufacturing a semiconductor device according to claim 7, wherein said etching comprises - the sacrificial layer ( 110 ) is exposed to a wet etchant.
  12. Method for producing a semiconductor device according to claim 11, wherein the wet etchant comprises a mixture of Hydrofluoric acid (HF) and deionized water (DI water).
  13. A method of manufacturing a semiconductor device, comprising: - forming transistor structures on a substrate ( 102 ); Forming multi-level metallized interconnect structures, wherein forming the metallized interconnect structures comprises: depositing a sacrificial layer ( 110 ); Performing a double damascene process to create trenches ( 114 ), Vias ( 112 ) and cones ( 125 ), and - filling and planarizing the trenches ( 114 ), Vias ( 112 ) and cones ( 125 ); - etching away the sacrificial layer ( 110 ) in all of the multiple levels of metallized interconnect structures, wherein the etch comprises a free metallized interconnect structure and trunnions ( 125 ) leaves, wherein the trunnions ( 125 ) with the trenches ( 114 ) and vias ( 112 ) are not electrically connected and form a support column which extends through the plurality of planes of the free metallized connection structure.
  14. A method of manufacturing a semiconductor device according to claim 13, further comprising: a. Forming a passivation layer ( 118 ) on the free metallized connection structure and the trunnions ( 125 ).
  15. Method for producing a semiconductor device according to claim 14, wherein the free metallized connection structure as a dielectric either air or nitrogen or neon or argon used.
  16. A method of manufacturing a semiconductor device according to claim 13, wherein said etching comprises: - that said sacrificial layer ( 110 ) is exposed to a wet etchant.
  17. Method for producing a semiconductor device according to claim 16, wherein the wet etchant comprises at least one mixture from hydrofluoric acid (HF) and deionized water (DI water).
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