JPH05121369A - Method of etching contact hole of semiconductor device - Google Patents

Abstract

PURPOSE:To maintain the selection ratio on a conductive film, and prevent the contact hole from being tapered, and get enough large contact resistance, in etching of the contact hole. CONSTITUTION:A method of etching contact holes of a semiconductor device is provided for opening a deep hole 5b with a large diameter and a shallow hole 6b with a small diameter at the same time. And in plasma generation, microloading effect is produced by elevating the pressure, lowering the high frequency power, and lowering the total flow rate of gas, and raising the temperatures of the upper electrode and the inwall of the chamber, and lowering the temperature of the lower electrode, and raising the CHF3/CF4 ratio, and the high selection ratio of a silicon oxide insulating film 2 to a conductive film 3 is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of opening contact holes for connecting wiring layers in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art In semiconductor devices, particularly VLSI typified by DRAM, the aspect ratio of contact holes tends to become larger because the reduction ratio in the film thickness direction is smaller than the reduction ratio in the horizontal direction for each generation. It is in. In addition, the cell structure also has a three-dimensional structure such as a stacked type in order to increase the capacitance, so that the thickness of the interlayer insulating film also varies. Under such a circumstance, the deepest contact hole and the shallowest contact hole may have a depth of 4 to 5 times, and when these holes are simultaneously opened, the bottom of the hole in the deeper contact hole is the substrate. 400 to 500% on the underlying gate film (polysilicon, tungsten silicide, etc.) where the shallower contact hole falls while reaching
Therefore, the interlayer insulating film is required to have a high selection ratio with respect to the gate film. In order to etch with such a high selection ratio, the process of changing the gas composition, etching by devising the pressure and power, or opening the shallow contact hole and the deep contact hole in separate steps Is used.

[0003]

However, when etching is performed under process conditions in which a deposition reaction is likely to occur on the gate film in order to obtain a high selection ratio, the etching rate of the silicon oxide type interlayer insulating film is lowered. Alternatively, the side wall becomes tapered with a large pattern size, the hole bottom area decreases, and the contact resistance increases.

On the contrary, if a deep hole is vertically opened without a size change so that etching is performed under a low pressure condition, the underlying conductive film of the shallow hole will penetrate before the deep hole is opened. .. Further, in the method of etching a deep hole and a shallow hole in separate steps, the etching step needs to be performed at least twice, which is complicated and long. The above problems existed.

According to the present invention, when holes having different depths are formed in one etching process, if the selectivity ratio on the conductive film is to be obtained, the holes have a forward tapered shape and the bottom of the contact hole is formed. The area is reduced, the contact resistance is increased, and the problem of penetrating the conductive film when trying to open a deep contact hole without size change is eliminated, and the selectivity ratio on the conductive film is maintained. In addition, it is an object of the present invention to provide a contact hole etching method for a semiconductor device in which the contact hole does not have a tapered shape and a sufficient contact resistance can be obtained.

[0006]

In order to achieve the above object, the present invention relates to a method of etching a contact hole of a semiconductor device, in which a hole having a large hole diameter and a deep hole and a hole having a small hole diameter and a shallow hole are simultaneously opened. By increasing the pressure, lowering the high frequency power, lowering the total flow rate of gas, raising the temperature of the upper electrode and the inner wall of the chamber, lowering the temperature of the lower electrode, and raising the CHF ₃ / CF ₄ gas ratio, The microloading effect is generated and a high selection ratio between the silicon oxide-based interlayer insulating film and the conductive film is obtained.

[0007]

According to the present invention, as described above, in the step of simultaneously opening a deep hole having a large hole diameter and a shallow hole having a small hole diameter, the etching rate is reduced as the hole diameter is reduced by etching under a high pressure condition. By using the microloading effect, the underlying conductive film of the shallow hole is etched until the deep hole is opened to prevent the conductive film of the shallow hole from penetrating. it can. Further, since the selection ratio on the conductive film is high, it does not become a tapered shape.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view of a contact hole etching process of a semiconductor device showing an embodiment of the present invention. First, as shown in FIG. 1A, a silicon oxide insulating film 2 is formed on a Si substrate 1, and a conductive film 3 (eg, upper layer WSix 0.13 μm, lower layer n ⁺ poly) is formed on a part of the insulating film 2. Silicon 0.12 μm, that is, d ₂ is 0.
25 μm) is formed, and a photoresist 4 is applied in order to etch contact holes (d ₁ is 2.0 μm and d ₃ is 0.6 μm) having different depths.

Next, as shown in FIG. 1B, the hole diameter is increased by etching (for example, d ₄ is 1.2 μm).
The hole 5 and the hole diameter are small (for example, d ₅ is 0.7 μm).
m) Pattern the holes 6. Next, as shown in FIG. 1C, ordinary dry etching is performed, for example, by using a parallel plate discharge type plasma processing apparatus, and as shown in FIG. , As shown in FIG. That is, in the cases shown in FIG.
r, high frequency power 500W, Ar gas 800SCCM,
CHF ₃ gas 80 SCCM, CF ₄ gas 80 SCCM,
He back pressure for cooling of 7.5 Torr, electrode inner wall temperature of upper electrode 20 ° C., lower electrode −10 ° C., chamber inner wall temperature of 4
At 0 ° C., the selection ratio to the conductive film is 10 for WSix and 5.0 for n ⁺ polysilicon. In the case of, the pressure is 1.7 Torr.
r, high frequency power 700 W, Ar gas 800 SCCM,
CHF ₃ gas 80 SCCM, CF ₄ gas 80 SCCM,
He back pressure for cooling of 7.5 Torr, electrode inner wall temperature of upper electrode 20 ° C., lower electrode −10 ° C., chamber inner wall temperature of 4
At 0 ° C., the selection ratio to the conductive film is 13 for WSix and 7.0 for n ⁺ polysilicon. In the case of, the pressure is 1.0 Torr.
r, high frequency power 700 W, Ar gas 400 SCCM,
CHF ₃ gas 40 SCCM, CF ₄ gas 40 SCCM,
He back pressure for cooling 15.0 Torr, electrode inner wall temperature was 25 ° C. for the upper electrode, -20 ° C. for the lower electrode, chamber inner wall temperature was 50 ° C., selection ratio to the conductive film was 16 for WSix, and 8.0 for n ⁺ polysilicon. If yes, the pressure is 1.0 Tor
r, high frequency power 700 W, Ar gas 800 SCCM,
CHF ₃ gas 100 SCCM, CF ₄ gas 60 SCC
M, cooling He back pressure of 15.0 Torr, electrode inner wall temperature of upper electrode 25 ° C., lower electrode −20 ° C., chamber inner wall temperature of 50 ° C., selection ratio of conductive film to WSix 13 and n ⁺ polysilicon 7. It is 0.

In FIGS. 3A to 3C, the hole diameter (μm) is shown on the horizontal axis and the normalized etch rate is shown on the vertical axis, and the etching film is a silicon oxide insulating film (B ₂ O).
₃ / P ₂ O ₅ = 13/14 wt%, 900 ° C. flow),
The etching time was 90 seconds, and the etching rate of 0.5 to 0.9 μm diameter was shown on the vertical axis when the etching rate of 1.2 μm diameter was 1.0. 3 to FIG.
Corresponds to each of.

When the holes are etched under the above-mentioned generation conditions, the holes 6a having a small hole diameter,
A microloading effect that the etching rate decreases by about 6b occurs, and the etching rate of the silicon oxide insulating film 2 is 13 to 15% in 90 seconds in the case of a hole having a hole diameter of 0.7 μm as compared with the case of a hole having a diameter of 1.2 μm. Is reduced. In the above cases and, by increasing the pressure or lowering the high frequency power, respectively, the direction of the ions incident on the etching surface is made as vertical as possible to prevent the microloading effect. ing. In the above and above, the electrode temperature is increased in the upper part and decreased in the lower part, respectively. In addition, a microloading effect is generated by using a gas composition that easily causes a deposition reaction. Here, 5a and 5b are holes having a large hole diameter.

From the above conditions (1) to (4), for example, using the conditions of (1) and (2), a hole having a hole diameter of 1.2 μm and a depth of 2.0 μm and a hole having a hole diameter of 0.7 μm and a depth of 0.6 μm are simultaneously opened. The etching rate in the hole is 1.2
9300Å / min for μm diameter, 7900 for 0.7μm diameter
It becomes Å / min, and when the shallow hole is etched by 0.6 μm and the bottom surface of the hole just reaches the surface of the conductive film (the required time is 45 seconds), the deep hole has already been etched by 7,000 Å.

Further, as shown in FIG. 2, under this plasma generation condition, WSix of the silicon oxide type interlayer insulating film is formed.
(Tungsten silicide, conductive film upper layer 0.1 μm)
As shown in FIG. 1D, in order to completely open the deeper hole 5b having a larger hole diameter, the hole 6b having a smaller hole diameter is not removed even if the etching is further performed by 1.3 μm. The conductive film 3 to be opened is reduced by 0.1 μm, and the conductive film 3 is not penetrated.

Therefore, under this plasma generation condition,
By using the microloading effect and high selection ratio,
A deep hole and a shallow hole can be simultaneously formed without penetrating the conductive film, and similar results can be obtained under the above conditions. The present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0015]

As described above in detail, according to the present invention, even if the contact holes having different depths are simultaneously opened, the microloading effect that the etching rate decreases as the hole diameter decreases can be obtained. Since the conductive film is exposed to plasma until the deep holes are completely opened, the time during which etching is performed can be significantly shortened, and it is difficult for the conductive film in shallow holes to be thinned or penetrated. Resistance stabilizes. In addition, since the etching rate of deep holes is high, the total etching time is shortened.

Therefore, the manufacturing yield, reliability, throughput and the like of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a contact hole etching process of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a diagram showing a plasma generation condition and a selection ratio of a silicon oxide insulating film to a conductive film according to an embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a hole diameter and a standardized etch rate showing an example of the present invention.

[Explanation of symbols]

 1 Si substrate 2 Silicon oxide type insulating film 3 Conductive film 4 Photoresist 5, 5a, 5b, 6, 6a, 6b Hole

Claims (5)

[Claims] 1. A contact hole etching method for a semiconductor device in which a hole having a large hole diameter and a deep hole and a hole having a small hole diameter and a shallow hole are simultaneously opened. In plasma generation, the pressure is increased, the high frequency power is decreased, and the total gas flow rate is reduced. C, lowering the temperature of the upper electrode and the inner wall of the chamber and lowering the temperature of the lower electrode,
A method for etching a contact hole of a semiconductor device, which comprises increasing a HF ₃ / CF ₄ gas ratio to generate a microloading effect and obtaining a high selection ratio between a silicon oxide-based interlayer insulating film and a conductive film. 2. The method of etching a contact hole of a semiconductor device according to claim 1, wherein the pressure is 1.0 To.
rr, high frequency power 500W, Ar gas 800SC
CM, CHF ₃ gas 80 SCCM, CF ₄ gas 80
SCCM, cooling He back pressure of 7.5 Torr, electrode inner wall temperature of upper electrode 20 ° C., lower electrode temperature −10 ° C., chamber inner wall temperature 40 ° C., conductive film selection ratio to WSix of 1
A method for etching a contact hole of a semiconductor device in which 0, n ⁺ polysilicon is 5.0. 3. The contact hole etching method for a semiconductor device according to claim 1, wherein the pressure is 1.7 To.
rr, high frequency power 700 W, Ar gas 800 SC
CM, CHF ₃ gas 80 SCCM, CF ₄ gas 80
SCCM, cooling He back pressure of 7.5 Torr, electrode inner wall temperature of upper electrode 20 ° C., lower electrode temperature −10 ° C., chamber inner wall temperature 40 ° C., conductive film selection ratio to WSix of 1
3, a method of etching a contact hole of a semiconductor device in which n ⁺ polysilicon is 7.0. 4. The method of etching a contact hole of a semiconductor device according to claim 1, wherein the pressure is 1.0 To.
rr, high frequency power 700 W, Ar gas 400 SC
CM, CHF ₃ gas 40 SCCM, CF ₄ gas 40
SCCM, He back pressure for cooling is 15.0 Torr, electrode inner wall temperature is upper electrode temperature 25 ° C, lower electrode temperature -20 ° C,
Chamber inner wall temperature 50 ° C, selection ratio of conductive film to WSix
16. The method for etching a contact hole of a semiconductor device, wherein the etching temperature is 16, and the n ⁺ polysilicon is 8.0. 5. The method of etching a contact hole of a semiconductor device according to claim 1, wherein the pressure is 1.0 Torr.
r, high frequency power 700 W, Ar gas 800 SCC
M, CHF ₃ gas 100 SCCM, CF ₄ gas 60
SCCM, He back pressure for cooling is 15.0 Torr, electrode inner wall temperature is upper electrode 25 ° C., lower electrode −20 ° C., chamber inner wall temperature 50 ° C., conductive film selection ratio is 13 for WSix,
A method for etching a contact hole of a semiconductor device, in which n ⁺ polysilicon is 7.0.