JPS62180452A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To shorten the receiving time of data by transferring only the graph data part excluding a blank part in case the lateral length of the graph data is less than a printable area. CONSTITUTION:In case the graph data is transferred, the graph data receiving area F of a memory 203 is cleared previously to zero. While a lower processor 201 sets a graph data reception start address A2 to a DMA control part 202 as a reception address of the graph data together with the lateral byte number l1 of the graph data as the reception byte number respectively. Then the data on a hatched part E is loaded to a memory 203 after a split DMA flag 208 and then a DMA start flag 207 are set. The part 202 receives data equivalent to a line and produces an interruption to the processor 201 by the DMA end report interruption signal (t) as long as the flag 208 is set.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data transfer circuit between processing devices. In particular, when data divided into a plurality of blocks is transferred by DMA at once, each block is transferred at a transfer destination. relates to a data transfer circuit that can receive data into different memory areas.

[Background of the invention]

As described in Japanese Patent Application Laid-Open No. 59-62960, there is a method to start data transfer by specifying the transfer direction, transfer memory start address, and number of transfer bytes, and to notify the end of data transfer by an interrupt. It is being According to this method, the memory area that can be used for data transfer is fixed, so unless the receiving side transfers the transferred data to a memory area other than the data transfer area or the transferred data becomes unnecessary, the next data can be transferred. cannot be transferred. Further, when transferring data divided into a plurality of pieces, there is a problem that transfer activation is required for the number of times of division.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problem and provide a data transfer circuit that can transfer data divided into a plurality of parts to a plurality of memory areas of a transfer destination without increasing the overhead of the transfer source. There is a particular thing.

[Summary of the invention]

is stored contiguously in the memory area of the transfer source, and the length of each divided data is known at the transfer destination. When the transfer source starts one data transfer, the data Data reception is activated in divided data length units at the transfer destination, thereby reducing overhead related to data transfer at the data transfer source.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 is a schematic block diagram of a printer control device;
When transferring graph data to the 7' II interface control device, the host processor 101 uses DMA to set the start address, number of transfer bytes, and transfer mode of the graph data on the memory 103.
When the graph data transfer request command is set in the control unit 102 and the command register 204, an interrupt is generated in the lower processor 201 by the command reception interrupt signal ω. Note that the printing paper width W1, printing surface width W2, left margin W3, graph data horizontal width W4,
It is assumed that the vertical width of the graph data W5 and the upper margin W6 are already known by the printer control device.

When a command reception interrupt occurs, the lower processor 201 reads the contents of the command register 204 and recognizes the glaze type of the received data. If the data to be transferred is graph data, the graph data receiving area F of memory 2o/3
Clear to zero in advance. Lower processor 20
1 is the graph data reception start address A2 shown in FIG. 4 as the graph data reception address, and the graph data horizontal byte number t1 is the reception byte number in the DMA control unit 20.
2, and after shading the divided DMA flag 20B, the fourth DMA start flag 207 is set.
The data in the shaded area E shown in the figure is loaded into the memory 203. The DMA control unit 202 receives one row of data, and if the divided DMA flag is set, generates an interrupt to the lower processor 201 using a DMA end report interrupt signal l. When a DMA end interrupt occurs, the lower processor sets the graph data reception start address A2 shown in FIG.
Set in the MA control unit 202. After receiving only the graph data D necessary for printout in the graph data reception area F through the above sequence, the print control unit 212 prints out the graph data to the printer device 213 .

〔Effect of the invention〕

According to the present invention, when printing out graph data, if the data length in the horizontal direction of the graph data is smaller than the printable area, only the graph data portion is transferred, excluding the margin portion.) Data reception time It is possible to shorten the time and improve printing performance.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a printer control unit according to an embodiment of the present invention, and FIG. 2 is a diagram of a lower processor and an upper processor.
-IA transfer sequence diagram, FIG. 3 is an explanatory diagram of an example of outputting graph data onto printer paper, and FIG. 4 is an explanatory diagram of the graph data receiving area of the memory in the lower processor. DESCRIPTION OF SYMBOLS 101... Upper processor, 103... Upper processor memory, 201... Lower processor, 204... Command register, 207... DMA start flag, 208... Division DMA flag, 209... DMA OR gate for end interrupt, 210...
- AND gate for normal mode DMA end interrupt, 211...AND gate for split mode DMA end interrupt, 212...print control unit, 213...printer device.

Claims (1)

[Claims] 1. In a data processing system that has at least two processing devices, a program for the processing devices, a memory for storing data, and a DMA controller for controlling data transfer between the processing devices, data divided into multiple blocks can be DMAed at once. A data transfer circuit characterized in that when data is transferred, data can be received in different memory areas for each block at the transfer destination.