JPS6217867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MOS type semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device in which an element isolation process is improved.

As is well known, in semiconductor devices, a process of forming field regions for separating element regions of a semiconductor substrate is performed. In particular, with the recent increase in density and integration of semiconductor devices, there is a demand for the establishment of techniques for miniaturizing field regions.

Incidentally, a selective oxidation method is generally employed as a conventional device isolation method, but it has the disadvantage that the field oxide film digs into the device region, resulting in so-called bird peaks and the like, making it unsuitable for miniaturization.

For these reasons, the applicant proposed an element isolation method suitable for miniaturization technology. This is the MOS
A description will be given below using a transistor as an example with reference to FIGS. 1a to 1f.

(i) First, as shown in FIG. 1a, a high-resistance p ^- type silicon substrate 1 is thermally oxidized in a wet oxygen atmosphere at 1000°C to form a thermal oxide film 2 with a thickness of, for example, 5000 Å.
After growing the (insulating film), a photoresist film is applied to the entire surface, and a resist pattern 3 covering the element region is formed by photolithography.

(ii) Next, using the resist pattern 3 as a mask, boron, which is an impurity for preventing field inversion, is selectively ion-implanted into the substrate 1 through the thermal oxide film 2 at an acceleration voltage of 200 keV and a dose of 1×10 ¹³ /cm ^{2 .} After forming the p ⁺ -type anti-inversion layer 4, an Al film with a thickness of 2000 Å is vacuum-deposited over the entire surface. At this time, as shown in FIG. 1b, the resist pattern 3
Al coating 5 ₁ on top and Al coating 5 ₂ on thermal oxide film 2
It is separated into Subsequently, the resist pattern 3 is removed, the Al film ₅₁ on it is lifted off, and a layer is placed on the thermal oxide film 2 in the planned element isolation region.
The Al coating ₅₂ is left (as shown in FIG. 1c).

(iii) Next, using the remaining Al film ₅₂ as a mask, the thermal oxide film 2 is selectively etched by a reactive ion etching method to form a field oxide film (element isolation region) 6, and then the remaining Al film _{52 is} selectively etched.
was removed (as shown in Figure 1d).

(v) Next, the exposed substrate 1 is subjected to thermal oxidation treatment.
After growing an oxide film with a thickness of 400 Å to serve as a gate oxide film on the surface and further depositing a 4000 Å thick phosphorus-doped polycrystalline silicon film on the entire surface, patterning is performed by reactive ion etching to form the gate electrode 7. Then, using the same electrode 7 as a mask, the oxide film is etched to form a gate oxide film 8 (as shown in FIG. 1e). Next, arsenic is diffused into the silicon substrate 1 using the gate electrode 7 and the field oxide film 5 as a mask ^.
forming source and drain regions 9 and 10 of the mold;
Furthermore, after depositing a CVD-SiO ₂ film 11 on the entire surface and opening a contact hole, Al wirings 12 and 13 are formed by vapor deposition and patterning of an Al film to manufacture a MOS type semiconductor device (as shown in Fig. 1 f). ).

However, the above-mentioned method had the following drawbacks. That is, after forming the field oxide film 6, a thermal oxide film 14 is grown, a phosphorus-doped polycrystalline silicon film 15 is deposited, and a resist film 1 is grown.
2a, the resist film 16 becomes thicker at the shoulder portion of the polycrystalline silicon film 15 corresponding to the edge A of the field oxide film 6 than at other portions. As a result, when the exposed resist film 16 is developed, resist residue 16' is likely to be formed at the end of the field oxide film 6 as shown in FIG. Development must be performed, making it difficult to control the dimensions of the resist pattern. Also,
After forming the field oxide film 6, a thermal oxide film 14 is grown and a phosphorus-doped polycrystalline silicon film ₁₅ is deposited. As shown in FIG. The film thickness t ₂ at the stepped portion at the end of the field oxide film 6 is approximately 9000 Å. For this reason, when the polycrystalline silicon film 15 is etched by reactive ion etching for the purpose of miniaturizing the gate electrode to be formed, the etching progresses only from the surface downward.
As shown in FIG. 3B, etching residues 17 of polycrystalline silicon are formed in the stepped portions, and when one MOS transistor is formed in one element region, a short circuit occurs between the gate, source, and drain. Here, when a plurality of MOS transistors are formed in one element region, the etching residue causes a short circuit between the gate electrodes.

Furthermore, after forming the field oxide film 6, CVD-
After depositing the SiO ₂ film 11 and forming the Al wirings 12 and 13, the field oxide film 6 is formed as shown in FIG.
Al wiring 1 at the shoulder 18 of the steep step at the end
There is a drawback that 2 and 13 tend to be cut off easily.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and it is possible to form a miniaturized element isolation region with a simple process, and also to remove resist residue, polycrystalline silicon film, etc. near the edge of the element isolation region. Prevents etching residue and breakage of Al wiring, providing high performance.
The present invention aims to provide a method for manufacturing highly integrated and highly reliable MOS type semiconductor devices.

That is, the present invention includes a step of forming an insulating film on a semiconductor substrate of one conductivity type, and then forming a mask pattern covering a planned device area on the insulating film, and using this mask pattern as a shielding material to cover the device of the substrate. a step of ion-implanting impurities into the separation region to form an anti-inversion layer of the same conductivity type as the substrate; and depositing a film on the insulating film including the mask pattern, and then removing the mask pattern and forming a film on it. a step of selectively lifting off a portion of the insulating film to leave a film on a portion of the insulating film intended for an element isolation region; and a step of selectively etching away the insulating film using the remaining film as a mask to form an element isolation region. , after depositing the non-single-crystal semiconductor layer, irradiating the non-single-crystal semiconductor layer with an energy beam to make it into a single crystal, and selectively etching the single-crystal semiconductor layer to form a single-crystal semiconductor of the same conductivity type as the substrate. The present invention is characterized by comprising a step of forming an element region on the base between the element isolation regions, and a step of forming a MOS transistor in the element region.

Examples of the semiconductor used in the present invention include a p-type or n-type silicon or other semiconductor substrate, or a structure in which a single crystal semiconductor film is provided on the substrate.

The insulating film in the present invention is used to form element isolation regions. Such insulating films include, for example, thermal oxide films, CVD-SiO ₂ films, silicon nitride films,
Examples include an alumina film.

The mask pattern in the present invention functions as an ion implantation mask for impurities for preventing inversion, and
It acts as a lift-off material for leaving the film on the intended element isolation region of the insulating film. Therefore, the material of the mask pattern needs to have selective etching properties with respect to the insulating film and the coating. Examples of the material for such a mask pattern include resist and the like.

In the present invention, since the impurity for preventing inversion is doped into the semiconductor substrate through the insulating film, it is necessary to employ an ion implantation method. It is desirable that such ion implantation conditions be appropriately selected depending on the type, thickness, etc. of the insulating film.

The film in the present invention is patterned by lift-off by removing the mask pattern, and the film pattern (residual film) formed by patterning is used as an etching mask for the insulating film, so that it can be used for both the mask pattern and the insulating film. It is necessary to have selective etching properties. Examples of materials for such a coating include:
Al or Al alloys such as Al-Si, Al-Cu-Si,
Alternatively, other metals such as Mo, W, and Ni can be used.

The non-single crystal semiconductor layer in the present invention is used as a starting material for an element region formed by energy beam irradiation and selective etching. Examples of such a non-single crystal semiconductor layer include a polycrystalline silicon layer, an amorphous silicon layer, and the like.

The energy beam irradiation in the present invention is performed to single-crystallize the non-single-crystal semiconductor layer using the crystallinity of the semiconductor substrate in contact with the non-single-crystal semiconductor layer as a nucleus. Examples of such energy beams include laser beams, electron beams, and the like.

In the present invention, the plasma nitride is deposited on the single crystal semiconductor layer in a recessed part of the single crystal semiconductor layer corresponding to the semiconductor substrate separated by the element isolation region. This is done to deposit a plasma nitride film, which has a slower etching rate than ion etching. When such a plasma nitride film is treated with reactive ion etching, parts of the plasma nitride film other than the recessed portions are selectively etched away, and are self-aligned with the edges of the element isolation region as etching masks for the single crystal semiconductor layer. A plasma nitride film can be formed.
Therefore, by etching the single crystal semiconductor layer using the plasma nitride film as a mask, an element region made of the single crystal semiconductor layer can be formed in a self-aligned manner with respect to the element isolation region.

Next, an example in which the present invention is applied to manufacturing a MOS type semiconductor device will be described with reference to the drawings.

Example [] First, a p-type silicon substrate 101 with a surface index (100) is thermally oxidized in a wet oxygen atmosphere at 1000°C to form a thermal oxide film (insulating film) 1 with a thickness of 5000 Å.
I grew 02. Subsequently, a photoresist film was applied to the entire surface, and a resist pattern (mask pattern) 103 was formed by photolithography to cover the intended element area (as shown in FIG. 5A). Subsequently, using the resist pattern 103 as a mask, boron, which is an impurity for preventing inversion, is applied at an accelerating voltage.
Ions are selectively implanted into the substrate 101 through the thermal oxide film 102 under the conditions of 200 keV and a dose of 1×10 ¹³ /cm ² and heat treated to form the p ⁺ type inversion prevention layer 104.
was formed (as shown in Figure 5b).

[] Next, an Al film with a thickness of 2000 Å was vacuum-deposited on the entire surface. At this time, as shown in FIG _.
The Al coating ₁₀₅₂ on the thermal oxide film 102 became discontinuous and separated. Next, the resist pattern 103 is removed and the Al coating 1 thereon is removed.
₀₅₁ was lifted off to leave an Al film 1052 on the thermal oxide film ₁₀₂ in the intended element isolation region (as shown in FIG. 5d). Subsequently, the thermal oxide film ₁₀₂ was selectively etched by reactive ion etching using the remaining Al film 1052 as a mask to form an element isolation region (field oxide film) 106. Thereafter, the remaining Al coating ₁₀₅₂ on the element isolation region 106 was removed (as shown in FIG. 5e).

[] Next, as shown in FIG. 5f, a polycrystalline silicon layer 107 having the same thickness as the element isolation region 106 was deposited over the entire surface. Subsequently, the entire surface of the polycrystalline silicon layer 107 is irradiated with a laser beam, and the silicon substrate 1 in contact with the polycrystalline silicon layer 107 is
After forming a p-type single crystal silicon layer 108 by single crystallizing 01 as a crystal nucleus, a plasma nitride film 109 was deposited on the single crystal silicon layer 108 (as shown in FIG. 5g). Subsequently, it was treated with reactive ion etching. At this time, as shown in FIG. 5h, the etching rate of the plasma nitride film portion deposited in the recessed portion of the single crystal silicon layer 108 is slower than that of the plasma nitride film portion deposited on the other flat single crystal silicon layer. The plasma nitride film 109' remained in a self-aligned manner only in the concave portion of the single crystal silicon layer 108. Thereafter, the single crystal silicon layer 108 is selectively etched using the remaining plasma nitride film 109' as a mask, and as shown in FIG. An element region 110 made of layers was formed.
Note that, prior to forming the source, drain regions, etc. described below, the element region 110 made of a single crystal silicon layer may be further doped with a p-type impurity such as boron for threshold control.

[] Next, element regions 110 made of p-type single crystal silicon separated by element isolation regions 106
was thermally oxidized to grow an oxide film with a thickness of 400 Å,
Furthermore, after depositing a phosphorus-doped polycrystalline silicon film with a thickness of 3000 Å over the entire surface, the polycrystalline silicon film is patterned by reactive ion etching using a resist pattern formed by photolithography as a mask to form a gate electrode 111. Then, using the same electrode 111 as a mask, the oxide film was selectively etched to form a gate oxide film 112. Next, using the gate electrode 111 and the element isolation region 106 as a mask, arsenic diffusion or arsenic ion implantation is performed to form n ⁺ -type source and drain regions 113 and 114 in the element region 110 made of p-type single crystal silicon. , even more fully
After depositing a CVD-SiO ₂ film 115 and opening a contact hole, an Al film is deposited and patterned to form gate lead-out Al wiring (not shown), source and drain lead-out Al wiring 116, 117.
A MOS type semiconductor device was manufactured by forming a MOS semiconductor device (as shown in FIG. 5J).

According to the present invention, the silicon substrate 1 is separated by the element isolation region 106 as shown in FIG.
It is possible to extremely easily form an element region 110 made of p-type single crystal silicon at approximately the same level as the surface of the region 106 in the 01 portion. In other words, the already mentioned Figure 1a~
Unlike the method shown in f, the element region 110 can be made flat with respect to the element isolation region 106 without creating a step between the element isolation region and the silicon substrate serving as the element region. Therefore, during the resist film coating and photolithography after the oxide film growth and phosphorus-doped polycrystalline silicon film deposition in the step [], it is possible to avoid the formation of resist residues at the edges of the element isolation region 106. Therefore, it becomes possible to form a resist pattern with good dimensional accuracy, and in turn, it is possible to form a highly accurate gate electrode 111. In addition, in the same [] step, when a phosphorus-doped polycrystalline silicon film is deposited and selectively etched by reactive ion etching using the resist pattern as a mask, the element isolation region 106 and the element region made of p-type single crystal silicon are removed. 110 are flattened at the same level, it is possible to prevent polycrystalline silicon from remaining etched in the element region 110 around the edge of the element isolation region 106. As a result, the gate electrode 111 and the source and drain regions 113,
It is possible to obtain a highly reliable MOS type semiconductor device free from short circuits with 114. Moreover, the same []
In the process, source and drain extraction Al wiring 1
16 and 117, the element isolation region 106
It is possible to prevent the Al wirings 116, 117 from being cut off at the ends.

Furthermore, in the process of forming element isolation regions, bird's beaks do not occur as in the case of selective oxidation.
It is possible to suppress the miniaturization of the element distribution region 106 and the size reduction of the element region 110, resulting in a highly integrated MOS.
type semiconductor device can be obtained.

Note that the present invention is not limited to the manufacture of MOS type semiconductor devices as in the above embodiments, but is also applicable to dynamic
It can be similarly applied to the manufacture of other MOS type semiconductor devices such as RAM and CMOS.

As described in detail above, according to the present invention, it is possible to form a fine element isolation region through a simple process, and furthermore, by forming an element region made of single crystal silicon at approximately the same level as the surface of the element isolation region, the element isolation region can be isolated. It is possible to prevent resist residues and etching residues of polycrystalline silicon (gate electrode material, etc.) around the edge of the region, as well as to prevent disconnection of Al wiring at the edge of the same element isolation region, resulting in high performance and high integration. Accordingly, it is possible to provide a method for manufacturing a MOS type semiconductor device that has high reliability at high temperatures.

[Brief explanation of the drawing]

FIGS. 1a to 1f are cross-sectional views showing the manufacturing process of a MOS type semiconductor device using a method already proposed by the applicant, and FIGS. The explained cross-sectional views, FIGS. 3a and 3b, are cross-sectional views illustrating the etching residue of polycrystalline silicon, which is another drawback of the above method, and FIG. 5th cross-sectional view illustrating the break in
Figures a to f are cross-sectional views showing the manufacturing process of a MOS type semiconductor device in an embodiment of the present invention. 101...p type silicon substrate, 102...thermal oxidation film (insulating film), 103...resist pattern (mask pattern), 104...p ⁺ type inversion prevention layer, 105 ₁ ,
105 ₂ ...Al coating, 106... Element isolation region, 1
07... Polycrystalline silicon layer (non-single crystal semiconductor layer),
108...p-type single crystal silicon layer, 109...plasma nitride film, 110...element region, 111...gate electrode, 113...n ⁺ type source region, 114...n ⁺ type drain region, 116, 117...Al wiring.

Claims (1)

[Claims] 1. After forming an insulating film on a semiconductor substrate of one conductivity type, forming a mask pattern covering a planned element region on the insulating film, and using this mask pattern as a shielding material to inject impurities into the element isolation region of the substrate. ion implantation to form an inversion prevention layer of the same conductivity type as the substrate; and after depositing a film on the insulating film including the mask pattern, the mask pattern is removed and the film portion thereon is selectively removed. a step of lifting off the insulating film to leave a film on the intended element isolation region of the insulating film; a step of selectively etching away the insulating film using the remaining film as a mask to form an element isolation region; After the semiconductor layer is deposited, the non-single crystal semiconductor layer is irradiated with an energy beam to become a single crystal, and the single crystal semiconductor layer is selectively etched to form an element region made of a single crystal semiconductor of the same conductivity type as the substrate. a step of forming on the substrate between the element isolation regions;
1. A method for manufacturing a MOS semiconductor device, comprising the step of forming a MOS transistor.