JPS62177978A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62177978A JPS62177978A JP61019409A JP1940986A JPS62177978A JP S62177978 A JPS62177978 A JP S62177978A JP 61019409 A JP61019409 A JP 61019409A JP 1940986 A JP1940986 A JP 1940986A JP S62177978 A JPS62177978 A JP S62177978A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- epitaxial layer
- type epitaxial
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims description 18
- 238000002955 isolation Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 239000008188 pellet Substances 0.000 abstract description 7
- 238000005219 brazing Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にダイオード２つをシリ
ーズに接続したシリーズダイオードにさらに２つのダイ
オード間の接続部より第３の端子を出す構成の３端子型
シリーズダイオードの半導体ベレットに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a configuration in which a series diode in which two diodes are connected in series is further provided with a third terminal from a connecting portion between the two diodes. This article relates to a three-terminal series diode semiconductor bullet.
通常、バイアス回路の温度補償用に第２図に示す３端子
型のシリーズダイオードが用いられている。従来この３
端子シリーズダイオードを構成するには、例えば第３図
に示す様にＮ型半導体１に形成されたＰ型拡散層からな
るシングルダイオードペレットを２つ用いパッケージ内
のリードフレーム上でボンディングワイヤー７により接
続してリードフレームＴ、、Ｔ、及びＴ、を３端子とす
るシリーズダイオードを構成していた。Usually, a three-terminal series diode shown in FIG. 2 is used for temperature compensation in a bias circuit. Conventionally these 3
To configure a terminal series diode, for example, as shown in Fig. 3, two single diode pellets consisting of a P-type diffusion layer formed in an N-type semiconductor 1 are connected by a bonding wire 7 on a lead frame inside the package. The lead frames T, , T, and T constituted a series diode with three terminals.
上述した従来の３端子型のシリーズダイオードは、シン
グルダイオードベレットを２つ使用し、パッケージ内部
でボンディングワイヤーにより配線を行う為、
（１）ペレットマウント工程を２回行わなければならな
い。The conventional three-terminal type series diode described above uses two single diode pellets, and wiring is performed inside the package using bonding wires, so (1) the pellet mounting process must be performed twice.
（２）ボンディング作業が不規則な形となる。(2) The bonding work results in an irregular shape.
等アッセンブリ作業を著しく悪化させる問題があった。There was a problem that significantly worsened the assembly work.
本発明の半導体装置は、アッセンブリ工程の作業性に鑑
み従来２つのベレットで構成していたシリーズダイオー
ドを１チツプ内に形成したものである。In the semiconductor device of the present invention, in view of the workability of the assembly process, a series diode, which was conventionally composed of two pellets, is formed in one chip.
本発明の半導体装置は、−導電型の半導体基体上に形成
された反対導電型の第１のエピタキシャル層と、第１の
エピタキシャル層を絶縁分離する第１拡散層と、該第１
のエピタキシャル層上に形成された反対導電型の第２の
エピタキシャル層と、該第２のエピタキシャル層を絶縁
分離する第２拡散層と、該第２エピタキシャル層内に表
面より形成された第３拡散層と、前記第２拡散層と前記
第２のエピタキシャル層とが同電位となる様に形成され
た金属電極層とを有することを特徴とする。A semiconductor device of the present invention includes: a first epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of a -conductivity type; a first diffusion layer for insulating and separating the first epitaxial layer;
a second epitaxial layer of opposite conductivity type formed on the epitaxial layer; a second diffusion layer for insulating and separating the second epitaxial layer; and a third diffusion layer formed from the surface within the second epitaxial layer. and a metal electrode layer formed so that the second diffusion layer and the second epitaxial layer have the same potential.
次に、本実間について図面を８照して説明する。 Next, the actual room will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。Ｐ型半導体
基体８にエピタキシャル法によりＮ型エピタキシャル層
を形成し、Ｐ型絶縁分離拡散層１゜により、Ｎ型エピタ
キシャル層９を絶縁分離させる。FIG. 1 is a sectional view of an embodiment of the present invention. An N-type epitaxial layer is formed on a P-type semiconductor substrate 8 by an epitaxial method, and an N-type epitaxial layer 9 is insulated and isolated by a P-type insulating isolation diffusion layer 1°.
さらにエピタキシャル法によりＰ型エピタキシャル層を
形成し、同様にＮ型絶縁分離拡散層１２によりＮ型エピ
タキシャル層９上にＰ型エピタキシャル層１１を絶縁分
離させる。次にＰ型エピタキシャル層１１内に所定の方
法によυＮ型拡散層１３を形成し、最後に金属！極層４
によりＮ型拡散層１３からの電極と、Ｐ型エピタキシャ
ル層１１及びＮ型絶縁分離拡散層１２を接続した電極と
を形成し、該半導体基体に構成されたベレットをロー材
６によりリードフレームＴ、上にマウントし、ボンディ
ングワイヤ７で金属電極層４をそれぞれリードフレーム
Ｔ、、’ｒ、にボンディングすることにより、３端子型
シリーズダイオードを構成する。Further, a P-type epitaxial layer is formed by an epitaxial method, and the P-type epitaxial layer 11 is similarly insulated and isolated on the N-type epitaxial layer 9 by an N-type insulating isolation diffusion layer 12. Next, a υN type diffusion layer 13 is formed in the P type epitaxial layer 11 by a predetermined method, and finally a metal! extreme layer 4
An electrode from the N-type diffusion layer 13 and an electrode connecting the P-type epitaxial layer 11 and the N-type insulating isolation diffusion layer 12 are formed, and the pellet formed on the semiconductor substrate is connected to a lead frame T, using a brazing material 6. A three-terminal series diode is constructed by mounting the metal electrode layer 4 on the top and bonding the metal electrode layer 4 to the lead frame T, ,'r, respectively using the bonding wire 7.
本実施例の説明はＰ型半導体基体に関する構造について
行ったが、極性を逆にした場合も同様にトｎ成できる。Although this embodiment has been described with respect to a structure related to a P-type semiconductor substrate, formation can be similarly performed even when the polarity is reversed.
以上説明した様に、本発明はシリーズ接続ダイオードを
１チツプ構成にすることにより、アッセンブリ工程での
マウント作業及びボンディング作業の効率を大幅に向上
できる効果がある。As explained above, the present invention has the effect of greatly improving the efficiency of mounting work and bonding work in the assembly process by forming series-connected diodes into a single chip configuration.
第１図は本発明の一実施例の１チツプシリーズダイオー
ドのボンディング後の断面図、第２図け３端子型シリー
ズダイオードの回路構成図、第３図は従来の２つのベレ
ットで構成したシリーズダイオードのボンディング後の
断面図である。
１・・・・・・Ｎ型半導体基体、２・・・・・・Ｐ型拡
散層、３・・・・・・絶縁膜、４・・・・・・金属電極
層、５・・・・・・裏面金属電極層、６・・・・・・ロ
ー材、７・・・・・・ボンディングワイヤ、８・・・・
・・Ｐ型半導体基体、９・・・・・・Ｎ型エピタキシャ
ル層、１０・・・・・・Ｐ型絶縁分離拡散層、１１・・
・・・・Ｐ型エビタギシャル層、１２・・・・・・Ｎ型
絶縁分離拡散層、１３・・・・・・Ｎ型拡散層。
６一Fig. 1 is a cross-sectional view of a one-chip series diode according to an embodiment of the present invention after bonding, Fig. 2 is a circuit diagram of a three-terminal series diode, and Fig. 3 is a conventional series diode configured with two pellets. FIG. 3 is a sectional view after bonding. DESCRIPTION OF SYMBOLS 1... N-type semiconductor substrate, 2... P-type diffusion layer, 3... Insulating film, 4... Metal electrode layer, 5... ... Back metal electrode layer, 6 ... Brazing material, 7 ... Bonding wire, 8 ...
... P-type semiconductor substrate, 9 ... N-type epitaxial layer, 10 ... P-type insulating isolation diffusion layer, 11 ...
. . . P type epitaxial layer, 12 . . . N type insulating isolation diffusion layer, 13 . . . N type diffusion layer. 61
Claims (1)
１のエピタキシャル層と、該第１のエピタキシャル層を
絶縁分離する第１拡散層と、該第１のエピタキシャル上
に形成された反対導電型の第２のエピタキシャルと、該
第２のエピタキシャル層を絶縁分離する第２拡散層と、
該第２のエピタキシャル層内に表面より形成された第３
拡散層と、前記第２拡散層と前記第２のエピタキシャル
層とが同電位となる様に形成された金属電極層とを有す
ることを特徴とする半導体装置。A first epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type, a first diffusion layer for insulating and separating the first epitaxial layer, and an opposite conductivity layer formed on the first epitaxial layer. a second epitaxial layer of the type, and a second diffusion layer that insulates and isolates the second epitaxial layer;
a third epitaxial layer formed from a surface within the second epitaxial layer;
A semiconductor device comprising: a diffusion layer; and a metal electrode layer formed so that the second diffusion layer and the second epitaxial layer have the same potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61019409A JPS62177978A (en) | 1986-01-30 | 1986-01-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61019409A JPS62177978A (en) | 1986-01-30 | 1986-01-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62177978A true JPS62177978A (en) | 1987-08-04 |
Family
ID=11998456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61019409A Pending JPS62177978A (en) | 1986-01-30 | 1986-01-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62177978A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03280460A (en) * | 1990-03-29 | 1991-12-11 | Toshiba Corp | Diode module and bridge circuit structure |
-
1986
- 1986-01-30 JP JP61019409A patent/JPS62177978A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03280460A (en) * | 1990-03-29 | 1991-12-11 | Toshiba Corp | Diode module and bridge circuit structure |
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