JPS62176983A - Device for producing iii-v compound semiconductor - Google Patents

Abstract

PURPOSE:To obtain the titled device capable of reducing the dislocation number in a crystal and highly integrating the compd. semiconductor IC by providing a part for measuring the surface temp. of the crystal during growth, a crystal form arithmetic part by a gravitational method, a thermal strain calculating part, the minimum thermal strain form estimating part, and a controlling variable arithmetic part. CONSTITUTION:In the device for producing a III-V compd. semiconductor (e.g., GaAs) by the (liq.-sealed) Czochralski method, the form of the grown crystal 2 is initially calculated by the signal from a weight sensor 10 in the crystal form arithmetic part 12. The residual thermal strain is obtained by using the form in the thermal strain calculating part 13. In this case, the surface temp. Ts of the crystal is measured and obtained in the surface temp. measuring part 11 by using an IR temp. sensor 1. Then the crystal form wherein the thermal strain distribution obtained by the calculation during crystal growth is minimized is estimated in the minimum thermal strain form estimating part 14. Then the temp. of a heater is controlled by the controlling variable arithmetic part 15 so that the desired form is approached. Such controls are repeated during crystal growth, and the crystal is grown in the form wherein the residual thermal strain is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for producing a single crystal of a ■-v group compound semiconductor, and more particularly to an apparatus for producing a dislocation-free or low-dislocation crystal.

[Conventional technology]

In recent years, compound semiconductors of the ■-■ group have come to be widely used in integrated circuits, optoelectronic integrated circuits, etc., as high-quality crystals can be obtained. ■-Among group V compound semiconductors, gallium arsenide (GaAs) and indium phosphide (IrP) have high electron mobility and are easy to emit light, and are used in microwave transistors, high-speed integrated circuits, solar cells, and optical devices.・
It is becoming widely used as an electronic device material.

In order for a compound semiconductor single crystal to be used as a substrate for the above-mentioned integrated circuit, it is required to have semi-insulating properties with a resistivity of 1010 cm or more, no dislocations in the crystal, and a small amount of residual impurities. . Among these, dislocations in particular affect the characteristics of integrated circuits and cause a decrease in yield.

Dislocations in the crystal are mainly caused by the temperature distribution within the crystal that occurs during crystal growth and cooling, and the smaller the temperature difference within the crystal, the less likely thermal strain is introduced and the number of dislocations decreases.

Conventionally, low-dislocation crystals have been produced by modifying the shape of the carbon heat insulating material and heat shielding plates in the furnace to lower the temperature gradient and improve the temperature distribution within the crystal.

[Problem that the invention seeks to solve]

On the other hand, it is empirically known that the dislocation distribution in a crystal depends on the shape of the growing crystal. Therefore, in order to obtain a low dislocation crystal, 1. In addition to improving the temperature distribution inside the furnace, it is necessary to predict a shape that will reduce the dislocation distribution and control that shape.

Conventionally, there is an automatic diameter control pulling device that calculates the crystal shape using a gravimetric method and makes it possible to grow the crystal with a constant radius, but this method does not provide any knowledge about the residual stress in the crystal.

The present invention provides an apparatus for manufacturing a ■-■ group compound semiconductor which eliminates the above-mentioned drawbacks.

[Means for solving problems]

The present invention is an apparatus for manufacturing a ■-■ group compound semiconductor single crystal by the Czochralski method or the liquid-filled Czochralski method, in which the surface temperature of the growing crystal is measured, the crystal shape calculation section using the gravimetric method, and the minimum thermal strain calculation section. This is a manufacturing apparatus for a ■-■ group compound semiconductor characterized by having a thermal distortion shape prediction section and a control amount calculation section.

FIG. 1 shows a block diagram of a device according to the invention.

First, the shape of the growing crystal 2 is calculated by the crystal shape calculating section 12 based on the signal from the weight sensor 10. Next, using this shape, the residual thermal strain in the crystal is calculated by the thermal strain calculation unit 13, and this calculation is performed using J, Crystal, Growfh 6
1 (1983) 576, it is necessary to determine the surface temperature Ts of the crystal. We determined Ts by measuring it with a surface temperature measuring section 11 using an infrared temperature sensor 1. Other physical constants used in the calculations are the values shown in the previous literature.

Next, during crystal growth, a minimum thermal strain shape prediction unit 14 predicts a crystal shape that minimizes the thermal strain distribution obtained by calculation. This prediction is made as follows.

When the crystal radius r is expressed by analytical continuation as a quadratic function of Z with the pulling axis direction as the Z axis, the absolute value a of the coefficient of the quadratic term of Z is in the range of θ ~ 0.020. Several crystal shapes are assumed at the time when crystal growth has progressed for 20 to 60 minutes, and thermal strain analysis is performed on each of them, and the relationship between the residual thermal strain value and the a value is calculated. a with the lowest thermal strain value
The value is determined, and the shape with that a value is defined as the shape with the least thermal distortion.

Next, the control amount calculating section 15 controls the temperature of the heater so as to approach this target shape.

During crystal growth, such control is repeated to grow the crystal in a shape that minimizes thermal distortion due to thermal lightning.

Since the calculation time for one shape using the finite element method is about 4 minutes, it is possible to calculate 5 to 15 shapes in 20 to 60 minutes.

〔Example〕

Hereinafter, specific examples according to the present invention will be shown.

A PBN crucible with a diameter of 4 inches was charged with 1500 g of equal chemical equivalents of gallium and arsenic, and the thickness of Btus was 10
mm. A heat shield plate was placed on top of the heater to cover it, and the thermocouple at the bottom of the crucible carried out direct synthesis at 1350° C. for 45 minutes. During crystal growth, three heaters in the furnace were controlled to maintain a temperature gradient of 20° C. at the solid-liquid interface.

In addition to the above undoped crystal, indium is added to the melt in 1.
Indium doped crystals were also made with 0x10"6 cm" doping. The manufacturing conditions are the same as those for undoped. A total of four types of experiments were conducted on each of these indium-doped crystals and undoped crystals using an apparatus according to the present method and an apparatus according to the conventional method. UAI/NASTRAN was used as the program for calculating residual stress. The calculation time for one shape was 3 minutes and 30 seconds, so
Calculations were performed 13 times for different a values, and the minimum thermal distortion shape was determined from the results.

Table 1 shows the number of dislocations of the crystal obtained by the conventional method and the crystal obtained by the method of the present invention for each of the undoped crystal and the indium-doped crystal, with respect to each solidification rate of the crystal. The number of dislocations is K
It was determined by a chemical corrosion method using an OH solution, and is shown as an average of 9 points within a 2-inch wafer.

Calculate the residual thermal strain of the growing crystal as shown in Table 1,
The shape after 45 minutes when this will be the minimum is predicted and fed back to the shape during growth.

According to the method of the present invention, dislocations in the crystal can be reduced.

Table 1 [Effects of the Invention] As explained above, according to the device of the present invention, the number of dislocations in the crystal can be reduced, and by manufacturing an FET on a wafer obtained from this crystal, an FET with extremely small variation in characteristics can be produced. This has the effect of increasing the degree of integration of compound semiconductor ICs. Furthermore, when an epitaxial layer is grown on this wafer, a layer with excellent crystallinity with few dislocations can be formed, which has the effect of being usable as a substrate for optical/electronic coupled integrated circuits.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of the device of the present invention, which includes: 1. Temperature sensor part 2. Compound semiconductor single crystal 3.・・・・・・
...Liquid sealant 4...Compound semiconductor melt 5...
···heater

Claims (1)

[Claims] In an apparatus for producing a III-V compound semiconductor single crystal by the Czochralski method or the liquid-sealed Czochralski method, there is a surface temperature measurement section of a growing crystal, a crystal shape calculation section using a gravimetric method, a thermal strain calculation section, A manufacturing apparatus for a III-V compound semiconductor, characterized by having a minimum thermal distortion shape prediction section and a control amount calculation section.