JPH0694397B2 - (III) -Group V compound semiconductor manufacturing apparatus - Google Patents
(III) -Group V compound semiconductor manufacturing apparatusInfo
- Publication number
- JPH0694397B2 JPH0694397B2 JP1940286A JP1940286A JPH0694397B2 JP H0694397 B2 JPH0694397 B2 JP H0694397B2 JP 1940286 A JP1940286 A JP 1940286A JP 1940286 A JP1940286 A JP 1940286A JP H0694397 B2 JPH0694397 B2 JP H0694397B2
- Authority
- JP
- Japan
- Prior art keywords
- crystal
- thermal strain
- unit
- shape
- iii
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 150000001875 compounds Chemical class 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000013078 crystal Substances 0.000 claims description 60
- 238000004364 calculation method Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 9
- 238000009529 body temperature measurement Methods 0.000 claims description 2
- 238000009826 distribution Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000004033 diameter control Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000012887 quadratic function Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Description
【発明の詳細な説明】 本発明はIII−Ｖ族化合物半導体単結晶の製造装置に関
し、特に無転位又は低転位結晶を得るための製造装置に
関する。The present invention relates to a manufacturing apparatus for III-V group compound semiconductor single crystals, and more particularly to a manufacturing apparatus for obtaining dislocation-free or low-dislocation crystals.
近年III−Ｖ族化合物半導体は高品質の結晶が得られる
様になり集積回路、光電子集積回路などに広く用いられ
る様になってきた。III−Ｖ族化合物半導体の中でもガ
リウム砒素（GaAs）やインジウム・リン（IrP）等は電
子移動度が大きく、発光し易い等の特徴を有しマイクロ
波用トランジスタや高速集積回路、太陽電池及び光・電
子素子材料として広く用いられつつある。In recent years, III-V group compound semiconductors have come to be used for integrated circuits, optoelectronic integrated circuits, etc., because high quality crystals have been obtained. Among III-V group compound semiconductors, gallium arsenide (GaAs), indium phosphide (IrP), etc. have characteristics such as high electron mobility and easy light emission, and have characteristics such as microwave transistors, high-speed integrated circuits, solar cells and optical devices. -It is being widely used as a material for electronic devices.
化合物半導体単結晶が上述の集積回路用基板として用い
られるには比抵抗が107Ω・cm以上の半絶縁性を有する
事、結晶中に転位がない事、残留不純物が少ない事、等
が要求される。この中で特に転位は集積回路の特性に影
響を与え歩留りを低下させる原因となっている。In order for a compound semiconductor single crystal to be used as a substrate for integrated circuits as described above, it must have a semi-insulating property with a specific resistance of 10 7 Ωcm or more, no dislocations in the crystal, and few residual impurities. To be done. Of these, dislocations particularly affect the characteristics of integrated circuits and are a cause of lowering the yield.
結晶中の転位は、結晶成長中及び冷却中に生じる結晶内
の温度分布に主に起因しており、結晶内温度差が小さい
程それによる熱的な歪が導入されにくく転位は少くな
る。The dislocations in the crystal are mainly caused by the temperature distribution in the crystal generated during the crystal growth and cooling, and the smaller the temperature difference in the crystal, the less the thermal strain is introduced and the fewer the dislocations.
従来、低転位結晶を作製するには炉内のカーボン保温材
や熱遮蔽板の形状を工夫して、低温度勾配化を行い結晶
内温度分布を改善して行っている。Conventionally, in order to produce a low dislocation crystal, the shape of the carbon heat insulating material and the heat shield plate in the furnace has been devised, and the temperature gradient in the crystal has been reduced to improve the temperature distribution in the crystal.
一方、結晶中の転位分布は成長中の結晶の形状に依存す
る事が経験的に知られている。従って低転位結晶を得る
には、炉内の温度分布を改善する事に加えて、転位分布
が少くなる様な形状を予測し、その形状を制御する必要
がある。On the other hand, it is empirically known that the dislocation distribution in a crystal depends on the shape of the growing crystal. Therefore, in order to obtain a low dislocation crystal, in addition to improving the temperature distribution in the furnace, it is necessary to predict a shape in which the dislocation distribution is small and control the shape.
従来、重量法により結晶形状を演算し結晶半径を一定に
して成長する事を可能にした自動直径制御引上げ装置が
あるが、この方法では結晶中の残留応力について何ら知
見が得られない。Conventionally, there is an automatic diameter control pulling device capable of calculating the crystal shape by the weight method and growing the crystal with a constant crystal radius, but this method cannot provide any knowledge about the residual stress in the crystal.
本発明は、上記欠点を除いたIII−Ｖ族化合物半導体の
製造装置を提供するものである。The present invention provides an apparatus for producing a III-V group compound semiconductor without the above drawbacks.
本発明によれば、III−Ｖ族化合物半導体単結晶をチョ
クラルスキー法で作成する製造装置において、成長中の
結晶の表面温度を測定する表面温度測定部と、成長中の
結晶の重量を測定する重量センサー部と、重量センサー
部により測定された重量から結晶形状を演算する結晶形
状演算部と、結晶形状演算部により計算された結晶形状
と表面温度測定部により測定された表面温度とから結晶
中の残留熱歪を計算する熱歪計算部と、熱歪計算部によ
り計算された残留熱歪が一定時間後に最小になるような
条件を予測する最小熱歪予測部と、最小熱歪予測部によ
り予測された条件に合うように設定温度を調節する制御
量演算部とを有するIII−Ｖ族化合物半導体の製造装置
が得られる。According to the present invention, in a manufacturing apparatus for producing a III-V compound semiconductor single crystal by the Czochralski method, a surface temperature measuring unit for measuring a surface temperature of a growing crystal and a weight of the growing crystal are measured. A weight sensor unit, a crystal shape calculation unit that calculates the crystal shape from the weight measured by the weight sensor unit, and a crystal from the crystal shape calculated by the crystal shape calculation unit and the surface temperature measured by the surface temperature measurement unit. Thermal strain calculation unit that calculates the residual thermal strain in the inside, minimum thermal strain prediction unit that predicts the condition that the residual thermal strain calculated by the thermal strain calculation unit becomes the minimum after a certain time, and minimum thermal strain prediction unit A III-V compound semiconductor manufacturing apparatus having a controlled variable calculating unit for adjusting the set temperature so as to meet the conditions predicted by
第１図に本発明による装置のブロック図を示す。まず重
量センサー10の信号により成長結晶２の形状を結晶形状
演算部12にて演算する。次にその形状を用いて結晶中の
残留熱歪を熱歪計算部13で求める訳であるが、この計算
にはJ.Cryst.Growfh 61（1983）576に示される様に結晶
の表面温度Tsを求める事が必要である。我々はTsを赤外
線温度センサー１を用いた、表面温度測定部11で測定し
て求めた。計算に用いた他の物理定数は先の文献に示さ
れている値を用いている。FIG. 1 shows a block diagram of the device according to the invention. First, the crystal shape calculator 12 calculates the shape of the grown crystal 2 based on the signal from the weight sensor 10. Next, the shape is used to determine the residual thermal strain in the crystal by the thermal strain calculation unit 13. In this calculation, as shown in J. Cryst. Growfh 61 (1983) 576, the surface temperature Ts of the crystal is calculated. It is necessary to ask. We obtained Ts by measuring the surface temperature measuring unit 11 using the infrared temperature sensor 1. The other physical constants used in the calculation use the values shown in the above literature.
次に結晶成長中、計算によって得られた熱歪分布が最小
になる様な結晶形状を最少熱歪形状予測部14で予測す
る。この予測は次の様にして行う。Next, during crystal growth, the minimum thermal strain shape predicting unit 14 predicts a crystal shape such that the thermal strain distribution obtained by calculation is minimized. This prediction is made as follows.
引き上げ軸方向をＺ軸として結晶半径ｒをＺの２次の関
数で解析接続により表した時、Ｚの２次の項の係数の絶
対値ａが０〜0.020の範囲にある様な結晶形状のうち数
通りを、現時点よりも20〜60分結晶成長が進行した時点
で想定し、その各々に対して熱歪解析を行ない、残留熱
歪値とａ値との関係から熱歪値が最少であるａ値を求
め、そのａ値を持つ形状を最少熱歪形状とする。When the crystal radius r is expressed as an analytical connection by a quadratic function of Z with the pulling axis direction as the Z axis, the absolute value a of the coefficient of the quadratic term of Z is in the range of 0 to 0.020. A few of them are assumed when the crystal growth progresses for 20 to 60 minutes from the present time, and thermal strain analysis is performed for each of them, and the thermal strain value is minimized from the relationship between the residual thermal strain value and the a value. A certain a value is obtained, and the shape having the a value is set as the minimum thermal strain shape.
次に制御量演算部15により、この目標形状に近づく様に
ヒーターの温度を制御する。Next, the control amount calculation unit 15 controls the temperature of the heater so as to approach the target shape.
結晶成長中、この様な制御を繰り返し熱留熱歪が最少と
なる形状で結晶を育成する。During crystal growth, such control is repeated to grow the crystal in a shape that minimizes thermal strain.
尚、有限要素法による一つの形状の計算時間は約４分で
あるので20〜60分の間で５〜15通りの形状について計算
できる。Since the calculation time for one shape by the finite element method is about 4 minutes, 5 to 15 kinds of shapes can be calculated in 20 to 60 minutes.
以下、本発明による具体的実施例を示す。 Hereinafter, specific examples according to the present invention will be shown.
４インチ径のPBNるつぼ中にガリウムと砒素を等化学当
量ずつ1500gチャージし、B2O3の厚さは10mmとした。ヒ
ーターの上部にそれを覆う様にして熱遮蔽板を置き、る
つぼの底の熱電対が1350℃で45分間直接合成を行った。
また結晶成長時は炉内の三つのヒーターを制御して固液
界面の温度勾配を20℃とした。In a 4-inch diameter PBN crucible, 1500 g of gallium and arsenic were charged at equal chemical equivalents, and the thickness of B 2 O 3 was 10 mm. A heat shield was placed on the top of the heater so as to cover it, and the thermocouple at the bottom of the crucible was directly synthesized at 1350 ° C. for 45 minutes.
During crystal growth, three heaters in the furnace were controlled to control the temperature gradient at the solid-liquid interface to 20 ° C.
上記のアンドープ結晶の他にインジウムを融液中に1.0
×1020cm-3ドープしてインジウム・ドープ結晶も作製し
た。作製条件はアンドープのものと同じである。これら
のインジウム・ドープ結晶とアンドープ結晶の各々に対
して本方法による装置と従来の方法による装置を用い、
計４種類の実験を行った。残留ストレスを計算する際の
プログラムにはUAI/NASTRANを用いた。１つの形状の計
算時間は３分30秒であったので、異なるａ値について13
回の計算を行ない、その結果から最少熱歪形状を求め
た。In addition to the above undoped crystal, indium was added to the melt at 1.0
Indium-doped crystals were also prepared by doping × 10 20 cm -3 . The manufacturing conditions are the same as those of the undoped one. Using the device according to the present method and the device according to the conventional method for each of these indium-doped crystals and undoped crystals,
Four kinds of experiments were conducted in total. UAI / NASTRAN was used as a program for calculating residual stress. Since the calculation time for one shape was 3 minutes and 30 seconds, 13
The calculation was performed once, and the minimum thermal strain shape was obtained from the results.
従来の方法による結晶と本発明の方法による結晶の転位
数をアンドープ結晶とインジウム・ドープ結晶の各々に
つき、結晶の各固化率に対して表１に示す。転位数はKO
H溶液による化学腐食法により求めたものであり２イン
チウェハー内で９点の平均で示してある。The number of dislocations in the crystal according to the conventional method and the crystal according to the method of the present invention is shown in Table 1 for each solidification rate of the crystal for each of the undoped crystal and the indium-doped crystal. Number of dislocations is KO
It was obtained by the chemical corrosion method using the H solution and is shown as an average of 9 points in a 2-inch wafer.
表１からわかる様に成長中の結晶の残留熱歪を計算し、
それが最少となる45分後の形状を予測し、成長中の形状
にフィード・バックする。As can be seen from Table 1, the residual thermal strain of the growing crystal was calculated,
Predict the shape after 45 minutes when it becomes the minimum, and feed back to the growing shape.
本発明の方法によれば結晶中の転位が低減できる。The method of the present invention can reduce dislocations in the crystal.
〔発明の効果〕 以上説明した様に本発明の装置によれば結晶中の転位数
が低減でき、この結晶から得られるウェハーにFETを作
製する事により特性バラツキの極めて少ないFETが得ら
れ、化合物半導体ICを高集積化できる効果がある。さら
にこのウェハーにエピタキシャル層を成長させた場合、
転位の少ない結晶性の優れた層を形成する事ができ光・
電子結合型集積回路用基板として使用できる効果があ
る。 [Effects of the Invention] As described above, according to the device of the present invention, the number of dislocations in the crystal can be reduced, and FET having a very small variation in characteristics can be obtained by producing the FET on the wafer obtained from the crystal. There is an effect that the semiconductor IC can be highly integrated. If further epitaxial layers are grown on this wafer,
It is possible to form a layer with few dislocations and excellent crystallinity.
There is an effect that it can be used as a substrate for an electronically coupled integrated circuit.
第１図は、本発明の装置をブロック図で示したものであ
り、 １……温度センサー部 ２……化合物半導体単結晶 ３……液体封止剤 ４……化合物半導体融液 ５……ヒーターFIG. 1 is a block diagram showing the apparatus of the present invention, 1 ... Temperature sensor part 2 ... Compound semiconductor single crystal 3 ... Liquid sealant 4 ... Compound semiconductor melt 5 ... Heater
Claims (1)
ルスキー法で作成する製造装置において、成長中の結晶
の表面温度を測定する表面温度測定部と、前記成長中の
結晶の重量を測定する重量センサー部と、前記重量セン
サー部により測定された重量から結晶形状を演算する結
晶形状演算部と、前記結晶形状演算部により計算された
結晶形状と前記表面温度測定部により測定された表面温
度とから結晶中の残留熱歪を計算する熱歪計算部と、前
記熱歪計算部により計算された残留熱歪が一定時間後に
最小になるような条件を予測する最小熱歪予測部と、前
記最小熱歪予測部により予測された条件に合うように設
定温度を調節する制御量演算部とを有することを特徴と
するIII−Ｖ族化合物半導体の製造装置。1. A manufacturing apparatus for producing a III-V compound semiconductor single crystal by the Czochralski method, and a surface temperature measuring unit for measuring a surface temperature of a growing crystal, and a weight of the growing crystal. A weight sensor unit, a crystal shape calculation unit that calculates a crystal shape from the weight measured by the weight sensor unit, a crystal shape calculated by the crystal shape calculation unit, and a surface temperature measured by the surface temperature measurement unit From the thermal strain calculation unit to calculate the residual thermal strain in the crystal from, and the minimum thermal strain prediction unit to predict the condition that the residual thermal strain calculated by the thermal strain calculation unit becomes a minimum after a certain time, An apparatus for manufacturing a III-V group compound semiconductor, comprising: a controlled variable calculation unit that adjusts a set temperature so as to meet the condition predicted by the minimum thermal strain prediction unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1940286A JPH0694397B2 (en) | 1986-01-30 | 1986-01-30 | (III) -Group V compound semiconductor manufacturing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1940286A JPH0694397B2 (en) | 1986-01-30 | 1986-01-30 | (III) -Group V compound semiconductor manufacturing apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62176983A JPS62176983A (en) | 1987-08-03 |
| JPH0694397B2 true JPH0694397B2 (en) | 1994-11-24 |
Family
ID=11998271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1940286A Expired - Lifetime JPH0694397B2 (en) | 1986-01-30 | 1986-01-30 | (III) -Group V compound semiconductor manufacturing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0694397B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01264992A (en) * | 1988-04-13 | 1989-10-23 | Toshiba Ceramics Co Ltd | Single crystal pulling up device |
-
1986
- 1986-01-30 JP JP1940286A patent/JPH0694397B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62176983A (en) | 1987-08-03 |
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