JPS61247700A - Preparation of iii-v compound semiconductor - Google Patents

Abstract

PURPOSE:To obtain a III-V compound semiconductor contg. no dislocation suitable as material for a substrate of GaAs integrated circuit, and substrate for optical-electronic integrated circuit by growing a GaAs single crystal by the pulling method from GaAs soln. by allowing a specified amt. of In element to be contained. CONSTITUTION:A GaAs single crystal is grown from melt by pulling method by melting a mixture consisting of Ga as a Group III element, As and In as Group V element, B2O3 as liquid sealing agent to a PBN crucible wherein the growth of the GaAs single crystal is controlled by regulating the concn. of In contained in the crystal to 4.0X10<18>-6.0X10<19>cm<-3> and the temp. gradient at the solid/liquid boundary of the GaAs single crystal and the melt formed by the pulling to 5-40 deg.C/cm.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for producing a Ill-V group compound semiconductor single crystal, and is particularly suitable for a GaAs integrated circuit substrate and an opto-electronic integrated circuit substrate. The present invention relates to a method for manufacturing a dislocation-free GaAs single crystal.

[Conventional technology]

Recently, III-V group compound semiconductors have come to be widely used in integrated circuits, opto-electronic integrated circuits, electronic device materials, etc. as high quality crystals can be obtained. - Among group V compound semiconductors, gallium arsenide (OaAs) has the characteristics of high electron mobility, easy luminescence, and the ability to detect single rays.It is used in microwave transistors, high-speed integrated circuits,
It is becoming widely used as a material for solar cells and opto-electronic devices.

In order for the G a A,s single crystal to be used as the above-mentioned integrated circuit substrate and opto-electronic integrated circuit substrate, the specific resistance must be 10.
It is required to have a semi-insulating property of 7Ω·α or more, to be free from physical and chemical defects such as dislocations and lattice defects, and to have a small amount of residual impurities. Among these, dislocations and lattice defects in particular affect the characteristics of integrated circuits and cause a decrease in yield.

Recently, it has become clear that dislocations can be significantly reduced by adding indium (In) to OaAs crystals.Integrated circuits have been developed using GaAs crystals that have been made dislocation-free by adding In. Once fabricated, the threshold voltage (v
th) can be reduced.

[Problem that the invention seeks to solve]

However, when the temperature gradient at the solid-liquid interface is 4Q'Q/cm or more, it is necessary to add I to make the GaAs substrate dislocation-free.
It is necessary that the n concentration is 5 x l 019cm-" or more,
10×lQ2′cm-” to 3. Q x l Q 2
The effect is strongest within the range of 06m-3. However, adding multiple In in this way has a drawback in that the activation rate of the ion-implanted atoms decreases.

Further, when GaAs is epitaxially grown on the above-mentioned GaAs substrate, there are problems such as the inability to obtain a good quality epitaxial layer due to lattice misalignment.

This is a fatal drawback for opto-electronic integrated circuit boards.

An object of the present invention is to provide a method for growing a Ga A, s single crystal that eliminates the above-mentioned drawbacks.

[Means for solving problems]

According to the present invention, 0aAs single crystal is made of indium element 4
．． Q x l Q “Cm-” or more 60 x 10”
It is produced by the Czochralski method so that the VC is less than Cm-3. In particular, when pulling up from the Ga As solution, the temperature gradient at the solid-liquid interface is set to 5 to 40°C/Cm to incorporate indium into the Ga As crystal.

[Effect]

Oa A, sThe temperature gradient at the solid-liquid interface is conventionally 40℃/cm
Although it has been considered difficult to achieve a temperature below 40°C/cm or more than 5°C/cm by optimizing the thickness of the liquid-sealed cup, the structure of the multistage heater, and the shape of the heat-insulating tube. Under such a low temperature gradient, residual thermal strain in the crystal is small (I
Even when n is not added, the dislocation density by chemical corrosion method is 2.
X I Q3 (1m-3~4 X I Q"1l17
Crystals of i2 are obtained. Under this low temperature gradient condition, as shown in Figure 1, the concentration of In contained in the crystal is 4.5%.
Ox ], 01acm3 to 6. Ox 1019cy
No dislocation can be achieved within the range of n-3. Furthermore, the temperature gradient is 5°C.
Below /σ, it becomes difficult to control the crystal shape during crystal growth υ, and dislocations are introduced due to the rapid increase/decrease in diameter, making it impossible to eliminate dislocations. A crystal with In added within this range is Ga
When used as a substrate for an As integrated circuit, the activation rate of the ion-implanted atoms is better than that of a substrate with a high In concentration, as shown in FIG. This is because the implanted atoms react with indium in the substrate, preventing activation.

On the other hand, the standard deviation of the threshold voltage variation within the wafer surface also increases as the In concentration increases, as shown in Figure 3, because added In forms defects such as growth stripes and In precipitation inside the crystal. Become.

Furthermore, if an epitaxial layer is grown on a crystal doped with In within this range, a crystallinity comparable to that of a mandoped crystal can be obtained, as shown in Figure 4, but as the In concentration increases, The crystallinity of the epitaxial layer deteriorates due to the lattice misalignment. The crystallinity was evaluated by the half width of the X-ray rocking curve.

〔Example〕

Examples according to the present invention will be shown below.

A 4-inch diameter PBN melt was charged with 2100 g of equal chemical equivalents of gallium and arsenic, and 80 g of indium and arsenic in equivalent chemical equivalents to the added amount were added. The thickness of the B2O3 layer, which is a liquid sealant, is 100 degrees, and a heat shield plate is placed on top to reduce the temperature gradient at the solid-liquid interface to 70°C/c! A single crystal A with a diameter of 54 mm and a length of 80 mm was produced. On the other hand, 8 g of indium and chemically equivalent amount of arsenic were added, and the temperature gradient at the solid-liquid interface was adjusted to 2 by controlling each of the three heaters.
Single crystal B was produced using the same manufacturing method as crystal A except that the temperature was 0°C/cIn.

For each crystal, single crystal A and single crystal B, Ueno was cut out from a portion 20 degrees from the top of the straight body, and the dislocation density was examined using a chemical corrosion method. As a result, no dislocations were found. An integrated circuit of field effect transistors was fabricated using the wafers adjacent to these i′L, and the threshold voltage (v
As a result of measuring the variation (σVth) in single crystal A, it was large at 20 mV, but it was small at 6 mV in single crystal B.

Amada activation rate is 11chi for single crystal A and 4 for single crystal B.
It was 5chi.

〔Effect of the invention〕

As explained above, by using the method according to the present invention, it is possible to obtain a dislocation-free GaAs crystal with a low In concentration in the crystal, and a field effect transistor can be built in the Ueno obtained from this crystal. By manufacturing this, a field effect transistor with extremely small temporal variations can be obtained, and GaAs ICs can be highly integrated. Furthermore, when an epitaxial layer is grown on this wafer, it is possible to form a layer with excellent crystallinity free of dislocations, which has the effect of being usable as a substrate for opto-electronic integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a graph showing the relationship between the temperature gradient at the solid-liquid interface and the amount of indium in the crystal required to make a GaAs substrate free of dislocations. FIG. 2 is a graph showing the relationship between the In concentration in the crystal and the activation rate. FIG. 3 is a graph showing the relationship between the In9 degree in the crystal and the variation (σvth) in the threshold voltage of a field effect transistor. FIG. 4 is a graph showing the relationship between the In concentration in the crystal and the half width of the X-ray locking curve of the epitaxial layer.

Claims (1)

[Claims] 1. GaAs single crystal with indium element of 4.0×10^
1^8cm^-^3 or more 6.0 x 10^1^9cm^-
A method for manufacturing a III-V compound semiconductor, characterized in that a single crystal is pulled from a GaAs solution as a growth seed so as to contain ^3 or less. 2. Claim 1, characterized in that the temperature gradient at the solid-liquid interface between the GaAs solution and the GaAs single crystal formed by pulling the single crystal as a growth seed is 5 to 40°C/cm. A method for manufacturing the III-V compound semiconductor described above.