JPS6217668A - Apparatus for inspecting semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to measure a time with high accuracy, by relatively simple constitution such that IC output through a data converter is also supplied to a time measuring means through a selector. CONSTITUTION:The outputs of a semiconductor IC2 to be inspected are converted to digital signals by driver comparators DC1-DC6 and selectively applied to the pattern generator analyser 4 of an inspection apparatus main body and the time counter 5 of a time measuring means through a data selector 9. The analyser 4 selectively analyzes the output of each measuring pin of IC2 and the counter 5 measures the timewise relation between the outputs of the measuring pins of IC2 because the skews of the comparators DC1-DC6 are equal. Therefore, a large number of switches changing over the outputs of IC2 are dispensed with and the outputs of IC2 can be subjected to digital conversion in the vicinity of IC2 and the error caused by the attenuation or wave form strain of a high frequency signal in a coaxial cable is reduced and the measurement of a time can be performed with high accuracy by relatively simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit testing device, and more particularly to an improvement in a time measurement system.

[Prior Art] FIG. 5 is a block diagram showing an example of a main part of a conventional semiconductor integrated circuit testing apparatus. In FIG. 5, 1 is a test head in which a semiconductor integrated circuit to be tested (hereinafter referred to as CUT) 2 is arranged, and 3 is a test device main body, which generates a test pattern to be applied to DUT2 and outputs it from UT2. (Pattern generator analyzer 4 (hereinafter referred to as PGA), which has the function of analyzing No. 8, DUT
The time counter 5 has a function of measuring the time relationship of the signals outputted from the time counter 2 and the like. The test head 1 and the PGA 4 are connected via a bus 6, and the test head 1 and the time counter 5 are connected via a coaxial cable 7.8.

FIG. 6 is a block diagram showing a specific example of the inside of such a test head 1. As shown in FIG. Each terminal of DUT2 is connected to a driver comparator DC via a switch S+=Ss.
+~DCg are connected, and these driver comparators D
CI-DC6 is connected to PGA1 via bus 6. In addition, each terminal of 0UT2 has a switch 87.
One coaxial cable 7 is connected via switches Se3 to Sea, and the other coaxial cable 8 is connected via switches Se3 to Sea.

In such a configuration, when measuring the DUT 2 using the PGA 4, the switches sI to S6 are selectively turned on and off, and when measuring the time relationship using the time counter 5, the switches 87 to SI2 and S
l) - Selectively turn on and off SO6.

[Problems to be Solved by the Invention] However, according to such a conventional configuration, a large number of switches are required to disconnect the wiring between the PGA 4 and the time counter 5, and the number of accompanying wirings increases. The structure becomes complicated. In addition, because the wiring of the coaxial cable 7.8 up to the time counter 5 is long (e.g. about 10-MHz), high-frequency signals (e.g.
M I-l z ) +7) Attenuation and waveform distortion may occur, leading to measurement errors.

The present invention has been made in view of these points, and its object is to provide a semiconductor integrated circuit testing device that has a relatively simple structure and can perform highly accurate time measurements.

Means for Solving Problem E] The present invention that achieves the above object includes a plurality of comparators connected to an output terminal of a semiconductor integrated circuit to be tested.
It is characterized by comprising a data selector connected to the output terminal of each of these comparators, and a time measuring means connected to the output terminal of the data selector.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, and the same parts as in FIG. 5 are given the same reference numerals. 1st
In the figure, the test head 1 is equipped with conventional switches 81 to 81.
A data selector 9 is provided in place of S's.

FIG. 2 is a block diagram showing a specific example of the inside of the test head shown in FIG. 1, and the same parts as in FIG. 6 are given the same reference numerals.

In FIG. 2, PGA4. Time counter 5 and D
C+ to DCa are connected to each other via a data selector 9.

In such a configuration, the output of each measurement bin of 0UT2 as shown in FIGS. 3(a) to (C) is DC+
~ DCs converts the bales into digital signals as shown in Figures 4 (a) ~ (C), and the data selector 9 converts the bales into PG signals.
It will be selectively added to A4 and time counter 5. As a result, the PGA 4 can selectively analyze the output of each measurement bin of DLIT 2, and the time counter 5 can detect the time relationship between the outputs of each measurement bin of OUT 2 since the respective skews of DC blind to DCg are equal. can be measured.

With this configuration, the conventional PGA4
A large number of switches for disconnecting the wiring between the time counter 5 and the time counter 5 are not required, and the wiring associated therewith is also not required, so that the structure can be simplified.

Also, since DC1 to DCs are also used as comparators for the time counter 5, the analog output of CUT2 is used to measure the time relationship.
! ? Since it can be converted into a digital signal using a conventional coaxial cable, it is possible to reduce measurement errors caused by attenuation and waveform distortion of high-frequency signals that pass through a conventional coaxial cable, allowing highly accurate time measurements.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a semiconductor integrated circuit testing device that can perform highly accurate time measurement with a relatively simple structure, and has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the inside of the test head shown in FIG. 1, and FIGS. FIG. 5 is a block diagram showing an example of essential parts of a conventional semiconductor integrated circuit testing apparatus, and FIG. 6 is a block diagram showing a specific example of the inside of the test head shown in FIG. 5. DESCRIPTION OF SYMBOLS 1...Test head, 2...Semiconductor integrated circuit to be inspected (OUT), 3...Inspection device main body, 4...Pattern generator analyzer (PGA), 5...Time counter, 6... Pass, 7.8...Coaxial cable,
9...Data selector, DC...Driver comparator. Figure 3 (C) Figure 4

Claims (1)

[Claims] It is composed of a plurality of comparators connected to the output terminal of the semiconductor integrated circuit under test, a data selector connected to the output terminal of each of these comparators, and a time measuring means connected to the output terminal of the data selector. Features of semiconductor integrated circuit testing equipment.