JPS62174969A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62174969A
JPS62174969A JP1703686A JP1703686A JPS62174969A JP S62174969 A JPS62174969 A JP S62174969A JP 1703686 A JP1703686 A JP 1703686A JP 1703686 A JP1703686 A JP 1703686A JP S62174969 A JPS62174969 A JP S62174969A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
layer
film
type silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1703686A
Other languages
Japanese (ja)
Inventor
Takashi Ito
隆司 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1703686A priority Critical patent/JPS62174969A/en
Publication of JPS62174969A publication Critical patent/JPS62174969A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

PURPOSE:To obtain a substrate with an SOI structure having a highcrystal quality, by forming an insulation film over a single crystal semiconductor substrate on which a layer of a different type of semiconductor has been formed, bonding a supporting substrate thereto, and etching away the semiconductor substrate so as to leave the layer of the different type of semiconductor only. CONSTITUTION:A p-type silicon layer 11 having a thickness of about 1mum is epitaxially grown on an n<+> type silicon substrate 10 (wafer) and the surface of the p-type silicon layer 11 is heated in oxidizing atmosphere at high temperature of about 1,000-1,200 deg.C so as to produce an SiO2 film 12 having a thickness of about 0.3mum. After another silicon substrate or quartz substrate 13 (supporting substrate) is bonded thereon, only the n<+> type silicon layer 11 is left. The p-type silicon layer 11 thus obtained is a single 11 is left. The p-type silicon layer 11 thus obtained is a single crystal thin film formed on the insulating layer and this single crystal silicon film has a high quality with reduced defects. Accordingly, a semiconductor element formed on such silicon film is allowed to have a high quality with reduced parasitic capacitance.

Description

【発明の詳細な説明】 [概要] 単結晶半導体基板に異質半導体層を形成した後、その上
に絶縁膜を形成し、その絶縁膜に支持基板を接着する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] After forming a heterogeneous semiconductor layer on a single crystal semiconductor substrate, an insulating film is formed thereon, and a support substrate is bonded to the insulating film.

次いで、半導体基板をエツチング除去し、異質半導体層
のみを残存させて、Sol構造の半導体基板を形成する
。そうすると、結晶品質の良いSOI構造の基板が得ら
れる。
Next, the semiconductor substrate is removed by etching, leaving only the foreign semiconductor layer to form a semiconductor substrate with a Sol structure. In this way, a substrate having an SOI structure with good crystal quality can be obtained.

[産業上の利用分腎コ 本発明は半導体装置の製造方法のうち、特に、S01構
造半導体装置の単結晶半導体基板の形成方法に関する。
[Industrial Applications] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a single crystal semiconductor substrate of an S01 structure semiconductor device.

最近、S OI  (Silicon On In5u
lator)構造の半導体装置が注目されており、それ
は高速動作。
Recently, S OI (Silicon On In5u
Semiconductor devices with a lator structure are attracting attention because of their high-speed operation.

耐放射線、高温動作に有利な半導体装置が作成できるか
らである。例えば、立体的(三次元)に積層して、高度
に高集積化すれば、絶縁基板のための寄生容量が減少す
る効果が相乗して、高速動作が得られる。
This is because a semiconductor device that is advantageous in radiation resistance and high-temperature operation can be produced. For example, if devices are stacked three-dimensionally (three-dimensionally) and highly integrated, the effect of reducing the parasitic capacitance of the insulating substrate will combine to provide high-speed operation.

しかし、このようなS○■構造の半導体装置は1、出来
るだけ結晶品質の良い基板上に形成する、二とが、高性
能化・高品質化の面から要望されている。
However, such a semiconductor device having an S○■ structure is required to be formed on a substrate with as good a crystalline quality as possible from the viewpoints of improved performance and quality.

[従来の技術と発明が解決しようとする問題点]さて、
従前より著名なSol構造の半導体基板に、S OS 
(Silicon On 5apphire )基板が
知られており、それは第2図の断面図に示すように、サ
ファイヤ基板1上にシリコンをエピタキシャル成長して
、単結晶シリコン膜2を生成させた基板である。即ち、
サファイヤ基板は高融点の材料であるから、約1200
℃に加熱して、その上にシリコン膜を成長すると、サフ
ァイヤ結晶に沿った結晶性のシリコン膜が形成される。
[Problems to be solved by conventional technology and invention] Now,
SOS
A (Silicon On 5apphire) substrate is known, and as shown in the cross-sectional view of FIG. 2, it is a substrate in which silicon is epitaxially grown on a sapphire substrate 1 to form a single crystal silicon film 2. That is,
Since the sapphire substrate is a material with a high melting point, approximately 1200
℃ and grow a silicon film thereon, a crystalline silicon film along the sapphire crystal is formed.

しかし、サファイヤ基板が非常に高価であり、且つ、サ
ファイヤとシリコンが類似の結晶構造を有しているとは
云うものの、結晶学的にはやはり相異があって、結晶格
子のミスマツチが生じ、形成したシリコン膜2に多数の
結晶欠陥が含まれる。
However, sapphire substrates are very expensive, and although sapphire and silicon have similar crystal structures, they are still crystallographically different, resulting in a mismatch in the crystal lattice. The formed silicon film 2 contains many crystal defects.

従って、従来の引き上げ法や帯域精製法で作成したシリ
コン基板と比較すれば、結晶品質は決して良質のもので
はなく、そのため、SO8基板は余り汎用されるに至っ
ていない。
Therefore, when compared with silicon substrates produced by conventional pulling methods or zone refining methods, the crystal quality is by no means good, and as a result, SO8 substrates are not widely used.

他方、最近、提唱されているSol構造の基板に、ビー
ムアニールした作成したSol基板があり、その形成方
法を第3図(a)、(ト))で説明する。まず、同図(
a)に示すように、シリコン基板3上に二酸化シリコン
(SiO2)膜4を生成し、その上に多結晶シリコン膜
5を化学気相成長(CVD)法によって被着する。また
、この時、5i02膜の代わりに、窒化シリコン(Si
a N4 )膜を生成してもよいし、また、多結晶シリ
コン膜の代わりに、アモルファスシリコン膜を成長して
も良い。
On the other hand, one of the Sol structure substrates that has been proposed recently is a Sol substrate prepared by beam annealing, and the method for forming it will be explained with reference to FIGS. 3(a) and 3(g). First, let's start with the same figure (
As shown in a), a silicon dioxide (SiO2) film 4 is formed on a silicon substrate 3, and a polycrystalline silicon film 5 is deposited thereon by chemical vapor deposition (CVD). Also, at this time, silicon nitride (Si) was used instead of the 5i02 film.
a N4 ) film may be formed, or an amorphous silicon film may be grown instead of the polycrystalline silicon film.

次いで、第3図(blに示すように、多結晶シリコン膜
5を、例えば、連続アルゴンレーザCCW−Ar La
5er)ビームで走査して加熱溶融しくこれがビームア
ニールで、本例はレーザアニールである)、多結晶シリ
コン膜を単結晶シリコン膜5に変成する。
Next, as shown in FIG.
5er), the polycrystalline silicon film is scanned with a beam and heated and melted (this is beam annealing (this example is laser annealing)), and the polycrystalline silicon film is transformed into a single crystal silicon film 5.

ところが、この方法で作成したSOI基板は、多結晶シ
リコン膜5を完全に単結晶化することが難しく、また、
単結晶化しても結晶品質は余り良くはない。従って、や
むなく欠陥が多く、品質の良くない結晶シリコン膜5に
半導体素子を形成している現状である。
However, in the SOI substrate created by this method, it is difficult to completely convert the polycrystalline silicon film 5 into a single crystal, and
Even if it is made into a single crystal, the crystal quality is not very good. Therefore, the current situation is that semiconductor elements are unavoidably formed in a crystalline silicon film 5 that has many defects and is of poor quality.

また、上記した第3図に示す基本的な形成法を改善して
、結晶シリコン膜5の結晶品質を向上するための種々の
作成方法も試みられており、例えば、シリコン基板3に
核となる種を設け、その種からラテラルにエピタキシャ
ル成長する方法などが知られている。しかし、このよう
にして形成しても、絶縁膜との境界面近傍での欠陥の除
去は非常に難しいことで、結局、結晶品質の優れたシリ
コン薄膜は未だ作成されていない状況である。
Various methods have also been attempted to improve the crystal quality of the crystalline silicon film 5 by improving the basic formation method shown in FIG. A method is known in which a seed is set and lateral epitaxial growth is performed from the seed. However, even when formed in this manner, it is extremely difficult to remove defects near the interface with the insulating film, and as a result, a silicon thin film with excellent crystal quality has not yet been created.

本発明は、このような問題点を解決して、結晶品質の良
い単結晶薄膜が得られるSol構造基板の形成方法を提
案するものである。
The present invention solves these problems and proposes a method for forming a Sol structure substrate that allows a single crystal thin film with good crystal quality to be obtained.

c問題点を解決するための手段] その目的は、所定不純物濃度の一導電型半導体基板(例
えば、n型シリコン基板)に、該不純物濃度とは異なる
不純物濃度を有する半導体層、あるいは、異種導電型の
半導体層(例えば、p型シリコン層)を形成し、更に、
該半導体層上に絶縁膜(例えば、S i O2膜)を形
成する工程、次いで、該絶縁膜上に支持基板を接着した
後、前記半導体層を除く前記半導体基板をエツチング除
去(例えば、ハロゲンガスを含む光励起エツチング法で
エツチング除去する)する工程が含まれる半導体装置の
製造方法によって達成される。
[Means for Solving Problem c] The purpose is to add a semiconductor layer having an impurity concentration different from the impurity concentration or a different conductivity type to a semiconductor substrate of one conductivity type (for example, an n-type silicon substrate) with a predetermined impurity concentration. forming a type semiconductor layer (e.g., a p-type silicon layer);
A step of forming an insulating film (for example, a SiO2 film) on the semiconductor layer, and then, after adhering a support substrate on the insulating film, the semiconductor substrate except for the semiconductor layer is removed by etching (for example, using halogen gas). This is achieved by a method of manufacturing a semiconductor device, which includes a step of etching away using a photo-excited etching method.

[作用コ 即ち、本発明は、単結晶半導体基板に異質半導体層を形
成した後、その上に絶縁膜を形成し、その絶縁膜に支持
基板を接着する。次いで、半導体基板をエツチング除去
して、異質半導体層を残存させる。このようにして形成
したSo!構造の半導体基板は、結晶品質の良い基板と
なる。
[Operation] In the present invention, after forming a heterogeneous semiconductor layer on a single crystal semiconductor substrate, an insulating film is formed thereon, and a support substrate is bonded to the insulating film. The semiconductor substrate is then etched away, leaving the foreign semiconductor layer. So! formed in this way! A semiconductor substrate with this structure has good crystal quality.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図(al〜(d)は本発明にかかる形成方法の形成
工程順断面図を示しており、まず、同図(a)に示すよ
うに、n+型シリコン基板10(ウェハー)上に、膜厚
1μm程度のp型シリコン層11をエピタキシャル成長
する。このp型シリコン層11はドナー不純物濃度がシ
リコン基板10よりも十分に低いことが必要であるが、
必ずしもp型でなくてもn型層でもよい。
FIGS. 1A to 1D show cross-sectional views in the order of the formation steps of the formation method according to the present invention. First, as shown in FIG. A p-type silicon layer 11 with a thickness of about 1 μm is epitaxially grown. This p-type silicon layer 11 needs to have a donor impurity concentration sufficiently lower than that of the silicon substrate 10.
It does not necessarily have to be a p-type layer, but may be an n-type layer.

次いで、第1図(b)に示すように、約1000〜12
00℃の高温酸化雰囲気中でp型シリコン層11の表面
を加熱して、膜厚0.3μm程度の5i02膜12を生
成する。この高温酸化して生成された5i02膜12は
、絶縁度も良く、界面の結晶欠陥も極めて少ない膜であ
る。
Next, as shown in FIG. 1(b), about 1000 to 12
The surface of the p-type silicon layer 11 is heated in a high-temperature oxidizing atmosphere at 00° C. to form a 5i02 film 12 with a thickness of about 0.3 μm. The 5i02 film 12 produced by this high-temperature oxidation has good insulation and extremely few crystal defects at the interface.

次いで、第1図(C1に示すように、Si○2膜12膜
上2他のシリコン基板または石英基板13(支持基板)
を接着する。接着法は、例えば、5i02膜12上に燐
シリケートガラス (P S G)をCVD法で薄(積
層し、これを溶融して接着する。この燐シリケートガラ
スは900℃程度の低温度で溶融するから、容易に接着
させることができる。また、5i02膜12そのものを
高温度で溶融して接着させてもよい。
Next, as shown in FIG.
Glue. The bonding method is, for example, by layering a thin layer of phosphorus silicate glass (PSG) on the 5i02 film 12 using a CVD method, and then melting and bonding this. This phosphorus silicate glass melts at a low temperature of about 900°C. Furthermore, the 5i02 film 12 itself may be melted at high temperature and bonded.

次いで、第1図(d)に示すように、n+型シリコン基
板10のみをエツチング除去して、p型シリコン層11
を残存させる。そのエツチング法は、ハロゲンを含むガ
ス、例えば、塩素ガスを反応ガスとして用い、反応部に
紫外線を照射するエツチング法、所謂、光励起ドライエ
ツチング法を使用する。
Next, as shown in FIG. 1(d), only the n+ type silicon substrate 10 is removed by etching, and the p type silicon layer 11 is removed.
remain. The etching method uses a halogen-containing gas, such as chlorine gas, as a reaction gas and irradiates ultraviolet rays onto the reaction area, ie, a so-called photoexcited dry etching method.

エツチング条件は、反応チャンバにおけるガス圧を1O
Torr位にして、波長300nm前後の紫外線を強度
300mW/co?で照射し、C12ガス流量を200
m1/分程度流がす。そうすると、約1100n/分の
エツチング速度でn+型シリコン基板10がエツチング
される。しかし、p型シリコン層はエツチング速度が2
桁以上小さいために、p型シリコン層11のみを残存さ
せることができる。
The etching conditions were a gas pressure of 1O in the reaction chamber.
Set the temperature to around Torr and emit ultraviolet light with a wavelength of around 300 nm at an intensity of 300 mW/co? irradiated with C12 gas flow rate of 200
Flow approximately m1/min. Then, the n+ type silicon substrate 10 is etched at an etching rate of about 1100 n/min. However, the etching rate of the p-type silicon layer is 2.
Since it is smaller by more than an order of magnitude, only the p-type silicon layer 11 can remain.

また、このシリコン基板11のエツチングには、その他
に、苛性カリ溶液によるウェットエツチングも可能で、
また、両者を併用しても良い。更に、初期のエツチング
に研磨を適用すれば、エツチング時間が短縮される。
In addition, for etching the silicon substrate 11, wet etching using a caustic potash solution is also possible.
Moreover, both may be used together. Furthermore, if polishing is applied to the initial etching, the etching time will be reduced.

このようにして形成したp型シリコン層11は絶縁膜上
の単結晶薄膜であり、従来のバルク結晶と同等に欠陥が
少なく、品質の高い単結晶シリコン膜である。
The p-type silicon layer 11 thus formed is a single-crystal thin film on an insulating film, and is a high-quality single-crystal silicon film with as few defects as a conventional bulk crystal.

従って、このような単結晶シリコン層11上に半導体素
子を形成すれば、寄生容量が少なく、高品質な素子が作
成される。
Therefore, if a semiconductor element is formed on such a single crystal silicon layer 11, a high quality element with less parasitic capacitance can be produced.

[発明の効果] 以上の説明から明らかなように、本発明によれば最高品
質のSOI構造の基板が得られて、その基板に作成する
半導体装置は性能・品質・信頼性の極めて高いものとな
る。
[Effects of the Invention] As is clear from the above explanation, according to the present invention, a substrate with an SOI structure of the highest quality can be obtained, and a semiconductor device fabricated on the substrate can have extremely high performance, quality, and reliability. Become.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明にがかるSol構造基板
の形成工程順断面図、 第2図は従来のSOS基板の断面図、 第3図(al〜(b)は従来のSOI基板の形成工程順
断面図である。 図において、 1はサファイヤ基板、  2は単結晶シリコン膜、3は
シリコン基板、   4,12は5i02膜、5はl 
晶シリコン膜(アモルファスシリコン膜)又は単結晶シ
リコン膜、 10はn+型シリコン基板、 11はp型シリコン層、 13はシリコン基板または石英基板(支持基板)を示し
ている。 74EMt=カーかasor、 芋)L改し〕Fq7乙
ろnFiTJ−Znl&#@E@ 1 図 従ptq 5osJ茨Δ跡面図 第2圀 社Cう SOユ」七1ミー^罎已fリ ノrン、e\゛
工〉tデ槽JミiaうIC≧り”第3図
Figures 1 (a) to (d) are cross-sectional views of a Sol structure substrate according to the present invention in the order of the formation process, Figure 2 is a cross-sectional view of a conventional SOS substrate, and Figures 3 (al to b) are cross-sectional views of a conventional SOI substrate. 1 is a cross-sectional view of the substrate in the order of forming steps. In the figure, 1 is a sapphire substrate, 2 is a single crystal silicon film, 3 is a silicon substrate, 4 and 12 are 5i02 films, and 5 is l
10 is an n+ type silicon substrate, 11 is a p-type silicon layer, and 13 is a silicon substrate or a quartz substrate (supporting substrate). 74 EMt = car or asor, potato) L revised] Fq 7 Otsuro nFiTJ-Znl &#@E@ 1 Figure following ptq 5osJ Thorn Δ Ruins map 2nd Kokusha C U SO Yu” 71 me ^ 罎已 りノFig. 3

Claims (4)

【特許請求の範囲】[Claims] (1)所定不純物濃度の一導電型半導体基板に、該不純
物濃度とは異なる不純物濃度を有する半導体層、あるい
は、異種導電型の半導体層を形成し、更に、該半導体層
上に絶縁膜を形成する工程、次いで、該絶縁膜上に支持
基板を接着した後、前記半導体層を除く前記半導体基板
をエッチング除去する工程が含まれてなることを特徴と
する半導体装置の製造方法。
(1) A semiconductor layer having an impurity concentration different from the impurity concentration or a semiconductor layer of a different conductivity type is formed on a semiconductor substrate of one conductivity type with a predetermined impurity concentration, and an insulating film is further formed on the semiconductor layer. A method for manufacturing a semiconductor device, comprising the steps of: bonding a support substrate onto the insulating film, and then etching away the semiconductor substrate except for the semiconductor layer.
(2)前記半導体基板がシリコン基板であり、前記絶縁
膜が加熱酸化によつて生成された酸化シリコン膜である
ことを特徴とする特許請求の範囲第1項記載の半導体装
置の製造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate, and the insulating film is a silicon oxide film produced by thermal oxidation.
(3)前記半導体基板がn型シリコン基板であり、前記
半導体層がp型シリコン層であることを特徴とする特許
請求の範囲第1項記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is an n-type silicon substrate, and the semiconductor layer is a p-type silicon layer.
(4)前記半導体基板をエッチング除去するエッチング
方法がハロゲンを含むガス中での光励起エッチング法で
あることを特徴とする特許請求の範囲第1項記載の半導
体装置の製造方法。
(4) The method of manufacturing a semiconductor device according to claim 1, wherein the etching method for etching away the semiconductor substrate is a photoexcitation etching method in a gas containing halogen.
JP1703686A 1986-01-28 1986-01-28 Manufacture of semiconductor device Pending JPS62174969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1703686A JPS62174969A (en) 1986-01-28 1986-01-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1703686A JPS62174969A (en) 1986-01-28 1986-01-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62174969A true JPS62174969A (en) 1987-07-31

Family

ID=11932769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1703686A Pending JPS62174969A (en) 1986-01-28 1986-01-28 Manufacture of semiconductor device

Country Status (1)

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JP (1) JPS62174969A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01106466A (en) * 1987-10-19 1989-04-24 Fujitsu Ltd Manufacture of semiconductor device
JPH0360007A (en) * 1989-07-27 1991-03-15 Fujitsu Ltd Clad sio substrate
JPH06331559A (en) * 1993-05-18 1994-12-02 Hitachi Ltd Method and apparatus for inspection of foreign body

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5451388A (en) * 1977-09-29 1979-04-23 Cho Lsi Gijutsu Kenkyu Kumiai Method of producing semiconductor
JPS5967634A (en) * 1982-10-09 1984-04-17 Mitsubishi Electric Corp Processing method for semiconductor device
JPS6041229A (en) * 1983-08-17 1985-03-04 Fujitsu Ltd Manufacture of semiconductor device and manufacturing equipment thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5451388A (en) * 1977-09-29 1979-04-23 Cho Lsi Gijutsu Kenkyu Kumiai Method of producing semiconductor
JPS5967634A (en) * 1982-10-09 1984-04-17 Mitsubishi Electric Corp Processing method for semiconductor device
JPS6041229A (en) * 1983-08-17 1985-03-04 Fujitsu Ltd Manufacture of semiconductor device and manufacturing equipment thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01106466A (en) * 1987-10-19 1989-04-24 Fujitsu Ltd Manufacture of semiconductor device
JPH0360007A (en) * 1989-07-27 1991-03-15 Fujitsu Ltd Clad sio substrate
JPH06331559A (en) * 1993-05-18 1994-12-02 Hitachi Ltd Method and apparatus for inspection of foreign body

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