JPS6217386B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention is based on I ² L (Integrated Injection Logic).
The present invention relates to a semiconductor integrated circuit that integrates gates.

I ² L is a logic element having a composite structure of a so-called inverted vertical transistor and a lateral transistor complementary to the transistor whose collector is the base of this transistor. In this logic element, the lateral transistor acts as an injector for injecting charge into the base of the inverted vertical transistor, and the inverted vertical transistor operates as an inverter. Therefore, it has recently attracted attention as an element that has a small logic amplitude and can operate at high speed and with low power consumption. Furthermore, since there is no need for isolation between elements, the degree of integration is high, making it suitable for application to large-scale integrated circuits. Furthermore, since I ² L is a bipolar process technology, it can easily coexist with other bipolar circuits, such as linear circuits and ECL circuits, on the same chip, making it possible to realize multifunctional integrated circuits.

Many studies have been conducted on methods for operating such I ² L at high speed. For example, the IEEE Journal of Solids explains the importance of reducing the accumulation time of so-called minority carriers.
State Circuits, Vol.SC―14, No.2, April
1979, pp. 327-336. In order to reduce the accumulation of minority carriers, in addition to optimizing the concentration profile of the epitaxial semiconductor layer and emitter layer, it is effective to minimize the area where minority carriers are accumulated. be. As a method for this, a structure as shown in FIG. 1 can be considered. 1 is a P-type silicon substrate, 2 is an N-type buried layer with high impurity concentration, 3 is an N-type epitaxial layer, 4 is a silicon oxide film, 5 is a P-type region, and 6 is an N-type layer.
A type high impurity concentration region, 7 is polysilicon, 8 is a dielectric, 9 is an oxide film, and 10 is a metal wiring. That is, the I ² L gate is surrounded by the dielectric layer 4, the I ² L collector n ⁺ layer and the dielectric layer 4 are adjacent to each other, and the area of the external base region 5 is minimized.

In such a structure, the low-resistance external base region 5 is divided by the collector region 6, and the charges injected from the injector cannot sufficiently reach the base layer directly under the collector, which is far from the injector. As shown in FIG. 2, a base contact hole 30 is provided adjacent to each collector 6.
The above problem can be solved by forming and interconnecting with metal wiring 10. In this case, the collector
A polysilicon layer 7 is used for the diffusion source of the n ⁺ layer 6 and its interconnection, and is three-dimensionally intersected with the metal interconnection 10 for base contact interconnection. According to this structure, since the base area can be made smaller than the area of the collector 6, the switching time of I ² L can be made faster.

In I ² L having such a structure, the base contact hole 30 can be opened with respect to the polysilicon layer 7 in a self-aligned manner. For example, if we take advantage of the fact that the oxidation rate ratio between the N ⁺ polysilicon layer 7 and the P-type base layer 5 increases at low temperatures, we can first oxidize the entirety at a low temperature and then oxidize the P-type base layer with a relatively thin oxide film. Only the upper part of 5 can be exposed by etching. By the way, the base contact hole 30 area opened by this method is the n ⁺ collector diffusion layer 6,
In particular, if the n ⁺ polysilicon layer and the field part contact the collector layer where they cross, this may cause leakage between the base and the collector, or over-etching while the oxide film in the field part etches the oxide film on the P-type base. Therefore, there is a risk that leakage will occur between the wiring on the P-type base and the n-type epitaxial layer, and this becomes more serious when the P-type base layer is shallow. These are further increased by overetching when opening the base contact hole.

The present invention has been made in view of the above-mentioned points, and is capable of self-aligning the I ² L collector layer diffusion source or the N ⁺ polysilicon used for the collector connection wiring without creating an overlap with the base contact hole. A method for improving I ² L switching speed by reducing the external base region of the I ² L gate by forming a gate electrode to prevent leakage current between the collector base and between the base and the n-type epitaxial layer. This provides a method for manufacturing semiconductor integrated circuits that is a reproducible technique.

The gist of this invention is to form the base contact hole region of the I ² L switching transistor inside the base layer, and to form an n ⁺ collector layer therein via a silicon oxide film obtained by oxidizing the n ⁺ polysilicon layer. , which prevents the metal wiring provided over the opening from coming into contact with the N ⁺ collector layer.

An embodiment of the present invention will be described below with reference to the drawings.

First, as shown in FIG. 3, an N-type high impurity concentration layer 2 and an N-type epitaxial layer 3 are formed on a single-crystal P-type silicon substrate 1, and then a field oxide film 4 that is selectively oxidized is formed. Then, a dielectric layer 8 serving as a diffusion mask is provided, a P-type semiconductor layer 5 serving as an I ² L injector and a base layer is formed by diffusion, and an arsenic-doped polycrystalline silicon layer 7 is selectively provided thereon. .

Next, a cross section of the semiconductor layer 5 (semiconductor region) and polycrystalline silicon layer 7 after oxidation is shown in FIG. This polycrystalline silicon layer 7 is used as a diffusion source for forming the I ² Ln ⁺ collector layer, and is doped with, for example, arsenic of 10 ²¹ /cm ³ or more. Therefore, when wet oxidation is performed at a low temperature, the oxidation rate of the n ⁺ polycrystalline layer 7 can be more than one order of magnitude faster than ^the oxidation rate of the p-type semiconductor layer 5. is 3000Å, and the oxide film thickness on the P-type semiconductor layer 5 is
The thickness can be approximately 300 Å.

Next, as shown in FIG. 5, arsenic is diffused from the arsenic-doped polycrystalline silicon layer 7 to form an n ⁺ I ² L collector layer. A resist mask 11 is formed so as to cover the periphery of the thin oxide film from the PN junction edge formed between the p-type base layer 5 and the N-type epitaxial layer 3 to the surface side of the P-type base layer 5,
By etching the entire oxide film,
As shown in FIG. 6, the thin oxide film on the inner side of the P-type base layer is peeled off, leaving the peripheral portion of the thin oxide film to expose a part of the surface of the P-type base layer. In this etching, the thick oxide film on the surface of the polycrystalline silicon layer 7 is also etched, but remains because of its thickness. FIG. 7 shows the planar pattern of the semiconductor substrate in this step. The N ⁺ polycrystalline silicon layer 7 in this region 12, which is exposed only on the P-type base layer 5, is always covered with a silicon oxide film 9 obtained by oxidizing this N ⁺ polycrystalline silicon.

Next, after only a part of the silicon oxide film of the P-type base layer 5 is peeled off by etching, a metal wiring 10 is connected to the exposed surface of the P-type base, and this metal wiring 10 is further connected to the remaining thick oxide film. It is provided so as to extend onto the polycrystalline silicon layer 7 via the film. That is, this metal wiring 10 is formed on an element region such as a so-called base layer, and contact portions for connection with more wiring can be provided on this element region, which increases the height of the integrated circuit. Helps with densification.

In the above steps, since the contact holes 30 of the formed base layer and injector layer 5 are provided with a margin from the periphery of the base layer, that is,
Because a thin oxide film remains at the periphery of the base layer, the edge of the silicon oxide film in the field area due to the etching process of the silicon oxide film on the base layer, and the intersection between the field and N ⁺ polycrystalline silicon. Occurrence of shorting or leakage current between the I ² L base and collector due to the edges of the silicon oxide film on the N ⁺ polycrystalline silicon layer 7 in the stepped portion, or shorting or leakage between the I ² L base and the N epitaxial layer. Generation of current can be prevented, and I ² L can be manufactured with high yield through this process. FIG. 9 is a power-delay curve of the I ² L ring oscillator produced according to the above embodiment.
The propagation delay speed tpd is a minimum value of 1 nsec or less, which is extremely high compared to conventional I ² L.

As described above, according to the present invention, extremely high-speed I ² L can be manufactured with high yield by preventing shortening between the collector and the base, and between the base and the n-type epitaxial layer.

In the above-described embodiment, after forming a relatively thick oxide film on the N ⁺ polycrystalline silicon 7 and a relatively thin oxide film on the P-type base layer 5 at a low temperature, one layer on the P-type base layer 5 is formed. Although the silicon oxide film is etched off at the top, a dielectric layer, such as a silicon nitride film, may be deposited on the silicon oxide film before the base contact hole 30 is opened. In this case, reliability etc. are improved by using a silicon nitride film. In particular, since the base portion (n-type epitaxial layer 3) of the I ² L lateral pnp transistor is covered with silicon nitride, characteristic deterioration due to impurity contamination of the I ² L lateral pnp transistor, contamination from the package, etc. can be prevented. In the above embodiment, arsenic-doped polycrystalline silicon 7 was used, but polycrystalline silicon doped with other acceptor impurities such as phosphorus may also be used, and the oxidation conditions are not limited to wet oxidation, but may also include dry oxidation, etc. It is also possible to do it with

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the IIL gate, FIG. 2 is a plan view of the same, FIGS. 3 to 8 are sectional views of the IIL gate in each manufacturing process according to an embodiment of the present invention, and FIG. FIG. 3 is a characteristic diagram showing the relationship between the injector current per gate and the propagation delay speed of the IIL gate manufactured according to the invention. 1...P-type silicon substrate, 2...N ⁺ buried layer, 3
...N epitaxial layer, 4...silicon oxide film, 5
...P layer, 6...N ⁺ layer, 7...N ⁺ polysilicon, 8...
Dielectric layer, 9...Silicon and N ⁺ polysilicon oxide film, 10...Metal wiring, 11...Resist.

Claims (1)

[Scope of Claims] 1. A region of an opposite conductivity type is introduced from a part of the surface to the inside of a region where an element is to be formed in a single conductivity type single crystal semiconductor layer, so that a region of an opposite conductivity type exists between these semiconductor layers and the region of the opposite conductivity type. A process of forming a PN junction with an end extending to the surface, and a part of this opposite conductivity type region,
forming a first wiring made of a polycrystalline silicon layer containing impurities of one conductivity type, and oxidizing the surface of the polycrystalline silicon layer and the surface of the opposite conductivity type region,
forming a thick first oxide film on the surface of the polycrystalline silicon layer and forming a thin second oxide film on the surface of the opposite conductivity type region; a step of introducing into a region of opposite conductivity type to form a region of one conductivity type;
The first and second oxide films are etched with a mask applied to a portion of the second oxide film located on the PN junction end, to the extent that a portion of the surface of the opposite conductivity type region is exposed. Remove the second oxide film and remove the first oxide film.
a step of leaving the oxide film; and a step of forming a second wiring connected to the exposed surface of the opposite conductivity type region and extending over the first wiring through the remaining first oxide film. A method for manufacturing a semiconductor integrated circuit, comprising: 2 The first conductivity type semiconductor layer is the emitter of the NPN transistor of the IIL gate, and the opposite conductivity type region is the emitter of the NPN transistor of the IIL gate.
The first conductivity type region forming the base of the NPN transistor and formed in the opposite conductivity type region by diffusion of one conductivity type impurity from the polycrystalline silicon layer forms the collector of the NPN transistor. A method for manufacturing a semiconductor integrated circuit according to claim 1.