JPS6217384B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention is based on I ² L (Integrated Injection Logic).
This invention relates to a semiconductor integrated circuit that integrates gates.
I ² L is a logic element having a composite structure of a so-called reverse structure vertical transistor and a lateral transistor complementary to the transistor whose collector is the base of this transistor.
In this logic element, the lateral transistor acts as an injector that injects charge into the base of the inverted vertical transistor, and the inverted vertical transistor operates as an inverter. Therefore, it has recently attracted attention as an element that has a small logic amplitude and can operate at high speed and with low power consumption. Furthermore, since isolation between elements is not required, the degree of integration is high, making it suitable for application to large-scale integrated circuits. Furthermore, since I ² L is a bipolar process technology, other bipolar circuits such as linear circuits and ECL circuits can easily coexist on the same chip, making it possible to realize multifunctional integrated circuits.

Many studies have been conducted on methods for operating such I ² L at high speed. For example, the IEEE Journal of
Solid-State Circuits, Vol.SC-14, No.2,
April 1979, pp. 327-336.

In order to reduce the accumulation of minority carriers, in addition to optimizing the concentration profile of the epitaxial semiconductor layer and emitter layer, it is effective to minimize the area where minority carriers are accumulated. be. As a method for this, a structure as shown in FIG. 1 can be considered. 1 is a P-type silicon substrate, 2 is an N-type buried layer with high impurity concentration, 3 is an N-type epitaxial layer, 4 is a silicon oxide film, 5 is a P-type region, 6 is an N-type high impurity concentration region, and 7 is polysilicon. , 8 is a dielectric, 9 is an oxide film, and 10 is a metal wiring. That is, the I ² L gate is surrounded by the dielectric layer 4, and the I ² L collector n ⁺ layer 6 and the dielectric layer 4
are adjacent to each other, minimizing the area of the external base region 5.

In such a structure, the low-resistance external base region 5 is divided by the collector region 6, and the charges injected from the injector cannot sufficiently reach the base layer directly under the collector, which is far from the injector. As shown in FIG. 2, a base contact hole 30 is provided adjacent to each collector 6.
The above-mentioned problem is solved by forming and interconnecting with metal wiring 10. In this case, the collector
A polysilicon layer 7 is used for the diffusion source of the n ⁺ layer 6 and its interconnection, and is three-dimensionally intersected with the metal interconnection 10 for base contact interconnection. According to this structure, since the base area can be made smaller than the area of the collector 6, the switching time of I ² L can be made faster.

In I ² L having such a structure, the base contact hole 30 can be opened in a self-aligned manner with respect to the polysilicon layer 7. For example, N ⁺
Taking advantage of the fact that the oxidation rates of the polysilicon layer 7 and the P-type base layer 5 are significantly different at low temperatures, the entire substrate is first oxidized, and then only the P-type base 5, where the oxide film is thin, is etched. can be exposed.
By the way, in this method, the open base contact hole 30 region may come into contact with the n ⁺ collector diffusion layer 6 and cause leakage between the base and the collector. For example, over-etching when opening the base contact hole 30 may be the cause of this.

The present invention has been made in view of the above points, and it forms a base contact hole in self-alignment with the N ⁺ polysilicon used for the I ² L collector layer diffusion source or the collector connection wiring, and the I ² L gate. By minimizing external base area, I ² L
The present invention provides a method for manufacturing a semiconductor integrated circuit that improves reproducibility by preventing leakage current between the collector and the base when improving the switching speed of the semiconductor integrated circuit.

The gist of this invention is that I ² L opened in a self-aligning manner.
For the base contact hole of the gate and the injector layer contact hole, metal is not directly used as the wiring material, but a two-layer structure with a P-type polycrystalline silicon layer on the bottom and metal on the top is used, so that the opened contact hole does not overlap. Even if part of the N ⁺ collector layer is exposed due to etching or the like, leakage or shorting between the I ² L collector and base is prevented by forming a pn junction.

An embodiment of the present invention will be described below with reference to the drawings.

First, as shown in FIG. 3, a P-type silicon substrate 1
An N-type high impurity concentration layer 2 and an N-type epitaxial layer 3 are formed thereon, and a selectively oxidized field oxide film 4 is further formed. Then, a dielectric layer 8 that serves as a diffusion mask is provided, and a P-type semiconductor layer 5 that serves as an I ² L injector and base layer is formed by diffusion, and a polycrystalline silicon layer 7 doped with arsenic is selectively placed on top of the P-type semiconductor layer 5 that serves as an I 2 L injector and base layer. establish.

Next, a cross section of the semiconductor layer 5 and the polycrystalline silicon layer 7 after oxidation is shown in FIG. This polycrystalline silicon layer 7 is used as a diffusion source for forming an I ² Ln ⁺ collector layer, and is doped with, for example, 10 ²¹ /cm ³ or more of arsenic. Therefore, when wet oxidation is performed at a low temperature, the oxidation rate of the n ⁺ polycrystalline layer 7 can be more than one order of magnitude faster than the oxidation rate of the p-type semiconductor layer 5. For example, the film thickness on the n ⁺ polycrystalline layer 7 can be 3000Å, P
The thickness of the oxide film on the type semiconductor layer 5 can be approximately 300 Å.

Next, as shown in FIG. 5, an oxide film etching process is performed to form an opening in a self-aligned manner only on the P-type semiconductor layer 5, which has a thin oxide film thickness. Next, as shown in FIG. 6, a P-type polycrystalline silicon layer 12 doped with boron is provided. Next, as shown in FIG. 7, the polycrystalline silicon 7,
Arsenic and boron are each diffused from 12, and N ⁺
Collector region 6 and P ⁺ base contact region 1
1 is formed. Next, as shown in Figure 8,
A metal layer 10 is provided to form a wiring region. The plan view of the I ² L gate formed by the above process is the second one.
It is similar to the figure. Here, the collector wiring is formed of an n ⁺ polycrystalline silicon layer 7. Note that when connecting this n ⁺ polycrystalline layer 7 and metal wiring layer 10, the P-type polycrystalline silicon layer 1 is connected in advance.
A part of the P-type polycrystalline layer 12 of the two-layer structure of the metal layer 2 and the metal layer 10 may be removed.

In the above process, even if the contact hole to the base layer formed in a self-aligned manner is enlarged by overetching or the like and spreads to the N ⁺ collector region 6, the p ⁺ base contact region 11 is formed of p ⁺ polycrystalline silicon. Since it is formed by impurity diffusion from layer 12, this polycrystalline silicon layer 12
There is no contact with the N ⁺ collector region 6.

Therefore, the occurrence of short or leakage current between the base and collector of I ² L can be prevented, and I ² L integrated circuits can be manufactured with high yield through this process.

FIG. 9 is a power-delay curve of the I ² L ring oscillator made according to the above embodiment. The propagation delay speed t _pd has a minimum value of 1 nsec or less, which is extremely high speed compared to conventional I ² L.

As described above, according to the present invention, extremely high-speed I ² L can be manufactured with high yield by preventing shortening of the collector and base.

In the above embodiment, arsenic-doped polycrystalline silicon is used, but polycrystalline silicon doped with other acceptor impurities such as phosphorus may also be used.
The oxidation conditions are not limited to wet oxidation, but dry oxidation is also possible. The boron-doped P-type polycrystalline silicon layer 12 can be formed by ion-implanting boron into an undoped polycrystalline silicon layer, or directly by boron-doped P-type polycrystalline silicon layer 12.
Either type of polycrystalline silicon layer may be deposited.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the IIL gate, FIG. 2 is a plan view thereof, FIGS. 3 to 8 are sectional views of the IIL gate in each manufacturing process according to an embodiment of the present invention, and FIG. FIG. 3 is a characteristic diagram showing the relationship between the injector current per gate and the propagation delay speed of the manufactured IIL gate. 1...P-type silicon substrate, 2...N ⁺ buried layer, 3
...N epitaxial layer, 4...silicon oxide film, 5
...P layer, 6...N ⁺ layer, 7...N ⁺ polysilicon, 8...
Dielectric layer, 9...Silicon and N ⁺ polysilicon oxide film, 10...Metal wiring, 11...P ⁺ layer, 12...
P ⁺ polysilicon layer.

Claims (1)

[Claims] 1. A step of forming an opposite conductivity type region from a part of the surface to the inside of a region where an element is to be formed in a semiconductor layer of one conductivity type, and including an impurity of one conductivity type in a part of the opposite conductivity type region. A step of forming a first wiring made of a polycrystalline silicon layer, and oxidizing the surface of the polycrystalline silicon layer and the surface of the opposite conductivity type region to form a thick first oxide film on the surface of the polycrystalline silicon layer, and forming a first interconnection of opposite conductivity. forming a thin second oxide film on the surface of the mold region, and removing the second oxide film by etching to the extent that the surface of the opposite conductivity type region is exposed;
a step of leaving the first oxide film; and a step of forming a second wiring having a polycrystalline silicon layer containing impurities of the opposite conductivity type over the exposed surface of the opposite conductivity type region and the remaining surface of the first oxide film. and the first
selectively forming a semiconductor region of one conductivity type and a high impurity concentration region of the opposite conductivity type on the surface of the region of the opposite conductivity type by performing diffusion using each polycrystalline silicon layer of the wiring and the second wiring as a diffusion source; A method for manufacturing a semiconductor integrated circuit, comprising: 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the second wiring has a two-layer structure in which a conductive layer is further provided on a polycrystalline silicon layer. 3. The one conductivity type layer constitutes the emitter of the NPN transistor of the IIL gate, the opposite conductivity type region constitutes the base of the NPN transistor, and the one conductivity type layer is formed by introducing impurities from the polycrystalline silicon layer of the first wiring. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the region constitutes a collector of the NPN transistor.