JPS62172425A - Image processing controlling system - Google Patents

Abstract

PURPOSE:To execute image processing and continuous arithmetic processing between adjoining modules by connecting plural arithmetic modules together with plural image memories by pipeline system and controlling plural switching means in each arithmetic module by switching them. CONSTITUTION:A controlling means 29 supplies controlling signals 27 to each arithmetic module 21. Each arithmetic module 21 is provided with an arithmetic means 31, the first switching means 35 that switches the first input 13 and the second input 15 responding to the first signal 271 in the controlling 27 and makes it arithmetic input 33 of an arithmetic means 31, the second switching means 39 that switches arithmetic output 37 of the arithmetic means 31 and the first input 13 responding to the second signal 272 and makes it the first output 17, and the third switching means 41 that switches arithmetic output 37 and the second input 15 responding to the third signal 273. Thus,the state of switching means 35, 39 and 41 is determined by the controlling signals 27 as the whole constitution, and image processing is made by pipeline system of optional combination of plural arithmetic modules according to the state.

Description

[Detailed Description of the Invention] [Table of Contents] Page Overview/
・・・・・・・・・・・・・・・・・・5 Industrial application fields・・・・・・・・・・・・・6 Conventional technology・・・・・・・・・・
...6 Problems that the invention attempts to solve...
・Means for solving the 8 problems...9■, Structure of the first invention...10■, Structure of the second invention...11 Effects・・・・・・・・・・・・・・・
...13■, First invention...13■
, Second invention......15 Examples of the invention
・・・・・・・・・・・・18■, 1st example・・・・・・
・・・・・・18■, 2nd example・・・・・・・・・・2
3. Effects of the invention 34 [Summary] An image processing control system that uses a plurality of calculation modules each having a calculation function and a plurality of input/output switching means. By connecting with memory in a pipeline system and controlling multiple switching means in each calculation module, the calculation function of the calculation module can be activated or skipped, and multiple calculation modules can be freely controlled. Pipeline image processing by combination and continuous arithmetic processing between adjacent modules are possible.

[Industrial application field]

The present invention relates to an image processing control method, and particularly to an image processing control method in which a plurality of modules are connected in a pipeline manner to process image data.

[Conventional technology]

For example, in the field of arithmetic processing, the amount of data handled is extremely large, and frame memory type, parallel processor type, etc. have been proposed and put into practical use as processing methods. This allows large amounts of data to be processed at high speed and with high efficiency. However, this method is not necessarily suitable for large-scale images because it requires a large amount of memory and becomes expensive.

FIG. 18 is a schematic diagram of an image processing device that can process images at high speed. Generally, the image memory 5L and the plurality of calculation modules 53A, B, . . . , N are connected to a dedicated bus 5.
5, and calculations are performed by transferring image data between them. However, even if multiple calculation modules are provided, they cannot be activated at the same time, and the image memory 51 → calculation module 53
→Computation is performed for each unit such as the image memory 51.

That is, as shown in FIG. 19, image data read from the image memory 51 is input to the calculation module 53A via the read bus 55R, and
The processing result at A is re-stored in the image memory 51 via the write bus 55W. When performing subsequent processing, the image data stored therein is read out from the image memory 51 again and processed by another arithmetic module 53B, and the processing results are stored again. That is, since one calculation module performs only one calculation, reading, calculation, and storage are repeated.

In addition, as shown in FIG. 20, image processing is performed in a pipeline manner based on a plurality of modules, such as image memory 5■ = calculation module 53A → calculation module 53B →... It has become.

In this example, two arithmetic modules 53A and 53B are used to perform two stages of processing, so three buses 57
is needed.

[Problem that the invention seeks to solve]

However, as for the connection relationships shown in FIGS. 18 and 19, an image data bus is required between the image memory 51 and the plurality of calculation modules 53, even if the image processing control method allows high-speed processing using hardware. 55, operations on images can only be performed one by one, and it is difficult to perform continuous processing on two or more images.

Therefore, it is possible to perform two or more consecutive processes by connecting each processing module via multiple buses, but as the number of stages increases, the number of buses increases and the scale of the device becomes extremely large. There was a problem with it getting stuck. In addition, the order of processing operations in a pipeline method using multiple processing modules is fixed, and if you want to perform the processing in an arbitrary order, it is necessary to connect all the processing modules with each other using a "star join." This results in an extremely large number of connection buses, which increases the size of the device.

The present invention was created in view of the above points, and connects a plurality of arithmetic modules and an image memory so that image processing can be performed in a pipeline manner, and connects a plurality of arithmetic modules and an image memory so that image processing can be performed in a pipeline manner. Continuous processing is 1
The purpose of the present invention is to provide an image processing control method that can be activated in one go, and also reduces the number of buses and reduces the size of the device.

[Means for solving problems]

FIGS. 1A and 1B are block diagrams of the principle of the image processing control system according to the present invention.

(2) Configuration of the First Invention In FIG. 1(A), the image memory 11 is capable of writing and reading image data.

Each of the plurality of calculation modules 21 has a first input 13
and a second input 15, a first output 17, and a second output 19.

Between the plurality of calculation modules 21, the first
The input 13 and the second output 19 are connected to the first output 17 and the second input 15 of the previous stage, and the first output 17 and the second input 15 are connected to the first input 13 and the second output 19 of the latter stage, respectively. , the read output 23 and write input 25 of the image memory 11 are connected to the first input 13 and second output 19 of the first-stage arithmetic module 21, thereby providing a pipeline processing means.

The control means 29 supplies each arithmetic module 21 with a control signal 27 consisting of at least a first signal 271, a second signal 272, and a third signal 273.

Each calculation module 21 includes a calculation means 31, a control signal 2
The first switching means 35 switches between the first input 13 and the second input 15 in response to the first signal 271 in 7 and serves as the calculation input 33 of the calculation means 31;
A second switching means 39 switches between the first calculation output 37 and the first input 13 to become the first output 17, and switches between the calculation output 37 and the second input 15 in response to the third signal 273, and A third switching means 41 is provided.

Therefore, in the overall configuration, the states of the switching means 35, 39 and 41 are determined by the control signal 27 from the control means 29, and image processing by an arbitrary combination of pipeline methods in the plurality of calculation modules 21 is performed according to the state. It is supposed to be done.

(2) Configuration of the Second Invention In FIG. 1(B), the image memory 11 is capable of writing and reading image data.

Each of the plurality of calculation modules 21 has a first input 13
and a second input 15, a first output 17, and a second output 19.

Between the plurality of calculation modules 21, the first
The input 13 and the second output 19 are connected to the first output 17 and the second input 15 of the previous stage, and the first output 17 and the second input 15 are connected to the first input 13 and the second output 19 of the latter stage, respectively, The first input 13 of the first stage calculation module 21. The second output 19 and the first output 17 and second input 15 of the final stage arithmetic module 21 are disabled, and the read output 23 and write input 25 of the image memory 11 are connected to all the arithmetic modules 21 in a bus format. When connected, it becomes a pipeline processing means.

The control means 29 supplies each arithmetic module 21 with a control signal 27 consisting of at least a first signal 271, a second signal 272, and a third signal 273, and an energizing signal 43.

Each calculation module 21 includes a calculation means 31, a control signal 2
a first switching means 35 that switches between the first input 13 and the second input 159 and the readout output 23 of the image memory 11 in accordance with the first signal 271 in 7, and sets it as the calculation input 33 of the calculation means 31;
The calculation output 37 of the calculation means 31 in response to the second signal 272.
A second switching means 39 switches the first input 13 to the first output 17 , and a calculation output 37 according to the third signal 273 . Second
Input 15. A third switching means 41 switches the first input 13 to the second output 19, and a calculation output 3 is generated by the energizing signal 43.
An output means 45 is provided for determining whether or not 7 is to be used as the write input 25 of the image memory 11.

Therefore, in the overall configuration, the states of the switching means 35, 39 and 41 are determined by the control signal 27 from the control means 29, and image processing by an arbitrary combination of pipeline methods in the plurality of calculation modules 21 is performed according to the state. It is supposed to be done.

[For production]

(2) First invention (see FIG. 1(A)) The switching states of the switching means 35, 39 and 41 in the arithmetic module 21 are determined according to the control signal 27 supplied from the control means 29.

The readout output 23 from the image memory 11 is first supplied to the first input 13 of the first-stage arithmetic module 21, and the first
The first output 1 is switched by the switching means 35 and the second switching means 39.
If 7 is selected, the corresponding calculation module 21 is skipped.

In the first switching means 35 of the arithmetic module 21 at a certain stage,
If the first input 13 is selected to be the calculation input 33 of the calculation means 31, the calculation means 31 performs the calculation based on the readout output 23 from the image memory 11.

The calculation output 37 is supplied by the second switching means 39 to the first input 13 of the calculation module 21 at the next stage. Alternatively, depending on the switching state of the third switching means 41, the signal is returned as the second input 15 of the arithmetic module 21 at the previous stage.

In addition, the second input 15 of the calculation module 21 may become the second output 19 and be passed to the previous stage calculation module 21 as it is (skip), but the calculation input 3
3 and is supplied as the computation input 33 of the computation means 31, and its computation output 37 may be supplied as the second output 19 to the preceding stage computation module 21.

In this way, the calculations of the calculation means 31 in the calculation modules 21 that are not skipped are performed sequentially, and calculation processing is performed in an arbitrary combination of calculation modules 21 in a pipeline method, and the processed image data is stored in the image memory 1.
It becomes a write input 25 of 1 and is written again.

In the first invention, there are a plurality of arithmetic modules 21 connected so as to perform pipeline image processing, and by appropriately switching the switching means included in the arithmetic modules 21, any of the arithmetic modules 21 can be selected. Pipeline image processing is possible through combinations.

(2) Second invention (see FIG. 1(B)) The switching states of the switching means 35, 39 and 41 in the arithmetic module 21 are determined according to the control signal 27 supplied from the control means 29.

A readout output 23 from the image memory 11 is supplied to all calculation modules 21.

If the first input 13 is selected as the first output 17 by the first switching means 35 and second switching means 39 of the calculation module 21, the calculation module 21 is skipped.

The first switching means 35 of the arithmetic module 21 at a certain stage causes the first input 13. One of the second input 159 and the readout output 23 of the image memory 11 is selected. If the readout output 23 is selected to be the calculation input 33 of the calculation means 31, the calculation means 31 performs calculation based on the readout output 23 from the image memory 11.

The calculation output 37 is changed to the first input 1 of the next stage calculation module 21 depending on the switching selection state of the second switching means 39.
3. Alternatively, depending on the switching state of the third switching means 41, the signal is returned as the second input 15 of the arithmetic module 21 at the previous stage, or is outputted to the outside via the output means 45 energized according to the energizing signal 43.

Depending on the switching state of the third switching means 41, the calculation module 2
The second input 15 of 1 becomes the second output 19 and is passed as is to the calculation module 21 at the previous stage (skip), but it becomes the calculation input 33 and is passed to the calculation means 31 as it is.
The calculation output 37 may be supplied as the second output 19 to the preceding calculation module 21. Further, the calculation output 37 may be selected by the third switching means 41 so as to become the second output 19.

In this way, the calculation module j1 that is not skipped. -Le 2
The calculations of the calculation means 31 of 1 are performed sequentially, the calculation processing of the pipeline method is performed by the calculation modules 21 of arbitrary combinations, and the image data after the final processing by the calculation modules 21 is outputted via the output means 45. obtained by
It becomes the write input 25 of the image memory 11 and is written again.

Also in the second invention, there are a plurality of arithmetic modules 21 connected so as to perform pipeline image processing, and by appropriately switching the switching means included in the arithmetic modules 21, any of the arithmetic modules 21 can be selected. Pipeline image processing is possible through combinations.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below based on the drawings.

(2) First Embodiment FIG. 2 shows a connection state of an image processing control system according to an embodiment of the present invention.

In the figure, image data is written to the image memory 61 in response to a write signal 63W, and stored image data is read out in response to a read signal 63R. Also,
A plurality of calculation modules 65A, B, C, . . . are connected to the image memory 61 so as to sequentially process the image memory 61. This enables pipeline-based image processing.

In the figure, the calculation module 65 has two input inputs and two output outputs for image data, and each can be connected one-to-one with the left and right calculation modules to perform pipeline processing. ing. In this case, it is desirable that the arithmetic modules be arranged so that the arithmetic module closest to the image memory is at the top (initial stage).

FIG. 3 shows the internal configuration of each calculation module shown in FIG. 2.

In FIG. 3, the calculation module 65 is composed of a calculation unit 67 having one input terminal and one output terminal, three multiplexers (MPX) 69, 71 and 73, and an external control circuit (not shown). ), two input cuffs 7.79 and two output cuffs 8.
1.83 can be selected. This calculation module 65 can be set to the following three modes.

(1) Data path (first mode) of first person's cuff 7 → calculation unit 67 → first output 81 and second person's cuff 9 - second output 83 (first mode) In other words, the multiplexer 69 is activated by the control signal 751 to is selected and used as the calculation data input 85 to the calculation section 67. The calculation data output 87 from the calculation unit 67 is
It is selected by the multiplexer 71 in response to the control signal 752 and outputted to the outside as the first output 81. Further, the second person's cuff 9 is selected by the control signal 75.3, and the second person's cuff 9 is selected by the control signal 75.3.
It is outputted to the outside as an output 83.

(2) First person cuff 7 - first output 81 and second person cuff 9 -
Data path from calculation unit 67 to second output 83 (second mode) The first person's cuff 7 is selected by the multiplexer 71 and becomes the first output 81 . Also, the second person cuff 9 is connected to the multiplexer 6
9 is selected and becomes the calculation data input 85 and is sent to the calculation section 67.
supplied to The calculated data output 87 of the calculation unit 67 is selected by the multiplexer 73 and becomes the second output 83.
(3) Data path of the first person's cuff 7 - calculation section 67 - second output 83 (third mode) The first person's cuff 7 is selected by the multiplexer 69, becomes the calculation data input 85 of the calculation section 67, and its The calculation data output 87 is selected by the multiplexer 73 and the second output 83
becomes.

The case where the three mode-set calculation modules 65A-C perform continuous processing in this manner is shown in FIGS. 4(a) to 4(C). In the case of (a) in the figure, the processing order is image memory 61 - first calculation module 65A = second calculation module 65B -> third calculation module 65C -> image memory 61, and first calculation module 65A and second calculation module 65B. is in the first mode, and the third calculation module 65C is in the third mode. With this, image memo I
After reading the stored image data of J61 and sequentially processing it in the first calculation module 65A to third calculation module 65C, the processed image data is stored in the image memory 61 by skipping the second calculation module 65B and the first calculation module 65A. Write again.

The processing order in FIG. 6(b) is image memory 61 - third calculation module 65C - second calculation module 65B → first calculation module 65A → image memory 61, and both the first calculation module 65A and the second calculation module 65B Second
mode, the third calculation module 65C is in the third mode. As a result, the image data from the image memory 61 is first transferred to the first calculation module 65A and the second calculation module 65A.
B is skipped and processed in the order of the third calculation module 65C, second calculation module 65B, and first calculation module 65A, and then written to the image memory 61 again.

Furthermore, the processing order in FIG.
Arithmetic module 65B=third arithmetic module 65C-first arithmetic module 65A-image memory 61;
The calculation module 65A is in the second mode, the second calculation module 65B is in the first mode, and the third calculation module 65C is in the third mode. As a result, the image data read from the image memory 61 first skips the first calculation module 65A and is processed by the second calculation module 65B.
Thereafter, the data is sequentially processed by the third calculation module 65C and the first calculation module 65A, and rewritten into the image memory 61.

By the way, in order to perform the image processing as shown in FIGS. 4(a) to 4(c), the readout signal 63R of the image memory 61 is supplied to the first person's cuff 7 of the first calculation module 65A, and the first person's cuff 7 of the first calculation module 65A is
It is necessary to make the output data of the second output 83 of the calculation module 65A the write signal 63W. As a result, the image memory 6 is connected as shown in FIG.
1 → first calculation module 65A → second calculation module 6
5B--Third arithmetic module 65C→... image processing is possible.

(2) Second Embodiment FIG. 5 shows another embodiment of the present invention. Here, the image memory 91 and the plurality of calculation modules 95A-D are connected by an image data bus 93, which is a common bus. Also,
The arithmetic modules are connected to each other by a local bus 97, which enables pipeline processing.

FIG. 6 specifically shows the configuration of the arithmetic module 95 shown in FIG. Here, an arithmetic unit 111 having one input terminal and one output terminal and three multiplexers 113 and 115
and 117 and one output gate 119. It is assumed that a selection control signal for controlling a multiplexer (not shown) is supplied and applied to each corresponding multiplexer.

The arithmetic module 95 at a certain stage uses a multiplexer 113 to switch and select the first input 121 to which the first output of the preceding arithmetic module is introduced, the second input 123 to which the second output of the subsequent arithmetic module is introduced, and the read bus 93R. The image data input 125 is supplied to the calculation unit 111. Calculation data output 127 of this calculation unit 111. The first input 121 and the second input 123 are switched and selected by the multiplexer 115 and output as the first output 129.

In addition, the multiplexer 117 has a calculation data output 127
．． First input 121. and the second input 123 are switched and selected and outputted as the second output 131.

Further, the output gate 119 outputs the write bus 9 of the calculation data output 127 of the calculation unit 111 depending on the state of the energizing signal 133.
Controls output to 3W.

Note that the first output 129 is connected to the first input 121 of the subsequent-stage calculation module, and the second output 131 is connected to the second input of the previous-stage calculation module.
are connected to inputs 123, respectively. Adjacent arithmetic modules are connected to each other by a local bus 97.

In the configuration shown in FIG. 6, each arithmetic module 95 has various operating states (modes) depending on the selection control states of the three multiplexers 113, 115 and 117, which will be discussed below.

(1) First mode This is a mode in which calculations are performed based on data from the lead bus 93R and the processed data is output to the write bus 93W.

That is, as shown in FIG. 7, the multiplexer 113 selects the read bus 93R, and
The data of 3R becomes the calculation data input 125 and is sent to the calculation unit 1.
11. Calculated data output 1 after the calculation process
27, when the output gate 119 is activated, the write bus 9
Output to 3W.

(2) Second mode This is a mode in which the data on the read bus 93R is processed and then output as the first output 129, and the second input 123 is output as the second output 131 as is.

That is, as shown in FIG. 8, the read bus 93R is selected by the multiplexer 113 and the calculation data input 12 is
5 to the arithmetic unit 111, and the multiplexer 115
The calculated data output 127 is selected as the first output 129. Further, the multiplexer II7 selects the second input 123 and makes it the second output 131, thereby skinning the present calculation module 95.

(3) Third mode In this mode, the data of the read path 93R is processed and the second
This is a mode in which the output is 131 and the first input 121 is directly the first output 129.

That is, as shown in FIG. 9, the multiplexer 113 is selected so that the data on the read bus 93R becomes the calculation data input 125, and the calculation data output 127
is selected by the multiplexer 117 to be the second output 131. Also, the multiplexer 115 is switched and selected so that the first input 121 passes.

(4) Fourth mode In this mode, the data of the first input 121 is processed, the processed data is used as the first output 129, and the second input 123
This is a mode in which the second output 131 is used as is.

That is, as shown in FIG. 10, the multiplexer 113 is selected so that the first input 121 becomes the calculation data input 125, and the calculation data output 127 of the calculation section 111 is selected by the multiplexer 115 so that it becomes the first output 129. do. Further, the multiplexer 117 is switched and selected so that the second input 123 passes.

(5) Fifth mode In this mode, the data of the second input 123 is processed, the processed data is used as the second output 131, and the first input 121
This is a mode in which the first output 129 is used as is.

That is, as shown in FIG. 11, the multiplexer 113 is selected so that the second input 123 becomes the calculation data input 125, and the calculation data output 127 of the calculation section 111 is selected by the multiplexer 117 so that it becomes the second output 131. do. Also, the multiplexer 115 is switched and selected so that the first input 121 passes.

(6) Sixth mode This is a mode in which arithmetic processing is performed based on the data of the second input 123 and the processed data is used as the first output 129.

That is, as shown in FIG. 12, the multiplexer 113 is selected so that the second input 123 becomes the calculation data input 125, and the calculation data output 127 of the calculation section 111 is selected by the multiplexer 115 so that it becomes the first output 129. do.

(7) Seventh mode This is a mode in which calculation processing is performed based on the data of the first input 121 and the processed data is used as the second output 131 of the calculation module 95.

That is, as shown in FIG. 13, the multiplexer 113 is switched so that the first input 121 becomes the calculation data input 125, and the multiplexer 117 is switched so that the calculation data output 127 becomes the second output 131. .

(8) Eighth mode This is a mode in which arithmetic processing is performed based on the data of the first input 121, the processed data is output to the light path 93W, and the second input 123 is directly used as the second output 131. .

That is, as shown in FIG. 14, the first input 121 is used as the calculation data input 125, and the calculation data output 127 is output to the write bus 93W. Further, the second input 123 is set as the second output 131.

(9) Ninth mode This is a mode in which arithmetic processing is performed based on the data of the second input 123, the processed data is output to the write bus 93W, and the first input 121 is directly used as the first output 129.

In other words, as shown in FIG.
The second input 123 is supplied to the calculation section 111 as the calculation data input 125, and the calculation data output 127 is outputted to the write bus 93W by the output gate 119.

(10) 10th mode In this mode, the first input 121 is directly sent to the first output 129,
This is also a mode in which the second input 123 is passed as is to the second output 131 and no calculations are performed.

In other words, as shown in FIG.
The multiplexer 115 is switched so that the output 129 becomes the output 129, and the multiplexer 117 is switched so that the second input 123 becomes the second output 131. As a result, this calculation module 95 is skipped.

Each calculation module 95 can take the above modes (first mode to tenth mode), and in the embodiment shown in FIG. 5, the second calculation module 95B and the third
All modes of operation described above apply to calculation module 95C. However, the first stage first calculation module 95A
does not have the first input 121 and second output 131 (invalidated), and the fourth calculation module 95D at the final stage does not have the first output 129 and second input 123 (invalidated), so all the above modes does not apply, and mode operations related to these missing inputs and outputs are not performed.

Referring again to FIG. As shown in the figure, there are various combinations when four calculation modules 95 are connected. For example, one stage of processing using one calculation module, or three stages of processing using three calculation modules, etc.
Systems based on various numbers of stages are possible.

FIG. 17 shows an example of performing arithmetic processing with different numbers of stages by changing the number of operating arithmetic modules.

Figure (a) shows the case where one calculation module is used (
1 step). Further, both (b) and (c) of the same figure are cases in which three calculation modules are used (three stages).

In the case shown in FIG. 17(a), all calculation modules 95 are set to the first mode shown in FIG. 7 by a control signal (not shown) from a control circuit (not shown). The multiplexers 113, 115 and 117 are switched and selected. As a result, the image data read from the image memory 91 is calculated by the calculation module 95 +a
After being processed in B111, it is stored again in the image memory 91.

In the case of FIG. 17(b), the first calculation module 95A
is in the second mode as shown in FIG. 8, the second calculation module 95B is in the fourth mode as shown in FIG.
The multiplexers 113, 115 and 11 are connected so that the calculation module 95C is in the eighth mode as shown in FIG.
Switch 7. As a result, the first calculation module 9
5A→second calculation module 95B-third calculation module 95C are sequentially calculated by these calculation units 111, and the image data obtained thereby is stored in the image memory 91.
will be restored.

In the case of FIG. 17(C), the first calculation module 95A is set to the ninth mode (see FIG. 15), the second calculation module 95B is set to the fifth mode (see FIG. 11), and the third
The calculation modules 95C are respectively switched to the third mode (see FIG. 9). As a result, the image data from the image memory 91 is sequentially calculated by the calculation unit 111 of the third calculation module 95C → second calculation module 95B = first calculation module 95A, and the image data that is the calculation result is stored in the image memory 91 again. written.

In addition to this, there are processing methods in which input and output directions of each calculation module 95 are selected and various combinations are used, but these are omitted here.

In this manner, by appropriately selecting the mode of each of the plurality of calculation modules 95, it is possible to perform image processing in a pipeline system using various combinations in the plurality of calculation modules 95.

〔Effect of the invention〕

As described above, according to the present invention, each arithmetic module having an arithmetic function is provided with a switching selection means to select the direction of data input to perform the arithmetic function and to select the direction of data input after the arithmetic operation. Select the direction and
In addition, it is configured to perform data busing (skipping), making it possible to perform pipeline processing using any combination of multiple processing modules without increasing the size of the device configuration. It is extremely useful.

[Brief explanation of drawings]

Figures 1 (A) and (B) are principle block diagrams of the image processing control system of the present invention, Figure 2 is a connection relationship diagram showing the configuration of the image processing control system according to an embodiment of the present invention, and Figure 3 is a A configuration block diagram specifically showing an arithmetic module in an embodiment of the present invention, Figures 4(a) to (c) are system diagrams for explaining the operation in an embodiment of the present invention, and Figure 5 is a system diagram of the present invention. FIG. 6 is a configuration block diagram specifically showing the calculation module shown in FIG. 5, and each of FIGS. 7 to 16 shows the calculation shown in FIG. 6. A mode diagram showing the operation of the module by mode, FIG. 17(a) ~
(c) is a system diagram showing the processing order in various operation modes in Fig. 5, and Figs. 18 and 19 are connection diagrams showing the state in which multiple conventional calculation modules are connected to the image memory via a dedicated bus. , FIG. 20 is a connection diagram showing the connection relationship between an image memory and a plurality of arithmetic modules for performing processing operations in a conventional pipeline system. In FIGS. 1A and 1B, 11 is an image memory, 21 is an arithmetic module, 27 is a control signal, and 35, 39, and 41 are switching means. 2 to 20, 51.61.91 is an image memory, 53A to N, 65.65A NC, 95, 95A to D are arithmetic modules, 55R and 93R are read buses, 55W and 93W are write buses, 67.111 is an arithmetic unit, 69.71, 73, 113, 115, 117 is a multiplexer, 75 is a control signal, 77.121 is a first input, 81.129 is a first output, 79.123 is a second input, 83 and 131 are second outputs, 97 is a local bus, and 119 is an output gate. Patent Applicant: Fujitsu Ltd.Principle block diagram of the first invention Fig. 1 (A) Principle block diagram of the second invention Explanatory diagram of the embodiment Fig. 2 Control signal 75 Configuration block diagram of the arithmetic module Third drawing image data Figure 5: Configuration block diagram of the calculation module Figure 6: Operational diagram of the calculation module Figure 7: Operational explanation of the calculation module Figure 10: Operational diagram of the calculation module Figure 11: Operation of the calculation module Explanatory diagram M! E 1m mv Operational diagram of the calculation module #A14 Figure 15 Operational diagram of the calculation module Explanation of processing order Figure 17

Claims (2)

[Claims] (1) An image memory (11) in which image data can be written and read, each having a first input (13), a second input (15), a first output (17), and a second output (19). a plurality of arithmetic modules (21) having a plurality of arithmetic modules (21);
21), the first input (13) and second output (19) of a certain stage are connected to the first output (17) and second input (15) of the previous stage, and the first output (17) and second output (15) of the previous stage are connected to each other. The input (15) is connected to the first input (13) and second output (19) of the subsequent stage, respectively, in multiple stages, and the read output (23) and write input (23) of the image memory (11).
25) is the first stage arithmetic module (21) first input (13
) and a second output (19), and at least the first, second and third signals (2
71, 272, and 273) for supplying a control signal (27) to each arithmetic module (21); and an arithmetic means (31) included in each arithmetic module (21).
, a first switching means (1) that switches between the first input (13) and the second input (15) in accordance with the first signal 271 in the control signal (27), and sets the first input (13) and the second input (15) as the calculation input (33) of the calculation means (31). 35
), the calculation output (37) of the calculation means (31) and the first input (13) are switched according to the second signal (272), and the first
The second switching means (39) outputs (17), the third signal (
273), the calculation output (37) and the second input (15)
a third switching means (
41); An image processing control method characterized by comprising: (2) An image memory (11) in which image data can be written and read, each having a first input (13), a second input (15), a first output (17), and a second output (19). a plurality of arithmetic modules (21) having a plurality of arithmetic modules (21);
21), the first input (13) and second output (19) of a certain stage are connected to the first output (17) and second input (15) of the previous stage, and the first output (17) and second output (15) of the previous stage are connected to each other. The input (15) is connected to the first input (13) and the second output (19) of the subsequent stage, respectively, in multiple stages, and the first input (13) and the second output ( 19) and the first output (17) and second input (15) of the final stage arithmetic module (21) are disabled, and the read output (23) and write input (2) of the image memory (11) are disabled.
5) is a pipelined processing means connected to all the arithmetic modules (21) in the form of a bus, and a control signal (27) comprising at least first, second and third signals (271, 272 and 273); , energizing signal (43
) to each arithmetic module (21).
9) and calculation means (31) included in each calculation module (21).
, the first input (13), the second input (15), and the image memory (11) according to the first signal (271) in the control signal (27).
) by switching the readout output (23) of the calculation means (31).
), the first switching means (35) switches the calculation output (37) of the calculation means (31) and the first input (13) according to the second signal (272) to output the first output. (1
7) second switching means (39) and third signal (273)
A third switching means (41) switches the calculation output (37), the second input (15), and the first input (13) to the second output (19) according to (
37) as a write input (25) of an image memory (11).