JP2007188249A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of increasing the processing speed of the whole system to a high speed approaching the processing speed of hardware by suppressing a wasteful use of a data bus. <P>SOLUTION: The multiprocessor system is constituted so that a system control processor is connected to a program memory and connected to a main memory in common together with a plurality of M units through the data bus. Each of the plurality of M units comprises a bus I/F 202 based on a DMAC for reading out data from the main memory through a data input port 201 and outputting a final processing result from a data output port 204 to the main memory and a plurality of P units 211, 212 or 221, 222 for independently executing prescribed processing for input data in each unit and outputting a finally obtained processing result to the bus I/F 202. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system having a configuration in which a plurality of processors are connected to a common main memory via a data bus.

  In data processing that handles enormous (image) data, such as image processing, the processor divides the data into several processing blocks and sequentially performs processing for each block. This is shown in FIG. When the processor needs to sequentially process four processing blocks to output the final result, the processor sequentially processes the four processing blocks P0, P1, P2, and P3 as shown in FIG. Get the final processing result. Each processing block P0 to P3 performs processing for each necessary data.

  In the case of image data processing, processing units are pixels, lines, blocks, and the like. Assuming that the data group of the processing unit is GD0, GD1, GD2,..., The data group processed by each processing block with the passage of time can be ideally processed as shown in FIG. However, the value of the target data is changed by the previous processing. Since each process is performed in parallel, the process of the unit process data ends at the process interval of the process that takes the longest processing time in the process blocks P0 to P3. In order to obtain such an ideal processing speed, the processing cannot be realized without hardware.

  In the case of software processing by the processor, each process cannot be performed in parallel in time. Therefore, as shown in FIG. 9, after processing units of data are sequentially processed in the order of processing blocks P0, P1, P2, and P3. Similarly, the next unit processing data is sequentially processed in the order of the processing blocks P0, P1, P2, and P3. As can be seen from FIG. 9, in the software processing by the processor, the total of the four processing times is taken to process the unit processing data, and therefore the cause of the overwhelmingly lower processing speed than the hardware to be processed as shown in FIG. Become.

  FIG. 10 is a flowchart for explaining the operation of an example when the processor advances the processing. As shown in the figure, data to be processed is read from the main memory (step S1), for example, processing of the processing block P0 is performed (step S2), and the processing result is temporarily stored in the main memory (step S3). Subsequently, the processing result of P0 stored in the main memory is read (step S4), the processing of the next processing block P1 is executed (step S5), and the processing result is temporarily stored in the main memory (step S6). ). Thereafter, the above-described processing is repeated in the same manner as many as necessary processing blocks to obtain the final result. In this way, when the processing is taken over, access to the main memory occurs.

  By the way, the above is a description of processing by a single processor, but a multiprocessor system in which a plurality of processors are combined for the purpose of improving performance and reliability has been conventionally known (for example, see Patent Document 1). . 11 shows n central processing units (CPUs) 11-1, 11-2,..., 11-n and m or more digital signal processors (DSPs) 12-1,. A plurality of processors such as −m are connected to the main memory 13 in common via the data bus 14 (that is, the main memory 13 is shared).

  The operation of the conventional multiprocessor system shown in FIG. 11 will be described with reference to the flowchart of FIG. First, since the CPU 11-1 performs processing, data necessary for processing is read from the main memory 13 (step S11), the CPU 11-1 processes this data (step S12), and the processing result is stored in the main memory 13. Write (step S13).

  Subsequently, in order for the CPU 11-2 to process the processing result of the CPU 11-1, the CPU 11-2 reads the processing result of the CPU 11-1 stored in the main memory 13 from the main memory 13 (step S14). -2 processes this data (step S15) and writes the processing result in the main memory 13 (step S16). In the same manner, the CPU 11-n processes data in the same manner as described above.

  Since the DSPs 12-1 to 12-m also perform processing in the system, the DSP 12-1 first reads data from the main memory 13 (step S17) and processes the data in the same manner as the CPUs 11-1 to 11-n. (Step S18), the processing result is written in the main memory 13 (Step S19). The other DSPs 12-2 to 12-m perform the same operation.

Japanese Patent Publication No.6-1463

  Incidentally, in a processor-oriented data processing system, one of the causes that the processing speed is inferior to that of hardware is a bus problem. Processor buses are broadly divided into instruction buses and data buses, but the data bus contains local data (stack and temporary storage data) in addition to processing data, and has one data access compared to a pure hardware processing system. Easy to concentrate on.

  That is, in the conventional multiprocessor system shown in FIG. 11, which is a parallel / distributed processing system (memory sharing system) using multiprocessors, the CPUs 11-1, 11-2,. In steps S11, S13, S14, S16, S17, S19, etc. in FIG. 12, the main memory 13 is accessed, and data access is concentrated on one data bus 14, and the large number of CPUs and DSPs is large. This problem appears more prominently in the system and the bus traffic gets worse.

  The present invention has been made in view of the above points, and provides a multiprocessor system capable of suppressing the use of a useless data bus and realizing the high processing speed of the entire system approaching the hardware processing speed. With the goal.

In order to achieve the above object, the present invention has a configuration in which a first processor for system control is connected to a first program memory and is commonly connected to a main memory through a data bus together with a plurality of units. Each of the plurality of units reads data from the main memory via the first data input port according to a processing start command from the first processor, and displays the final processing result as the first processing result. The first bus interface by the direct memory transfer controller that outputs to the main memory from the data output port and data input via the first bus interface are subjected to predetermined processing independently for each unit. A plurality of processing results connected to output the final processing result to the first bus interface. And a present unit, the number and mutual connection method identical to each other or a part or all different configurations of the basic unit,
Each of the plurality of basic units includes a second bus interface by a direct memory transfer controller, a second program memory in which a program for performing a predetermined operation is stored, and a second data input port. The data input to the second bus interface is subjected to predetermined processing according to the program in the second program memory, and the obtained processing result is output to the second data output port via the second bus interface. It has a 2nd processor and the data memory which memorize | stores the process result by a 2nd processor temporarily, It is characterized by the above-mentioned.

  In the present invention, each of the plurality of units outputs the processing result finally obtained by the second processor in the basic unit by the plurality of internal basic units via the first bus interface. Can be output from the port to the data bus.

  In order to achieve the above object, according to the present invention, each of the plurality of units is configured such that the first basic unit among the plurality of basic units in the unit accesses the main memory and reads processing data from the main memory. The processing data input via the first bus interface is processed and the processing result is read into the data memory in the first-stage basic unit, and the remaining of the plurality of basic units excluding the first-stage basic unit The basic unit receives the result processed by the previous basic unit, outputs the processed result to the next basic unit, and outputs the final result obtained by processing the final basic unit among the multiple basic units. A typical processing result is written into the main memory via the first bus interface.

  In the present invention, among the plurality of basic units, the remaining basic units other than the first-stage basic unit receive the result processed by the previous-stage basic unit and output the processed result to the next-stage basic unit. Since the final processing result obtained by processing in the last basic unit among the basic units is written to the main memory via the first bus interface, the plurality of basic units operate independently of each other. Thus, so-called parallel / distributed processing can be realized. Further, in the present invention, the inter-processor control between the basic units becomes very simple and can be easily scaled up, and the basic units can be connected by hardware.

  According to the present invention, each of the plurality of units receives the processing result finally obtained by the second processor in the basic unit by the plurality of internal basic units via the first bus interface. Since data is output from the data output port to the data bus, basic data transfer is performed between the basic units, and access to the main memory is performed only by the first-stage basic unit and the final-stage basic unit. Since data is transferred within each unit of multiple units, bus traffic to the main memory can be greatly reduced. As a result, the performance of the entire system can be improved, and each basic unit performs processing independently of each other. Therefore, so-called parallel / distributed processing is realized, the processing speed is dramatically improved, and the processing speed of the entire system is increased. It can achieve speeds approaching the hardware processing speed.

  In addition, multi-processor parallel / distributed processing requires complex control between processors. However, in the present invention, control between processors between basic units is very simple and easy to scale up. Since the units are connected by hardware, data transfer can be handled in real time. Further, since temporary data storage in the main memory is eliminated and useless bus use is reduced, the processing capacity of the entire system is improved.

  Next, embodiments of the present invention will be described with reference to the drawings. First, the configuration of the processor used in the multiprocessor system of the present invention will be described. The processor used in the present invention includes a first unit (hereinafter referred to as “P unit”) which is a basic unit and a second unit (hereinafter referred to as “M unit”) corresponding to one CPU in FIG. At least composed.

  FIG. 1 shows a block diagram of an embodiment of a P unit. As shown in the figure, the P unit 100 includes one data input port 101, a controller that performs direct memory access transfer (DMA transfer), that is, a bus interface (bus I / F) 102 by DMAC, It comprises a single CPU 103 that performs various operations, a single program memory 104 that stores instructions, a single data memory (RAM) 105, and a single data output port 106.

  In the P unit 100, the data input to the data input port 101 and output from the data output port 106 via the bus I / F 102 is only the processing data, and the processing results are obtained at regular intervals. Is. In addition, since functions can be freely implemented by an instruction (firmware) from the program memory 104 to the CPU 103 (because it is programmable, processing contents can be changed), it is possible to realize complicated processing.

  FIG. 2 shows a block diagram of an embodiment of the M unit. As shown in the figure, the M unit 200 includes one data input port 201, a bus I / F 202 using a high-performance DMAC, a P unit connection block 203, and one data output port 204. The P unit connection block 203 includes a plurality of P units each configured as shown in FIG. 1 in which data input from the data input port 201 is input via the bus I / F 202, and the processed data is transferred to the bus I / F 202. The data is output to the data output port 204 via the. Accordingly, there are a plurality of types of M units 200 depending on the number of P units constituting the P unit connection block 203 and the connection state.

  For example, there are two types of M units having two P units constituting the P unit connection block 203: an M unit 210 shown in FIG. 3A and an M unit 220 shown in FIG. The M unit 210 shown in FIG. 3A constitutes a P unit connection block 203 by two P units 211 and 212 connected in series. Also, the M unit 220 shown in FIG. 3B constitutes a P unit connection block 203 by two P units 221 and 222 connected in parallel.

  Since the plurality of P units 211 and 212 or 221 and 222 constituting the P unit connection block 203 perform processing independently, so-called parallel / distributed processing is realized, and the processing speed is dramatically improved.

  Thus, the M unit 200 has a mechanism that can freely change the connection state of the P unit according to the purpose. The P units can be connected to each other by directly connecting the input and output in hardware, or by the mutual DMAC cooperating with the other party and directly exchanging data. Data transfer can be handled in real time when the connections between P units are such that their inputs and outputs are directly connected by hardware.

  FIG. 4 shows a block diagram of an embodiment of a multiprocessor system according to the present invention. As shown in the figure, in this embodiment, a system control CPU 301 is connected to a program memory 302, and k units (k is a natural number of 1 or more) M units 200-1 and 200 are connected via a data bus 304. ,..., 200-k and the main memory 303 are connected to each other, and the system control CPU 301 and the M units 200-1 to 200-k share the main memory 303 via the data bus 304. is doing.

  Next, the operation of the present embodiment will be described with reference to the flowchart of FIG. Here, a case where the flow of processing proceeds in order of M units 200-1, 200-2,..., 200-k will be described as an example. The system control CPU 301 first outputs a process start command to the M unit 200-1 via the data bus 304 in accordance with a command from the program memory 302 (step S21). Then, the M unit 200-1 reads processing data from the main memory 303 via the data bus 304 (step S22), and a plurality of P units in the M unit 200-1 will be described later with respect to the processing data. The data is sequentially processed as described above (step S23). The M unit 200-1 transfers the result of data processing in this way to the main memory 303 via the data bus 304 and writes it (step S24).

  Subsequently, the system control CPU 301 outputs a process start command to the next M unit 200-2 via the data bus 304 (step S25). Then, the M unit 200-2 reads the processing result processed by the M unit 2001- written in the main memory 303 from the main memory 303 via the data bus 304 (step S26), and the processing result is A plurality of P units in the M unit 200-2 sequentially process data as described later (step S27), and transfer the processing result to the main memory 303 via the data bus 304 and write it (step S28). Thereafter, in the same manner as described above, data processing is sequentially performed by a plurality of M units, and the final processing result processed by the final M unit 200-k is stored in the main memory 303, and a series of processing ends. To do.

  Here, the operation of each M unit of the M units 200-1 to 200-k will be described in more detail with reference to the flowchart of FIG. There are (n + 1) P units from P unit 0 to P unit n in the P unit connection block in the M unit, and the processing flow is in the order of P unit 0, P unit 1,..., P unit n. An example of a case of proceeding will be described.

  First, in the M unit that has received the processing start command from the system control CPU 301, the first P unit 0 in the internal P unit connection block reads processing data necessary for processing from the main memory 303 (step S31). The processing data is processed (step S32), and the obtained processing result is stored in a memory (corresponding to the data memory 105 in FIG. 1) in the P unit 0. The P unit 1 in the next stage reads the data of the processing result of the P unit 0 from the memory in the P unit 0 (step S33), performs a predetermined process on the data of the processing result (step S34), and similarly obtains it. The processing result thus obtained is stored in a memory in the P unit 1 (corresponding to the data memory 105 in FIG. 1).

  The P unit 2 at the next stage reads data of the processing result of the P unit 1 from the memory in the P unit 1 (step S35). Thereafter, the same operation as described above is repeated, the last P unit n processes the data (step S36), and the final processing result obtained is written in the main memory 303 (step S37).

  As described above, in this embodiment, basic data transfer is performed between P units, and access to the main memory 303 is performed by the first stage P unit 0 in step S31 in FIG. 6 and the last stage in step S37. Since only the P unit n is performed and data is transferred in the M unit otherwise, the bus traffic to the main memory 303 is greatly reduced. As a result, the performance of the entire system can be improved.

  Further, in the conventional multiprocessor system shown in FIG. 11, for example, the processing performed by the five CPU processing units 11-1 to 11-5 is realized by the M unit 200-1 in FIG. When the processing performed by the DSP processing units (12-1 to 12-3) is realized by the M unit 200-2 in FIG. 4, the access to the main memory 303 is conventionally 16 pairs (one pair for reading and writing). What has been described is greatly reduced to two pairs in the embodiment of FIG.

  Furthermore, in this embodiment, since the processing is performed in each M unit, temporary storage of data in the main memory 303 is eliminated. Large scale of all systems can be handled by the number of M units, but large scale of M units can be dealt with. A method that suits the purpose and efficiency of the system can be taken. In the present embodiment, the inter-processor control between the P units is very simple and can be easily scaled up.

  Further, in recent years, CPUs have been remarkably miniaturized, and a part including a CPU 301, a program memory 302, an M unit 200-1 to 200-k, and a data bus 304 in FIG. An integrated circuit (LSI) can be used, and a large-scale multiprocessor system can be constructed using such an LSI.

  Note that the present invention is not limited to the above-described embodiment. For example, in FIG. 6, data processing is started from the first P unit 0, and the following P unit 1,... However, the present invention is not limited to this, and when the M unit is configured as shown in FIG. 3B, a plurality of P units are included. A configuration in which operations are performed simultaneously in parallel is also possible, and of course, a configuration in which a P unit group connected in series and a P unit group connected in parallel may coexist.

  In FIG. 4, the M units 200-1 to 200-k sharing the main memory 303 with the system control CPU 301 via the data bus 304 may have the same configuration, or part or Of course, all may be different from each other.

  Furthermore, in the above embodiment, two types of units have been described: the P unit 100 and the M unit 200. However, in the multiprocessor system of the present invention, the units connected to the data bus are limited to the M unit 200. For example, the third unit may be an M unit connection block instead of the P unit connection block 203 in FIG. 2. In short, a unit connection block connected to the bus I / F by DMAC is used. As long as it is an assembly in which at least the P unit 100 is used as a basic unit, the assembly may be multilayered.

It is a block diagram of one embodiment of a P unit used in the system of the present invention. It is a block diagram of one embodiment of the M unit used in the system of the present invention. It is a block diagram which shows each example of M unit in case P units in a P unit connection block are two. It is a block diagram of one embodiment of a multiprocessor system of the present invention. 5 is a flowchart for explaining the overall operation of the multiprocessor system of FIG. 4. 6 is a flowchart for explaining operations in an M unit constituting the multiprocessor system of FIG. 4. It is a figure which shows an example of the process sequence of a processor. It is a figure which shows an example of the data group which a process block processes with progress of time. It is a figure which shows the process order of the unit process data which a process block processes. It is a flowchart for operation | movement description of an example when a processor advances a process. It is a block diagram of an example of the conventional multiprocessor system. 12 is a flowchart for explaining the operation of FIG. 11.

Explanation of symbols

100, 211, 212, 221, 222 P unit 101, 201 Data input port 102 Bus I / F by DMAC
103 Central processing unit (CPU)
104, 302 Program memory 105 Data memory (RAM)
106, 204 Data output port 200, 200-1 to 200-k, 210, 220 M unit 202 Bus I / F by high-performance DMAC
203 P unit connection block 301 System control central processing unit (CPU)
303 Main memory 304 Data bus

Claims (2)

A multiprocessor system having a configuration in which a first processor for system control is connected to a first program memory and is connected to a main memory via a data bus together with a plurality of units,
Each of the plurality of units is
In response to a processing start command from the first processor, data is read from the main memory via the first data input port, and a final processing result is output from the first data output port to the main memory. A first bus interface by a memory transfer controller;
A connection is made so that data input via the first bus interface is subjected to predetermined processing independently for each unit, and the final processing result is output to the first bus interface. A plurality of basic units, and the number of the basic units and the connection method to each other are the same or partly or entirely different from each other,
Each of the plurality of basic units is
A second bus interface by a direct memory transfer controller;
A second program memory in which a program for performing a predetermined operation is stored;
Predetermined processing is performed on the data input to the second bus interface via the second data input port according to the program in the second program memory, and the obtained processing result is displayed on the second bus. A second processor for outputting to a second data output port via the interface;
A multiprocessor system, comprising: a data memory for temporarily storing the processing result by the second processor. In each of the plurality of units, the basic unit in the first stage among the plurality of basic units in the unit accesses the main memory to read processing data from the main memory, and passes through the first bus interface. The processing data input in step 1 is processed and the processing result is read into the data memory in the first-stage basic unit, and the remaining basic units excluding the first-stage basic unit among the plurality of basic units. Receives the result processed by the previous basic unit, outputs the processed result to the next basic unit, and obtains the final result obtained by processing the final basic unit among the plurality of basic units. 2. The processing result is written to the main memory via the first bus interface. Multi-processor system.

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