JPS62171307A - Differential amplifier - Google Patents

Abstract

PURPOSE:To prevent an input signal which has a large amplitude from deteriorating in linearity and having its waveform deformed by providing two auxiliary differential amplifiers which share a load resistance with a conventional differential amplifier and are applied with a bias in the opposite directions. CONSTITUTION:Assuming that transistors (TR) 21-26 are all equal in base- emitter voltage value, the 1st auxiliary differential amplifier does not operate when the signal voltages of signals sources 13 and 14 are both zero. When a signal voltage ES is low, and varied, for example, positively, the TRs 23 and 24 enter an active range and the 1st auxiliary differential amplifier operates to flow a signal current amplified by a resistance 43 (1st load means) and a resistance 44 (2nd load means), so the linearity is improved and waveform distortion is reduced greatly. When the signal voltage Es drops, the 2nd auxiliary differential amplifier operates to remove the waveform distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in differential amplifiers, and particularly to differential amplifiers suitable for handling large amplitude signals.

For example, the present invention provides a differential amplifier that is extremely suitable for generating large amplitude, low distortion signals for deflecting the X or Y axis of a cathode ray tube into an oscilloscope.

[Conventional technology] A conventional differential amplifier circuit is shown in FIG. 4 and will be explained.

Here, 11 and 12 are input terminals, to which a signal source 13 with a signal voltage of E and a signal source 14 with a signal voltage of opposite polarity -F are input, respectively.

Input terminals 11 and 12 are connected to transistors 21 whose respective emitters are coupled by a resistor 40 (resistance value R6).
and 22. The emitters of the transistors 2113 and 22 each have a bias current ■
. Constant current sources 31 and 32 are connected to flow the current. Resistors 43 (resistance value R) and 44 (resistance value R4) for loads are connected between the respective collectors of the transistors 21 and 22 and the power supply voltage of 10 V, and the voltage from the collectors of both transistors 21 and 22 is , respectively output '5
:'+? Output terminals 15 and 16 are provided for 7.

Generally, the emitter spread resistance ro of a transistor is approximately expressed as ro [Ω]''-26/IE [mA] (1), where IE is the emitter current of the transistor.

In FIG. 4, when the voltages of signal sources 13 and 14 are zero, the emitter current of each transistor 21 and 22 is I, respectively. It is. Here, when the voltages of the signal sources 13 and 14 are E and -ES, the emitter currents of the transistors 21 and 22 are . +I, and I
-1. Here, I is the signal current at the emitter due to signals E and -E.

Letting the emitter spread resistances of transistors 21 and 22 be r and 'e2, respectively, then from equation (1), r, 1=26/(Io+IS) (2) r'e2
=26/(Ie-1,) (3).

As shown in equations (2) and (3), the bias current ■. If the signal current I is a small value with respect to the emitter spreading resistances r and r. 2 can be ignored, but when the signal current I, becomes large, the emitter spread resistances r and r. Changes in number 2 cannot be ignored.

The voltage gain G of this differential amplifier is G= (R3+R4) / (R□ +r81+ 'e
2) It is expressed as (4〉).

[Problems to be Solved by the Invention] The voltage gain G of the differential amplifier is expressed by equation (4), where r and r are included in the denominator. 2 is the formula (2) and (
3) As shown in the equation, when the value of the signal voltage E of the signal sources 13 and 14 increases, the emitter spread resistance r. 1 and 'e2
Since the sum of 19G increases, the voltage sum 19G decreases. 1, however, there was a problem that linearity deteriorated and the waveform was distorted for large input signals.

[Means for Solving the Problems] The present invention has been made in order to solve these problems, and is to provide a conventional differential amplifier with a load resistance common to that of the conventional differential amplifier. Two sets of auxiliary differential amplifiers were provided with their biases shifted in opposite directions.

[Function] When the amplitude of the input signal is small, the two sets of auxiliary differential amplifiers are not in a balanced state due to the bias applied, so they do not operate as amplifiers, and only the conventional differential amplifier operates. do.

For example, when there is a large positive amplitude input signal, one of the auxiliary differential amplifiers becomes active and adds its amplification effect in addition to the amplification effect of the conventional differential amplifier. Further, when there is a large negative amplitude input signal, in addition to the amplification effect of the conventional differential amplifier, the other auxiliary differential amplifier becomes active and its amplification effect is added. In this way, the auxiliary differential amplifier becomes active and amplifies only the input signal with a width of one width, thereby reducing the amplification effect of the input signal of the conventional differential amplifier. Since this is supplemented, even large amplitude input signals can be amplified with good linearity.

[Example] An embodiment of the present invention is shown in FIG. 1A and will be described.

Components corresponding to those shown in FIG. 4 are given the same symbols and numbers in FIG. 1A.

The l-transistors 21 and 22, the resistor 40, and the low current sources 31 and 32 form a main differential amplifier.

The transistors 23 and 24 are coupled between their emitters by a resistor 41 (resistance value R1), and constant current sources 33 (current value 1) and 34 are connected to their emitters.
(current value I...) are connected to each other, the base of the transistor 23 is connected to the emitter of the transistor 21 via the bias voltage 73 (voltage value v83), and the base of the transistor 24 is connected to the bias voltage 7
4 (voltage value V84) to the emitter of the transistor 22, and the collectors of the transistors 23 and 24 are connected to the output terminals 15 and 16, respectively, forming a first auxiliary differential amplifier.

The transistors 25 and 26 are connected between their emitters by a resistor 42 (resistance value R2), and constant current sources 35 (current value ■) and 36 are connected to their emitters.
(current value I...) are connected to each other, the base of transistor 25 is connected to the emitter of transistor 21 via bias voltage 75 (voltage value vB5), and the base of transistor 26 is connected to bias voltage 76.
(voltage value VB6) to the emitter of transistor 22, and the collectors of transistors 25 and 26 are connected to output terminals 15 and 16, respectively, forming a second auxiliary differential amplifier.

Now, regarding the first auxiliary differential amplifier, if the base-emitter voltages of the transistors 21 to 26 are all vBE of the same value, and the signal voltages of the signal sources 13 and 14 are zero, the transistors The base voltage of transistor 23 is vB3+v higher than the base voltage of transistor 24.
The value is lower by 84. Therefore, when 8o, R1, V83 and VB4 are set so that 'ee-R1<VB3+VB4 (5), transistor 23 is in the cutoff region and transistor 24 also does not perform an amplification effect. Even if signal voltages E and -E are applied to terminals 11 and 12 in this state, 2 [s + Iee"R1<VB3+VB4 (
If it is in the range of 6), the transistor 23 is hot!
- The first auxiliary differential amplifier does not operate because it is in the off region and the transistor 24 does not perform any amplifying action.

In the second auxiliary differential amplifier including transistors 25 and 26, transistor 25 corresponds to 24, transistor 26 corresponds to 23, resistor 42 (R2> corresponds to 41 (R1), and constant current sources 35 and 36 correspond to 346 and 23, respectively). 33, so it does not operate with respect to small signal voltages E, similarly to the first auxiliary differential amplifier.

Therefore, when the signal voltage E is small, it operates like a conventional differential amplifier. For example, the signal voltage E3 increases in the positive direction by 2E, 10I. o-R1〉VB3+V84 (7) If the condition of equation (6) is no longer satisfied, the amplification of the main differential amplifier including transistors 21 and 22 will decrease, but
The transistors 23 and 24 become active regions, and the first auxiliary differential amplifier operates and resistors 43 (first load means>, 4
4 (second load means), linearity is improved and waveform distortion is significantly reduced.

When the signal voltage E increases in the negative direction, the second auxiliary differential amplifier similarly operates to remove waveform distortion.

When the circuit shown in Figure 1A was applied to an amplifier for deflecting the YIFIil of a cathode ray tube of a wideband oscilloscope, the waveform distortion was reduced to about 2% at full scale, compared to the conventional waveform distortion of about 10%. became.

FIG. 1B shows an alternative embodiment in that the two inputs of the second auxiliary differential amplifier are obtained one from the base of transistor 21 and the other from the emitter of transistor 22. This differs from the embodiment shown in FIGS. 1A and 1B. The second auxiliary differential amplifier is 2 E3 + VB5 + VBB+ v131E>I
ee''R2, the transistor 26 is off, and the signal voltage E8 increases in the negative direction (
When equation 8) is no longer satisfied, the second auxiliary differential amplifier becomes active.

Figure 1C shows a case where the second auxiliary differential amplifier is omitted and the first auxiliary differential amplifier is combined with the main differential amplifier, which is effective when the signal voltage E3 has a large amplitude only in one direction. be.

In FIGS. 1A to 1C, the collectors of the transistors 23 to 26 of the first and second auxiliary differential amplifiers are connected to the output terminal 15 through a filter, respectively or a part thereof.
and 16. These filters have frequency characteristics through a combination of resistance, inductance, conching, etc., and are effective in obtaining the effects of the present invention in the frequency range determined by the characteristics of these filters.

It will also be clear that the values of resistor 41 (R1) and resistor 42 (R2>) may be different to provide asymmetric distortion correction for large positive and negative amplitude input signals.

In the above description, the case where the voltages of the signal sources 13 and 14 are E and -E, respectively, is explained, but only one of them, for example, the signal source 13, is applied to the input terminal 11, and the input terminal 12 is grounded. It's okay. Also, one signal source may be connected between input terminals 11 and 12.

Further, the signal sources 13 and 14 may exhibit completely different voltage values.

Furthermore, the signal voltage may not be applied to either one of the input terminals of the first auxiliary differential amplifier, but a fixed voltage may be applied. Similarly, no signal voltage may be applied to either input terminal of the second auxiliary differential amplifier, and a fixed voltage may be applied.

The bias voltage means 73 to 76 shown in FIGS. 1A to 1C may be replaced with the various bias voltage means shown in FIG. 2, or if the bias voltage is not required, a simple connection It is also possible to connect directly by line.

Figure 2(a) shows a transistor 8 forming an emitter follower.
1 and a constant current source 89 are shown. In addition to such an emitter follower, an amplifier that uses a resistor in place of the constant current source 89, or even inserts a resistor between the collector of the transistor 81 and the power supply V, can also have a resistor connected to its base. It will be clear that the emitter-to-emitter voltage can be used as a bias voltage means. (b) is the diode 82
, the voltage between the anode and cathode is used as a bias means, and similarly, 83 is the resistor 83, 84
In this example, a constant voltage diode 84 is used as a bias voltage means. In (e), a field effect transistor 85 is used in place of the 1-run transistor 81 shown in (a).

In FIG. 2, it is also possible to use a PNP transistor for the transistor 81 and a P-channel type for the field effect transistor 85, or to reverse the polarity of the diode 82 and the constant voltage diode 84 from those shown, and to change the polarity of the constant current source 89. It will be clear that the polarity of the power supply voltage may also be reversed.

In FIGS. 18 to 1C, resistors 43 and 44 as load means are used for the output terminals 15 and 16, but these may include active elements as shown in FIG. 3.

In FIG. 3, transistors 27 and 28 are each connected to the base, and in (a), the current output from each collector of transistors 27 and 2B is 1q.
I can do that. In FIG. 3(b), a current output can be obtained from the collector of the transistor 27. In FIG. 3(C), transistor 2 of FIG. 3(a)
Resistors 45 and 46 are connected between the collectors of transistors 7 and 28 and the power supply +V1, respectively, so that a voltage output can be obtained from the collectors of transistors 27 and 28, respectively.

In FIGS. 3(d) to (f), in a3, 51 and 52 are operational amplifiers, 29 and 30 are transistors, and 61 and 62 are impedances for parallel feedback.

In FIGS. 3(d) to (f>), the input terminals of operational amplifiers 51 and 52 are connected to output terminals 15 and 1, respectively.
6, and a voltage output of 1q can be output to the output terminals of the amplifiers 51 and 52. In (e), the bases of J-transistors 29 and 30 whose emitters are connected to ground are connected to the output terminals 15 and 16, respectively, and an output voltage can be obtained at each collector. (
f) is a combination of (d) and (e).

When the load means shown in FIGS. 3(d) to 3(f) are used in FIGS. 1A to 1C, signal voltages E and -E are applied between input terminals 11 and 12 and ground, respectively. In the case, the amplified signal currents flowing through the output terminals 15 and 16 change the emitter spreading resistances of the transistors 21 and 22 to 'el and r, respectively. 2, then I
,=2E,/(Ro+r.1+'e2).

Therefore, if the respective one-channel impedances 61 and 62 are Zfl and Zr2, the signal voltage E at each output of operational amplifiers 51 and 52 (each collector of transistors 29 and 30). 1 and Eo2 are Eo, = 13- Zfl (10)E
O2=I3-Zr2 (11).

Even in the cases shown in FIGS. 3(d) to 3(f), one of the load means connected to each of the output terminals 15 and 16 may be omitted as shown in FIG. 3(b), Alternatively, it is also possible to replace one of the load means with a resistor or a transistor whose base is connected to the ground.

In FIG. 3, it is also possible to replace all or part of transistors 27-30 with field effect transistors.

[Effects of the Invention] As is clear from the above description, according to the present invention, it is possible to significantly reduce the distortion of a differential amplifier when the amplitude is large, and the effect is extremely large.

[Brief explanation of drawings]

1A, 1B, and 1C are circuit diagrams showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing other embodiments of the present invention, and FIG. 4 is a circuit diagram showing a conventional example. FIG. 11.12... Input terminal 13.14... Signal source 15.16... Output terminal 21-30... Transistor 31-36... Constant current source 40-46... Resistor 51.52 ...Running amplifier 61.62...Impedance 73-76...Bias voltage 81...1-Randisco 82...Diode 8
3...Resistor 84...Constant voltage guide 85...Field effect transistor 89...Constant current source Es...Signal voltage.

Claims (12)

[Claims] (1) a first input terminal and a second input terminal between which an input signal is applied; respective bases connected to the first input terminal and the second input terminal; and respective collectors connected to the first input terminal and the second input terminal; is the first
a first transistor connected to the output terminal of the first transistor and the second output terminal, an emitter resistor extending between the emitters thereof, and a constant current means for supplying an emitter current to the emitters of the first transistor; a second transistor; and at least one base of at least one of the emitter of the first transistor and the emitter of the second transistor has a bias voltage that may include zero volts. the respective collector currents are supplied through the first output terminal and the second output terminal, the first resistor is connected across the emitters of each other, and the emitter current is supplied to the emitters of the respective emitters. a first auxiliary differential amplifier including a third transistor and a fourth transistor connected to constant current means for supplying a constant current; and at least one of the first output terminal and the second output terminal. and at least one load means connected to one output terminal. (2) at least one base is connected to at least one of the emitter of the first transistor and the emitter of the second transistor via bias voltage means, which may include zero volts, and the respective collector current is connected to the emitter of the first transistor and the emitter of the second transistor; A second resistor is supplied through the first output terminal and the second output terminal, is connected to a second resistor spanning between the emitters, and is connected to a constant current means for supplying an emitter current to the emitters of the emitters. 2. The differential amplifier of claim 1, further comprising a second auxiliary differential amplifier including a fifth transistor and a sixth transistor. (3) the base of each is connected to the base of the first transistor and the emitter of the second transistor via bias voltage means, which may include zero volts;
Each collector current is supplied through the first output terminal and the second output terminal, a second resistor is connected across the emitters of each other, and a constant current is provided for supplying emitter current to the emitters of each other. 2. A differential amplifier as claimed in claim 1, comprising a second auxiliary differential amplifier including a fifth transistor and a sixth transistor connected to each other. (4) At least one of the collectors of the third and fourth transistors is connected to at least one of the first and second output terminals via at least one filter means. A differential amplifier according to claim 1. (5) The differential amplifier according to claim 1, wherein the at least one load means is at least one resistor. (6) The at least one load means is a transistor whose base is connected to a common ground, and the emitter of the transistor is connected to at least one of the first and second output terminals. A differential amplifier according to range 1. (7) The at least one load means is a field effect transistor whose gate is connected to ground, and the source of the field effect transistor is connected to at least one of the first and second output terminals. A differential amplifier according to claim 1. (8) The at least one load means is a common emitter-connected transistor having a parallel feedback impedance, and the base of the transistor is connected to at least one of the first and second output terminals. A differential amplifier according to claim 1. (9) said at least one load means is a field effect transistor having a parallel feedback impedance and whose source is connected to ground, the gate of said field effect transistor being connected to at least one of said first and second output terminals; A differential amplifier according to claim 1, wherein the differential amplifier is connected to two output terminals. (10) A patent in which the at least one load means is an operational amplifier having a parallel feedback impedance, and the input of the operational amplifier is connected to at least one of the first and second output terminals. A differential amplifier according to claim 1. (11) The bias voltage means, which may include zero volts, includes a connection line, a battery, a voltage between the base and emitter of a transistor, a voltage between electrodes of a diode, a voltage drop of a resistor, a voltage between the electrodes of a constant voltage diode, and 4. The differential amplifier according to claim 1, wherein the differential amplifier includes at least one of those using a gate-source voltage of a field effect transistor. (12) At least one of the collectors of the third, fourth, fifth, and sixth transistors is connected to at least one of the collectors of the third, fourth, fifth, and sixth transistors.
4. A differential amplifier according to claim 2, wherein the differential amplifier is connected to at least one of the first and second output terminals through two filter means.