JPS62171131A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62171131A
JPS62171131A JP61013103A JP1310386A JPS62171131A JP S62171131 A JPS62171131 A JP S62171131A JP 61013103 A JP61013103 A JP 61013103A JP 1310386 A JP1310386 A JP 1310386A JP S62171131 A JPS62171131 A JP S62171131A
Authority
JP
Japan
Prior art keywords
island portion
island
semiconductor element
bonding
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61013103A
Other languages
Japanese (ja)
Inventor
Takeshi Miyano
宮野　毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61013103A priority Critical patent/JPS62171131A/en
Publication of JPS62171131A publication Critical patent/JPS62171131A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate the dislocation of a semiconductor element from an initial mount position due to foaming of paste in the course of thermal hardening thereof by a method wherein a groove extending radially from the center of an island is provided in an island portion of a lead frame to which the semiconductor element is bonded. CONSTITUTION:A radial groove 2 is provided in an island portion 1. A semiconductor element 3 is die-bonded to the island portion 1 by using a paste material 4, and a bonding pad 5 of the semiconductor element 3 is wire-bonded to the end 6 of a lead element by a bonding wire 7. The periphery of the island portion containing these bonding elements is sealed up with resin, and thereby a semiconductor device is completed. Gas produced by the thermal hardening of the paste in a die-bonding process is removed outside rapidly through the groove in the island portion, and therefore a phenomenon of foaming ceases to occur on the bonded surface of the semiconductor device and the island portion.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にトラン７アーモールド
技術によって樹脂封止された半導体装置のリードフレー
ムのアイランド部の形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to the shape of an island portion of a lead frame of a semiconductor device resin-sealed by Tran 7 Armold technology.

〔従来の技術〕[Conventional technology]

従来、トランスファーモールド技術によって樹脂封止さ
れた半導体装置においては、半導体素子のダイポンディ
ング方法として、半導体素子をリードフレームのアイラ
ンド上にペースト材を用いてマウントし、その後ペース
トを加熱し熱硬化させ、半導体素子をアイランド上に接
着する方法が広く用いられている。Conventionally, in semiconductor devices sealed with resin using transfer molding technology, the die-bonding method for semiconductor elements is to mount the semiconductor element on an island of a lead frame using a paste material, then heat the paste and thermoset it. A method of bonding semiconductor devices onto islands is widely used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のグイボンディング方法では、第６図に示
すようにペースト材４からガスが発生し、半導体素子３
とリードフレームアイランド部１との接着面で発泡現象
が起こり、発泡８のため第５図に示すように半導体素子
３が初期のマウント位置から移動してしまうという欠点
がある。In the conventional bonding method described above, gas is generated from the paste material 4 as shown in FIG.
A foaming phenomenon occurs at the bonding surface between the lead frame island portion 1 and the semiconductor element 3, which causes the semiconductor element 3 to move from its initial mounting position as shown in FIG.

本発明は、上記欠点を除去し、半導体装置の製造におけ
る歩留を向上させることを目的とする。The present invention aims to eliminate the above-mentioned drawbacks and improve the yield in manufacturing semiconductor devices.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の半導体装置は、半導体素子を接着するリードフ
レームのアイランド部にアイランド中心から放射状に延
びた溝を有することを特徴とする。The semiconductor device of the present invention is characterized in that an island portion of a lead frame to which a semiconductor element is bonded has grooves extending radially from the center of the island.

〔実施例〕〔Example〕

以下、図面を参照して本発明の一実施例を説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第１図、第２図は本発明の一実施例のリード７レームア
イランド部ｌの概略平面図と断面図である。第１図に示
すようにアイランド部１には放射状の溝２がある。第３
図、第４図に示すようにアイランド部１に半導体素子３
をペースト材４を用いてダイボンディングを行ない、半
導体素子３のボンディングパット５とリード部先端６と
がボンディングワイヤー７、Ｋよってワイヤーボンディ
ングされている。これらボンディング部を含むアイラン
ド部の周囲が樹脂によって封止され半導体装置が完成す
る。FIGS. 1 and 2 are a schematic plan view and a cross-sectional view of a lead 7 frame island portion l according to an embodiment of the present invention. As shown in FIG. 1, the island portion 1 has radial grooves 2. Third
As shown in FIG.
Die bonding is performed using paste material 4, and bonding pad 5 of semiconductor element 3 and lead portion tip 6 are wire-bonded using bonding wires 7 and K. The periphery of the island portion including these bonding portions is sealed with resin to complete the semiconductor device.

ダイボンディング工程のペーストの熱硬化によって発生
したガスはアイランド部溝を通り速やかに外部に排出さ
れるため半導体装置とアイランド部の接着面には発泡現
象は起らなくなる。Gas generated by thermal curing of the paste in the die bonding process passes through the island groove and is quickly discharged to the outside, so that no bubbling occurs on the bonding surface between the semiconductor device and the island.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、リードフレームのアイラ
ンド部にアイランド中心から放射状に延びた溝を有する
ことにより、ペーストの熱硬化中の発泡に起因する半導
体素子の初期マウント位置からの移動をなくシ、トラン
スンファーモールド技術によって樹脂封止された半導体
装置の製造における歩留を向上できる効果がある。As explained above, the present invention has grooves extending radially from the center of the island in the island portion of the lead frame, thereby eliminating the movement of the semiconductor element from the initial mounting position due to foaming during thermal curing of the paste. This has the effect of improving the yield in manufacturing semiconductor devices sealed with resin using transfer molding technology.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例によるリードフレームアイラ
ンド部概略平面図、第２図は第１図のアイランド溝部の
断面図、第３図は本発明の一実施例による半導体装置の
概略平面図、第４図は第３図のアイランド溝部の断面図
、第５図は従来の半導体装置の概略平面図、第６図は第
５図のアイランド部の断面図。 １・・・・・・アイランド部、２・・・・・・溝、３・
・−・・・半導体素子、４・・・・・・ペースト材、５
・・・・・・ボンディングパ、ト、６・・・・・・リー
ド部、７・・・・・・ボンディングワイヤー、８・・・
・・・発泡。 彩３図1 is a schematic plan view of a lead frame island portion according to an embodiment of the present invention, FIG. 2 is a sectional view of the island groove portion of FIG. 1, and FIG. 3 is a schematic plan view of a semiconductor device according to an embodiment of the present invention. , FIG. 4 is a sectional view of the island groove portion in FIG. 3, FIG. 5 is a schematic plan view of a conventional semiconductor device, and FIG. 6 is a sectional view of the island portion in FIG. 5. 1...Island part, 2...Groove, 3.
... Semiconductor element, 4 ... Paste material, 5
...Bonding pad, G, 6...Lead part, 7...Bonding wire, 8...
...foaming. Aya 3

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を接着するリードフレームのアイランド部に
アイランド中心から放射状に延びた溝を有することを特
徴とする半導体装置。A semiconductor device characterized in that an island portion of a lead frame to which a semiconductor element is bonded has grooves extending radially from the center of the island.
JP61013103A 1986-01-23 1986-01-23 Semiconductor device Pending JPS62171131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61013103A JPS62171131A (en) 1986-01-23 1986-01-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61013103A JPS62171131A (en) 1986-01-23 1986-01-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62171131A true JPS62171131A (en) 1987-07-28

Family

ID=11823815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61013103A Pending JPS62171131A (en) 1986-01-23 1986-01-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62171131A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01297828A (en) * 1988-05-25 1989-11-30 Matsushita Electron Corp Semiconductor device
US5059558A (en) * 1988-06-22 1991-10-22 North American Philips Corp., Signetics Division Use of venting slots to improve hermetic seal for semiconductor dice housed in ceramic packages
JPH0737768A (en) * 1992-11-26 1995-02-07 Sumitomo Electric Ind Ltd Reinforcing method for semiconductor wafer and reinforced semiconductor wafer
KR100273113B1 (en) * 1998-03-11 2001-01-15 김충환 Lead frame for semiconductor
KR100499606B1 (en) * 2000-06-13 2005-07-07 앰코 테크놀로지 코리아 주식회사 Substrate for manufacturing semiconductor package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01297828A (en) * 1988-05-25 1989-11-30 Matsushita Electron Corp Semiconductor device
US5059558A (en) * 1988-06-22 1991-10-22 North American Philips Corp., Signetics Division Use of venting slots to improve hermetic seal for semiconductor dice housed in ceramic packages
JPH0737768A (en) * 1992-11-26 1995-02-07 Sumitomo Electric Ind Ltd Reinforcing method for semiconductor wafer and reinforced semiconductor wafer
KR100273113B1 (en) * 1998-03-11 2001-01-15 김충환 Lead frame for semiconductor
KR100499606B1 (en) * 2000-06-13 2005-07-07 앰코 테크놀로지 코리아 주식회사 Substrate for manufacturing semiconductor package

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