JPS62169591A - Time base collector - Google Patents

Abstract

PURPOSE:To eliminate the disturbance of a video signal at a search mode and to simplify the circuit constitution by detecting the deviation of an address at the search mode to hypass an input signal to the output side. CONSTITUTION:Since the horizontal synchronizing number during one vertical synchronizing period differs from that at the normal operation in an input signal (a) at a search mode, there exists a deviation between a write address of an address timing circuit 9 and the vertical synchronization of the input video signal. Then a write address deviation detection circuit 10 is operated, a bypass circuit 11 is activated and the input signal (1) is bypasses at the output. Although the write address is deviated and the video signal at the output of a D/A conversion circuit is fluctuated to a vartical synchronizing signal or causes disturbance in the search mode in such a way, since the bypass circuit is operated at the video signal output, the input signal is outputted as it is and no vertical fluctuation nor disturbance is caused in the video image. Further, a complicated circuit to prevent the write address deviation is not required and the circuit scale is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time base corrector device for correcting time base errors that occur when reproducing video signals recorded on a VTR, optical disc, or the like.

Prior Art FIG. 2 shows the configuration of a conventional time base collector device. In FIG. 2, a is a video signal input such as a VTR, 1 is a buffer amplifier for the input signal, 2 is an A/D conversion circuit that converts an analog video signal into a digital signal, and 3
4 is a memory circuit for storing digital signals; 4 is a D/A converter circuit for converting digital signals into analog signals; 5 is a D/A conversion circuit for converting digital signals into analog signals;
is an output signal buffer amplifier, and b is a video signal output. Further, 6 is a write clock generation circuit that generates a synchronization signal and a clock pulse from an input video signal, and C is a
Reference signal input, 9 is a buffer amplifier for the reference signal, 8 is a read clock generation circuit that generates a synchronization signal and clock pulse from the reference signal, and 7 is a circuit that generates memory addresses and timing pulses from the write clock and read clock. This is an address timing generation circuit.

Next, the operation of the above conventional example will be explained. In FIG. 2, input video signal a passes through buffer amplifier 1,
The data is converted by a D conversion circuit 2 and written into a memory circuit 3 consisting of a line memory.

Further, the write clock generation circuit 6 generates a clock that follows the jitter of the input video signal a.

On the other hand, the signals from the reference signal input C pass through the buffer amplifier 9 and are input to the read clock generation circuit 8, which generates a clock synchronized with the reference signal. The address timing generation circuit 7 generates a write address that follows the jitter of the input video signal from the write clock, and generates a read address synchronized with a reference signal from the read clock and supplies it to the memory circuit 3. The digital signal read by the read clock generation circuit 8 is converted into an analog signal by the D/A conversion circuit 4, and then passed through the buffer amplifier 5.
Output as a video signal.

Problems to be Solved by the Invention However, when a VTR is used in search mode or pause mode, the signal has a different number of horizontal synchronizations during one vertical interval. or vertical blanking appears in the center of the screen. Therefore, in order to produce a stable image in search mode or pause mode, there is a problem in that the write clock generation circuit and address timing generation circuit become complicated.

The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent time pace corrector device that outputs a stable video signal for any VTR without complicating the circuit.

Means for Solving the Problems In order to achieve the above object, the present invention includes a write address deviation detection circuit that detects a deviation of the write address from an input video signal, and a deviation detection signal that bypasses the input video signal to the output. A bypass circuit is added to the time pace corrector device.

Operation The present invention has the following effects due to the above-described configuration. In other words, when the input signal is in the search mode of the VTR, a shift occurs between the write address and the vertical synchronization of the input signal, the write address shift detection circuit operates, and the bypass circuit operates thereby, allowing the input signal to remain as it is. Since the search image is output, a stable search image can be displayed on the monitor. Furthermore, since it is bypassed when the power is turned on or when the write address is unstable, a distorted image will not be output.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 10 is a write address deviation detection circuit that detects a write address deviation, and 11 is a bypass circuit that bypasses an input signal to an output. other second
Numbers and symbols similar to those in the figures represent the same names.

Next, the operation of the above embodiment when the input signal is in the search mode will be explained. In the above embodiment, when the input signal a is in the search mode, the number of horizontal synchronizations during one vertical interval period is different from the normal operation, so there is a gap between the write address of the address timing circuit 9 and the vertical synchronization of the input video signal. causing misalignment. Therefore, the write address deviation detection circuit 10 operates, the bypass circuit 11 operates, and the input signal a is bypassed to the output.

In this way, according to the above embodiment, the write address deviates during the search mode, and the video signal fluctuates or is distorted with respect to the vertical synchronization signal in the output of the D/A conversion circuit. However, since the bypass circuit is operating for video signal output, the input signal is output as is,
The video has the advantage of not causing vertical fluctuations or disturbances. Further, according to the above embodiment, there is no need for a complicated circuit to prevent the write address from shifting, and there is an advantage that the circuit scale can be kept small.

Effects of the Invention As is clear from the above embodiments, the present invention is configured to detect the address shift during the search mode and bypass the input signal to the output side, so that the image is not distorted during the search mode. It has the advantage that such a circuit can be realized with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a time pace collector device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional time base collector device. 1... Buffer amplifier, 2... A/D conversion circuit,
3...Memory circuit, 1...D/A conversion circuit, 5.
...Buffer amplifier, 6.. Write clock generation circuit, 7.. Address timing generation circuit, 8.. Read clock generation circuit, 9.. Buffer amplifier, 10.
...Write address deviation detection circuit, 11...Bypass circuit, a...Video signal input, b...Video signal output,
C...Reference signal input.

Claims (1)

[Claims] When the input video signal is A/D converted, time axis errors are corrected via memory, and then D/A converted again to obtain the output video signal, when the input video signal is in the search mode, the memory is A time base collector that detects a synchronization difference between a write address and an input video signal using a write address detection circuit, bypasses the circuit between the A/D conversion and D/A conversion, and outputs the input video signal. Device.