JPS62169516A - Priority input selecting circuit - Google Patents

Abstract

PURPOSE:To change freely the priority in a large processing flow by a program, etc. by designating the signal priority with use of a priority designating register that can be rewritten by a program, etc. CONSTITUTION:Three registers 6-1, 6-2 and 6-3 of a rewritable properity designating register 6 designate the inputs of priority I, II and III respectively. Then three bits 0, 1 and 2 of those registers 6-1-6-3 indicate inputs I1, I2 and I3 respectively. Only one of those three bits is set at '1' and the priority of each input is designated. A priority converting circuit 7 converts plural input signals into the signals having properity after the register 6 is set. Then a selecting circuit 1 selects a signal having higher priority out of those signals having priority. An output converting circuit 8 converts the selected signal into an output signal corresponding to the original input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a priority manual selection circuit belonging to an electronic circuit.

[Conventional technology]

An example of a conventional priority input selection circuit is shown and explained in FIG.

In the figure, 1 is the input signal SI+ + SIz I S
This is a selection circuit that selects a signal with a high priority from i2.It is a selection circuit that selects a signal with a high priority from i2, and two knot circuits 2 and 3 which input the input signal SI and the input signal 5I21, respectively, and the output of this knot circuit 2 and the input signal SI, (i7 It is composed of 19 manually operated AND circuits 4, each output of the knot circuits 2 and 3, and an AND circuit 5 that receives the input signal 5Isi.
S Oz , 803 is the output signal from this selection circuit 1.Next, the operation will be explained.

1. Input signal SI1 has the highest priority (hereinafter referred to as priority I), input signal SI2 has the next highest priority (hereinafter referred to as priority ■), input signal SI3 has priority. The input with the lowest priority (hereinafter referred to as priority ■) is rejected. The following explanation will be based on positive logic.

First, if the input signal SI is rarely 1'', the output signal S01 of the selection circuit 1 will be 1'' regardless of whether each input signal SI2.Si2 is 4'' or 1''. Next, if the input signal SI2 is rarely found in mo1'', this input (g signal S
An AND circuit 4 is connected between I2 and the output signal so2, and the input signal SI whose logic is inverted through the NOT circuit 2 is input to the other input of the AND circuit 4, so that the input signal SI becomes sO" When , the output signal SO2 is %1'', but when the input Po signal S I 1 is %1'', the output signal SO2 is %1''.

becomes 10#. This output signal SO2 is the input signal S1.
Similarly, the AND circuit 5 between the input signal SI3 and the output signal S03 has a NOT time '#! 12 and the input signal S from the NOT circuit 3.
Since the inverted output of I2 is input, when the input signal SI3 is %l#, the input signals SIl and SI.

If both are 10'', the output signal 803 will not be %1''.

In other words, when the input signal SIl with the priority order ■ is a game friend (
S11=%l'), when the output signal SO1 becomes 1 and 9, and the input signal SI2 of priority ■ is present, if there is no input of priority I (SI, = '0 ') Output signal so2 becomes 11", input signal of priority ■ 8Xs
When 6')7'j, the output signal S03 becomes 11'' only when there is no input of priority level l or input of priority level port.

By the way, if there are multiple inputs, only the output for the input with the highest priority among the inputs will be %l''.

[Problems to be Solved by the Invention] The above-mentioned conventional priority input selection circuit is configured as described above, so the priority order for inputs is fixed, and the priority input selection circuit is configured as described above. The problem was that the priority of processing could not be changed.

The present invention was made to solve this problem, and the objective is to provide a priority input selection circuit that can freely change the priority of input signals from time to time during a large processing flow. do.

[Defined means of solving problems]

The priority input selection circuit according to the present invention includes a rewritable priority order designation register that designates the priority order of input signals;
A priority converting circuit that converts a plurality of input signals into signals with priorities, a selection circuit that selects a signal with a high priority from among the signals with the priority "I!r", and this selection circuit has a It is equipped with an output conversion circuit that converts the selected number with the next highest priority into an output signal corresponding to the original input signal.

[For production]

In this invention, it is possible to change the priority order designation register behind the scenes by a program, etc., and by rewriting the contents of this priority order designation register, the priority order of the input signal can be specified by modifying this register. , , the friend priority attached to the input signal changes, and the selected output signal also changes.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a priority input selection circuit according to the present invention.

In Fig. 1, the same reference numerals as in Fig. 2 indicate corresponding parts, and 1 is a selection circuit that selects a signal with a high priority from among ratio signals with a summer first order. It is composed of AND circuits 4 and 5. Reference numeral 6 denotes a rewritable priority order designation register that specifies the priority order of input signals, and there are three registers 6-1, 6-2, and 6.
-3, each register 6-1 to 6-6.
-3 are bit O, bit 1, respectively. It consists of 3 bits of pit 2. T is a priority conversion circuit that converts a plurality of input signals into signals with high priority;
The machining OR circuit 12a to 12°cK machining 9 grooves are formed.

8 is an output conversion circuit that converts a high priority signal selected by the selection circuit 1 into an output signal corresponding to the original input signal; AND circuits 13a to 13C914a to 14c;
15a to 15c and OR circuits 16 to 18.

Then, II r I2 + 13 n each indicate the priority conversion circuit 70 input, and 0+I O! lOs
tit indicates the output of the output conversion circuit 8, respectively.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

Three registers 6-1: Priority designation register 6
, 6-2, and 6-3 correspond to each priority, and the input of the register 6-1 or priority I is
Register 6-2 receives the input of priority ■, register 6-3
specifies inputs with priority level III. and,
Each of the three pins (U) of each register 6-1 to 6-3 corresponds to an input, and bit O is for all inputs 11 and bit 1.
indicates input Izk, and bit 2 indicates input crab 3t-. and,
By setting only one bit of these three bits as gold ◆l'', the priority order of each input is specified. (2
) to the input I, to the priority conversion circuit ``Itt'' priority ■
, input Ize priority order ■, register 6-1
Bit 2. Bit Ol register 6-2 of register 6-2
3 bit ITh'l'', and all remaining bits are set to 10#.

In this way, when setting the priority throne designation register fit,
The output H'o' of the AND circuit 9a of the priority order conversion circuit 7,
The output of the AND circuit 10a is sQI'.

The output of the AND circuit 11a is input 3 and 9, and the OR circuit 1
2a, the signal SI of priority level I is outputted, and the input 3 is outputted to (the input signal of the selection circuit 1).

At this time, if bit 0 of register 6-1 is %1'' and bit 1 and bit 2 are sO'', the output of AND circuit 9a is input ■I+ AND circuit 10a
The output of the AND circuit 11a is ◆0", and the output of the AND circuit 11a is 10"
Tona 9, OR circuit 12a K engineering is signal SI, (
The input signal of selection circuit 1) becomes input 11, and priority level I
This means that the input is input I. Then, bit 0 of register &-1 is %OI+.

If bit l is @ l rr and bit 2 is rarely 10'', then the input signal SI of the selection circuit 'EIIl is the same as above.

becomes Irikani 2. Similarly to this input signal SI, the priority level II signal 512 (input signal to the selection circuit 10) is determined by bit 0 of the register 6-2, and AND circuits 9b, 10b, and 11b. OR circuit 12
b Second, input I・1 is output, and signal SI3 (input signal of selection circuit 1) with priority level ■ is outputted from AND circuit 9 because bit l of register 6-3 is 11''.
c, 10c, 11c and OR circuit 12c to input I
2 is output.

Next, the operation of the selection circuit 1 is similar to that of the conventional priority input selection circuit shown in FIG.
1'', the output signal SO, becomes sl'', and the input signal S
When the input signal S 1 is sO'' and the input signal S 2 is 1#, the output signal S02 is % l N, and the input signal SI and SI2 are % O
", the output signal S03 becomes 11n.

Next, in the output conversion circuit 8, the output signal S of the selection circuit 1
AND circuit 13a when ol is 11n.

14 a + 15 a and OR circuits 16117 and 18, the entire contents of register 6-1 of priority designation register 6 are output to OI + 02 + 03, respectively. At this time, register 6-1 of priority specification register 6
Since the content of indicates the input signal of priority I, it is the same as outputting the input signal of priority I. In the case of the embodiment shown in FIG. 1, bit 2 of the priority designation register 6 is set to 1, so the output 03 is s1'', but the output signal SOI of the selection circuit 1 is %
1", but the input ■3 of the priority conversion circuit 7 is s1"
Therefore, nine crabs designated as priority I were correctly output from output 03.

Similarly, when the output signal S02 of the selection circuit 1 is 11'', the AND circuits 13b, 14b, 15b and the OR circuit 16
．． 17. At 18, the contents of register 6-2 in priority order designation register 6 are output from output 01 + 02t03, and the input signal with priority order ■ is input to input I! If it is Derotsukai, output 01 will be %1'', if it is rare in entering crab 2, output 02 will be deaf 1', and if it is rare in entering crab 3, output 03 will be
It becomes s1#. In this case, since the bit O of the register 6-2 is %IN, the output O1 becomes ``Hayabusa 1''. Then, when the output signal S03 of the selection circuit 1 is sl'', the AND circuits 13c, 14c, 15c and the OR circuit 16.
17. The contents of register 6-3 are output 01 by 18.
+ Output from 02.03.

In the above manner, input I I + ' 2 + ■3
Among them, when multiple input signals become s1'',
According to the priority designation register 6, only one output of the output OI for the input I, the output 02 for the input 2, and the output 03 for the input crab 3 becomes 11''.

In addition, if the contents of the priority order designation register 6 are rewritten behind the scenes by the program, input 'I +I2
The priority of + work 3 changes, and the output Or + 02
+03, the output that becomes %l" also changes.

In this way, in the embodiment shown in FIG. 1, a plurality of input signals are assigned priorities specified by the priority specification register 6, and a signal with a high priority is selected from among the input signals. It is configured.

In the above embodiment, the priority order designation register 6 is assigned to the register 6-1. Register 6-2. Although it was divided into registers 6-3, it does not matter whether you store 1 in one register or divide it into any number of registers, as long as the relationship between bits, priorities, and input signals is maintained. Furthermore, an AND circuit in the priority conversion circuit T1 selection circuit 1゜output conversion circuit 8,
OR circuit.

The configuration of the knot circuit can be any configuration as long as the input and output truth values are the same.

Here, we will explain the case where the input signals are three inputs, 1 + 2113, as an example, but the present invention is not limited to this, and even when there are other than three inputs, the priority order designation register The number of bits of 6 is set to the corresponding number, and the priority conversion circuit 72 selection circuit 1. There is no limit to the number of input signals as long as the configuration of the output conversion circuit 8 is changed to a configuration suitable for the configuration.

〔Effect of the invention〕

As explained above, according to the present invention, the priority of input signals is specified by the all-priority specification register.
It becomes possible to freely change the priority order, which has the effect of widening the range of processing and increasing the degree of freedom in connection destinations of input signals.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a preferential input selection circuit according to the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional preferential input selection circuit. 1...Selection circuit, 6...Priority designation register, 7...Priority conversion circuit, 8...Output conversion circuit.

Claims (1)

[Claims] a rewritable priority designation register that specifies the priority of input signals; a priority conversion circuit that converts a plurality of input signals into signals with priority; and a priority conversion circuit that converts a plurality of input signals into signals with priority; A selection circuit that selects a signal,
A priority input selection circuit comprising: an output conversion circuit that converts a high-priority signal selected by the selection circuit into an output signal corresponding to the original input signal.