JPS62169422A - Manufacture of epitaxial wafer - Google Patents

Abstract

PURPOSE:To prevent occurrence of misfit dislocation due to lattice mismatch between an epitaxial growth layer and a silicon single crystal wafer, by conducting, before epitaxial growth, a simple heat process for forming a surface relaxation layer in which a concentration of boron is decreased on a silicon single crystal wafer to which boron is added in a high concentration. CONSTITUTION:A silicon single crystal wafer 1, to which an impurity, boron is added such that it has a resistivity of 0.005OMEGAcm or below, is steam oxidized under normal pressures so as to segregate the boron in an oxide film 3. The concentration of boron on the surface of the silicon single crystal wafer is thereby decreased to form a relaxation layer 2. The oxide film is then removed by etching it with buffered fluoric acid. Thereafter, an epitaxial growth layer 4 having added boron is vapor phase grown by using 1,100 deg.C dichlorosilane as growth gas. In this manner, an epitaxial wafer an be formed without causing any misfit dislocation in the epitacial growth layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an epitaxial wafer manufacturing method, and more particularly to an epitaxial wafer manufacturing method for growing an epitaxial growth layer with few defects on a high concentration P++ silicon single crystal wafer.

[Conventional technology]

P/P epitaxial wafers, in which a P-type epitaxial growth layer is formed on a high-concentration P silicon single crystal wafer, are being developed for use in mega-pit class ultra-high integrated circuit devices. At this time, in order to improve device characteristics, high concentration P silicon single crystal wafers are required to have as low resistance as possible. Conventionally, to form this type of epitaxial wafer, boron was used at a high temperature of 11 [
A commonly used method is to perform epitaxial growth using a high-concentration P++ silicon single-crystalline wafer which has been added to lower the resistance and without performing any special treatment before epitaxial growth.

[1. Problems to be solved by the invention] In the conventional method described above, a large lattice mismatch occurs between the silicon single crystal wafer doped with a high degree of boron and the epitaxial growth layer grown thereon. If crystal defects such as misfit dislocations are generated in the wafer, the wafer may be curved. This has the disadvantage of deteriorating the characteristics of devices formed on the wafer.

[Means for solving problems]

In the epitaxial wafer manufacturing method of the present invention, the surface of a silicon single crystal wafer to which boron is added as an impurity so that the resistivity becomes 0.005 Ωcm or less is thermally oxidized, or an oxide film is formed by CVD growth or the like and then heated. The method is characterized by a step of treating the silicon single crystal wafer, a step of etching away the oxide film formed on the surface of the silicon single crystal wafer, and an epitaxial growth layer is formed on the silicon single crystal wafer.

〔Example〕

The present invention will be explained with reference to the drawings. FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention.

Add boron so that the resistivity is 0.0020,
Epitaxial growth on silicon single crystal wafers grown by the Czochralski method will be described. The silicon single crystal wafer 1 is subjected to normal pressure steam oxidation at 1000° C. for 5 hours to segregate boron in the oxide film 3 to reduce the boron concentration on the silicon single crystal wafer surface and form a relaxed layer 2.
was formed (Fig. 1(a)). After that, the oxide film is removed by etching with buffered hydrofluoric acid (see Figure 1).
b)). After that, 1100℃ dichloro7 run (8iH
zCA! z) was used as a growth gas to form an epitaxially grown layer 4 doped with boron to a thickness of 3 μm and a resistivity of 1 Ωα (FIG. 1(C)). the result,
It was possible to form an epitaxial wafer without misfit dislocations in the epitaxially grown layer.

The inventor of the present invention conducted detailed experiments and found that when the resistivity of the epitaxially grown layer is 0.5Ωα or more, when the resistivity of the silicon single-crystal wafer is 0.005ΩC or less, the wafer has a large curvature and misfit. It was confirmed that dislocations occur and deteriorate the characteristics of devices formed on wafers.

Figure 2 shows an epitaxial wafer (la) grown by the method described above and an epitaxial wafer (la) grown by the conventional method.
The expansion of the internally polished surface in b) shows a constant value of resistance 11111.

It can be seen that there is a relaxed layer with a reduced boron concentration formed in a thermal oxidation process on the high concentration P+ silicon single crystal wafer side under the 3 μm thick epitaxial growth layer of the epitaxial wafer according to the present invention.

〔Effect of the invention〕

As explained above, the present invention uses a simple thermal process to form a surface relaxation layer with a reduced boron concentration on a silicon single crystal wafer doped with boron at a high concentration, and then performs epitaxial growth. It is possible to prevent misfit dislocations from occurring due to lattice mismatch between the layer and the silicon single crystal wafer.

P/P consisting of a P-type epitaxial growth layer formed on a P/recon single crystal wafer doped with boron at a high concentration.
”+Epitaxial wafers are required when forming megabit-class ultra-highly integrated circuit elements, but in this case, epitaxial wafers are used for reasons such as increasing resistance to alpha rays and keeping the capacitance of groove capacitors large. It is desired that the P+1 silicon single crystal wafer has as low a resistance as possible.

In response to these demands, the present invention makes it possible to grow a high-quality epitaxial growth layer even if the resistance of a P++ silicon single crystal wafer is made low by an extremely simple method, and its industrial value is great. .

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the manufacturing process of an embodiment of the present invention, and FIG. 2 is an actual measurement example showing an example of the relationship between the spreading resistance value and the depth from the surface of the shrimp seal. In Fig. 1, 1 is a silicon single crystal wafer, 2 is a loose and oxidized layer, 3 is an oxide film, and 4 is an epitaxially grown layer. In FIG. 2, Ia) shows an epitaxial wafer produced by the method of the present invention, and (b) shows an epitaxial wafer produced by the conventional method. Agent Patent Attorney Susumu Uchihara (a) (b) (C) 34! Depth (l rudder)

Claims (1)

[Claims] A process of thermally oxidizing or heat-treating the surface of a silicon single crystal wafer to which boron has been added as an impurity so that the resistivity becomes 0.005 Ωcm or less or after forming an oxide film, and then oxidizing the silicon single crystal wafer formed on the surface of the silicon single crystal wafer. An epitaxial wafer manufacturing method comprising the steps of removing a film and performing epitaxial growth on the silicon single crystal wafer.