JPS59191323A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPS59191323A JPS59191323A JP6581683A JP6581683A JPS59191323A JP S59191323 A JPS59191323 A JP S59191323A JP 6581683 A JP6581683 A JP 6581683A JP 6581683 A JP6581683 A JP 6581683A JP S59191323 A JPS59191323 A JP S59191323A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- single crystal
- semiconductor substrate
- periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
Abstract
Description
【発明の詳細な説明】 本発明は半導体基板に関するものである。[Detailed description of the invention] The present invention relates to a semiconductor substrate.
本発明の目的とするところは半導体装置の製造プロモス
中に発生する結晶欠陥を極めて低く抑えることによp、
半導体素子の電気的特性を改善し、高歩留りの半導体装
置が得られる半導体基板を提供することにある。The purpose of the present invention is to suppress crystal defects occurring during the manufacturing process of semiconductor devices to an extremely low level.
An object of the present invention is to provide a semiconductor substrate that improves the electrical characteristics of a semiconductor element and allows a high-yield semiconductor device to be obtained.
従来の単結晶半導体基板は基板周辺部まで単結晶のため
、半導体装置製造プロセス中に基板周辺部より結晶欠陥
(基板周辺部よシ入る結晶欠陥は主としてスリップライ
ンと呼ばれる欠陥で以下スリップと略す)が入りやすく
、半導体装置の電気的特性を劣化させ、歩留シを低下さ
せる問題があった。Conventional single-crystal semiconductor substrates are single-crystalline to the periphery of the substrate, so crystal defects from the periphery of the substrate occur during the semiconductor device manufacturing process (crystal defects that enter from the periphery of the substrate are mainly defects called slip lines, hereinafter abbreviated as slips). There is a problem in that the electrical characteristics of the semiconductor device are deteriorated and the yield rate is lowered.
第1図は従来の単結晶シリコン基板の例である。FIG. 1 is an example of a conventional single crystal silicon substrate.
単結晶シリコン基板1け基板周辺部まで単結晶シリコン
1であり(第1図(a))、半導体装置の製造プロセス
(主に熱処理)を経るにつれて第1図(b)のように単
結晶シリコンの周辺部よりスリップ2が入る。これは、
基板周辺部の機械的損傷などの歪が熱応力により、この
歪を緩和しようとして周辺部にとどまらずに、単結晶シ
リコン基板中央部にまでスリップとして入るためである
。従って、スリップライン上に半導体素子が設けられて
いると、リーク電流の原因となり、半導体装置の特性の
劣化を招きひいては歩留シ低下をもたらす一因となる。The single crystal silicon substrate is made of single crystal silicon 1 up to the periphery of the substrate (Fig. 1 (a)), and as the semiconductor device goes through the manufacturing process (mainly heat treatment), it becomes monocrystal silicon as shown in Fig. 1 (b). Slip 2 enters from the periphery. this is,
This is because strain such as mechanical damage in the peripheral portion of the substrate is caused by thermal stress and, in an attempt to alleviate this strain, does not remain in the peripheral portion but enters the central portion of the single crystal silicon substrate as slip. Therefore, if a semiconductor element is provided on the slip line, it becomes a cause of leakage current, which causes deterioration of the characteristics of the semiconductor device, which in turn becomes a cause of a decrease in yield.
本発明は上記欠点を除き、特に単結晶半導体基板の周縁
部を多結晶半導体とすることによシ、基板の周辺部の歪
を緩和し、スリップが入シにくくし、該単結晶半導体基
板上に設けられた半導体装置の特性の劣化を防ぎ歩留シ
を向上させることができる。The present invention eliminates the above-mentioned drawbacks, and in particular, by making the periphery of a single crystal semiconductor substrate a polycrystalline semiconductor, the strain at the periphery of the substrate is alleviated, slippage is less likely to occur, and the single crystal semiconductor substrate is It is possible to prevent deterioration of the characteristics of the semiconductor device provided in the semiconductor device and improve the yield.
本発明は単結晶半導体基板の周縁部が多結晶半導体から
なることを%Iaとするものである。In the present invention, %Ia means that the peripheral portion of the single crystal semiconductor substrate is made of polycrystalline semiconductor.
以下、実施例VC基づき本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail based on Example VC.
第2図は、本発明を単結晶シリコン基板に適用し。FIG. 2 shows the present invention applied to a single crystal silicon substrate.
た場合の平面図(第2図(a))、および断面図(第2
図(b))である。即ち、単結晶シリコン基板3の周縁
部が多結晶シリコン4からなるシリコン基板である。本
発明の基板によシ、基板筒辺部の歪けは多結晶シリコン
4Vcよシ緩和され、スリップは単結晶シリコン基板3
には入らない。従って、単結晶シリコン基板3上に設け
られた半導体装置の特性は劣化せず歩留シも向上する。A plan view (Fig. 2 (a)) and a cross-sectional view (Fig. 2 (a))
Figure (b)). That is, the peripheral portion of the single crystal silicon substrate 3 is a silicon substrate made of polycrystalline silicon 4. With the substrate of the present invention, the distortion at the cylindrical side of the substrate is alleviated compared to that of polycrystalline silicon 4Vc, and the slippage of the monocrystalline silicon substrate 3
It doesn't fit in. Therefore, the characteristics of the semiconductor device provided on the single-crystal silicon substrate 3 are not deteriorated and the yield is improved.
尚、単結晶シリコン基板の周縁部の多結晶シリコンの厚
さは幾らでもかまわないが、基板の厚さと同程度にする
のが望ましい。このような、半導体基板は例えば、単結
晶半導体育成後に既知の方法例えばCVD法等により多
結晶半導体を単結晶半導体の表面に形成し、基板を切り
出す方法等が考えられる。Note that the thickness of the polycrystalline silicon at the periphery of the single-crystal silicon substrate may be any desired thickness, but it is preferable that the thickness be approximately the same as the thickness of the substrate. Such a semiconductor substrate may be produced by, for example, growing a single crystal semiconductor, forming a polycrystalline semiconductor on the surface of the single crystal semiconductor by a known method such as CVD, and then cutting out the substrate.
以上、詳細に説明したように本発明の半導体基板は基板
周辺部からスリップが入シにくく、半導体装置の電気的
特性が向上し、歩留シ向上に寄与できる。As described above in detail, the semiconductor substrate of the present invention is less prone to slippage from the periphery of the substrate, improves the electrical characteristics of the semiconductor device, and contributes to improved yield.
第1図(aJは従来の単結晶シリコン基板を示す平面図
、第1図(b)は半導体装置製造プロセスを経た単結晶
シリコン基板の平面図、第2図(a)および第2図(b
)は本発明をシリコン基板に適用した実施例の平面図お
よび断凹図である。
尚、図に2いて
1.3・・・・・・単結晶シリコン基板、2・・・・・
・スリップ、4・・川・多結晶シリコン。
荊1問C112)
9Fl[レノ
)tデ 2 回 tllン
第2図(めFig. 1 (aJ is a plan view showing a conventional single crystal silicon substrate, Fig. 1 (b) is a plan view of a single crystal silicon substrate that has undergone a semiconductor device manufacturing process, Fig. 2 (a) and Fig. 2 (b)
) are a plan view and a cutaway view of an embodiment in which the present invention is applied to a silicon substrate. In addition, 2 in the figure shows 1.3...single crystal silicon substrate, 2...
- Slip, 4... River - Polycrystalline silicon.荊1Question C112) 9Fl [Reno] tde 2 times tlln Fig. 2 (Me)
Claims (1)
を%徴とする半導体基板。A semiconductor substrate characterized in that the peripheral portion of a single crystal semiconductor substrate is made of a polycrystalline semiconductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6581683A JPS59191323A (en) | 1983-04-14 | 1983-04-14 | Semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6581683A JPS59191323A (en) | 1983-04-14 | 1983-04-14 | Semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59191323A true JPS59191323A (en) | 1984-10-30 |
Family
ID=13297923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6581683A Pending JPS59191323A (en) | 1983-04-14 | 1983-04-14 | Semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59191323A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10046892B2 (en) | 2013-12-26 | 2018-08-14 | Shanghai Hongyan Returnable Transit Packagings Co., Ltd. | Tamper-evident device and valve using same |
-
1983
- 1983-04-14 JP JP6581683A patent/JPS59191323A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10046892B2 (en) | 2013-12-26 | 2018-08-14 | Shanghai Hongyan Returnable Transit Packagings Co., Ltd. | Tamper-evident device and valve using same |
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