JPS62169275A - Memory system - Google Patents

Abstract

PURPOSE:To attain an image turned inside out to be written at an optional position at a high speed by providing a means which converts a data to be written on a memory cell to the image of a mirror image. CONSTITUTION:A data pattern requested to be written inside out is impressed on a bit position inside out circuit 1 through a data bus 100. At a control part 4, a bit of information which represents that the data pattern is written inside out is set in advance with a microprocessor, etc. Thereby, the data pattern in which the bit position is turned inside out is outputted to an output bus 101 in the bit position inside out circuit 1, then being impressed on a shifter 2. The data pattern that is turned inside out and is shifted to an objected bit position is outputted to an output bus 102 in the shifter 2, and the pattern is written on a memory 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method of configuring a memory system, and particularly to a memory system suitable for writing data upside down when the memory system is used in a display device or the like. Concerning the method of construction.

[Conventional technology]

Conventionally, a method has been known in which, when writing a data pattern to a memory system, the data pattern is written after shifting the bit position through a shifter 2 as shown in FIG. This is as described in Japanese Patent Application Laid-Open No. 112644/1983. According to this method, by setting the shift amount of the shifter 2 in the control unit 4 of FIG. 2 using a microprocessor or the like, data shifted by an arbitrary number of bits can be written into the memory at high speed.

This is an effective method for reducing the burden on software such as a microprocessor that controls writing and shortening processing time, especially when writing characters and graphics into the memory system of a bitmap display device. However, in this method, no consideration was given to the writing of data patterns such as characters and figures in an upside-down image in terms of hardware.

For example, when such a memory system is applied to a display device for images, characters, and graphics, a reversed image may be required to accent the characters. Although conventional methods can quickly write the necessary part of an image shifted by an arbitrary number of bits into the memory 3, if the above-mentioned reversed pattern was required, software processing had to be relied upon. .

[Problem that the invention seeks to solve]

For this reason, in the prior art described above, when writing a data pattern with the bit positions reversed into the memory, the data pattern must be converted into a reversed pattern using a microprocessor or the like.

There is a problem in that the burden on software etc. increases and the processing time associated with this increases.

The object of the present invention is to not only write a pattern to any bit position in memory at high speed by adding simple hardware, but also to write a pattern to any bit position at high speed even for a reversed pattern of a given data pattern. An object of the present invention is to provide a memory system that can quickly accent a character or figure using a reverse pattern when this memory system is applied to a display device or the like.

[Means for solving problems]

In order to achieve the above object, one aspect of the present invention includes a bit position reversing means (means for converting into a reversed image) between the data bus and the memory. This conversion means may be provided between the data bus and the shifter, or between the shifter and the memory.

[Effect]

The data pattern to be written as a mirror image in FIG.
is applied to Information indicating that the data pattern is to be written upside down is previously set in the control unit 4 by a microprocessor or the like. As a result, a data pattern with the bit positions reversed is output to the output bus 101 of the bit position reversing circuit 1 and applied to the shifter 2. By setting in advance in the control unit 4 a shift amount, which specifies how many bits of the data pattern to be written to be shifted and written to the memory, by a microprocessor, etc., the output bus 102 of the shifter 2 has the desired bit position. The reversed data pattern shifted to is output, and this pattern is written into the memory 3.

If the data is not written upside down, the data pattern applied via the data bus 100 can be passed through the output bus 101 to the shifter 2 by setting information in the control unit 4 using a microprocessor or the like to indicate that the data will not be written upside down. shifted and written to memory 2.

In Figure 3, the order in which the bit positions are flipped is shifter 2.
1 in terms of operation of this method, just because it is after being shifted by
There is no essential difference. That is, the write data pattern applied from the data bus 100 is shifted by the shifter 2 by the shift amount set in the control section 4, and is applied to the bit position reversing circuit 1 via the shifter output bus 105. If the pattern should be written upside down, the pattern is reversed in the bit position reversing circuit 1 according to instructions from the control unit 4, and written into the memory 3 via the output bus 106.

In the case of a pattern that does not need to be flipped, data of the same pattern as the output bus 105 of the shifter 2 is outputted to the output bus 106 of the bit position flipping circuit 1 and written into the memory 3 according to instructions from the control unit 4.

The write control section 5 is a section for writing only necessary portions of the data pattern given to the memory 3. That is, the output 107 from the write control unit 5 is one word (for example, one 8-bit word or one 16-bit word) constituting the memory 3.
(words, etc.) are connected to the write control terminals of the memory elements corresponding to the respective bits.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIGS. 1 and 4 to 8. Here, the case where the data buses 100, 101 and 103 are 8 bits will be explained as an example, but the bus width of the data buses 100, 101 and 103 may be any bit as long as it is 2 bits or more. Furthermore, the bus widths of the data buses 100 and 101 that input and output to the bit position inverting circuit 1 are the same number of bits, but the bus widths of the data buses 101 and 102 that input and output to the shifter 2 do not necessarily have to be the same number of bits.

(This also applies to the data buses 105 and 106 that input and output to the bit position flipping circuit 1 in FIG. 3, and the data buses 100 and 105 that input and output to the shifter 2.) FIG. , which is an example of a concrete implementation means of the bit position flipping circuit 1. In this example, data bus 1
Since 00 is 8 bits, 8 switch means 10~
This is realized by 17. In the figure, switch means 10~
17 is switched to the a side as shown by the solid line, but this can be simultaneously switched to the b side as shown by the dotted line by the control line 103 from the control section 4. In the same figure, switch means 10
-17 is switched to the a side, the data pattern is not reversed. Further, when switching to the b side, the data pattern is reversed.

FIG. 5 shows the input data bit pattern bQ-b when the switch means 10 to 17 in FIG. 4 are switched to bs.
7 (pattern applied to data bus 100; same figure (a)
)) and flipped data bit patterns bQ'~b
7' (pattern output to the data bus 101; FIG. 7(b)) shows the relationship. When the control line 103 specifies that the flip is to be performed, the process shown in FIG.
) data patterns ■~■ are changed to data patterns ■'~ as shown in FIG.
■' respectively. The converted data pattern is applied to shifter 2 as described above.

Shifter 2 can be constructed in various ways. For example, it can be realized by a combination of shift registers and switch means, but the means for realizing it is not particularly limited. However, here, as an example, a shifter 2 using a combination of switch circuits as shown in FIG. 6 is shown. An internal switch means is switched by a control line 104 from the control section 4, and the data pattern from the data bus 101 is shifted and outputted to the output bus 102.

The process up to writing the reverse pattern in the memory 3 will be explained with reference to FIG. In addition, here, Fig. 5 (a)
Turn over the pattern of right-pointing arrows shown in (left and right), shift it 4 bits to the right, and shift it 4 bits from the right end (b4 to b7).
) will be explained as being written to memory 3. In FIG.

The pattern (a) applied from the data bus 100 is converted into the reversed pattern (b) by the bit position reversing circuit 1 as described above, and is applied to the shifter 2. The shifter 2 shifts the pattern (b) to the pattern (C) in response to an instruction from the control unit 4 (for example, by switching a switch in a shifter using switch means as shown in FIG. 6). Next, the content of the output 107 from the write control unit 5 (
By e), the contents of the output bus 102 of the shifter 3 are written only to the bits of the memory 3 corresponding to the shaded parts in (e), and in the end, only the leading part of the leftward arrow as shown in (cl) in the same figure is written to the memory 3. written in.

As described above, the conversion from pattern (a) to pattern (b), which was conventionally performed by software processing such as a microprocessor, in order to write the reversed pattern to the memory 3 can be easily performed by the bit position reversing circuit, and the software The first effect is to reduce the burden on people.

Furthermore, as can be seen by comparing an example of the bit position reversing circuit 1 in FIG. 4 with an example of the shifter 2 in FIG. 6, the bit position reversing circuit 1 can be realized by adding a small amount of hardware compared to the shifter 2.

In particular, in this embodiment, the bit position reversing circuit 1 and shifter 2
However, in such a case, the bit position inverting circuit can always be realized with one stage of switch means, whereas in the shifter 2, as the bus width increases, the number of switch stages also increases. Therefore, when the bus width is large (for example, 16 bits or 32 bits wide), the second effect is that the increase in cost due to the addition of the bit position flipping circuit 1 can be kept small. This is an effect unique to the configuration using switch means.

Although the switching means has been described above, it goes without saying that this includes, for example, a data selector circuit realized by the logic circuit shown in FIG.

Next, another embodiment of the present invention will be described with reference to FIG. 9th
The diagram shows the configuration of FIG. 1 with the addition of a register 6 for temporarily storing data read from the memory 3, and a bus switch 7 for switching a data line 109 from the register 6 and a data bus 100. In this embodiment, memory 3
This has the effect that the data pattern already written in the memory 3 can be rewritten in an arbitrary position in the memory 3 as an inverted image. Assume now that a pattern 300 has been written in the memory 3 in advance as shown in FIG. 10(a). This pattern 300 is executed by memory 3 word by word in memory 3.
The data can be read into register 6 by read data path 108. The read data is applied to the bit position reversing circuit 1 by switching the bus switch 7, and can then be written to the memory 3 again using the same procedure as explained in the previous embodiment. As a result, it is possible to write a pattern in the memory 3, such as a pattern 301 in FIG.

Next, a third embodiment will be explained with reference to FIG.

FIG. 11 shows an example in which the present invention is applied to a color or monochrome multi-gradation graphic display. Generally, in such displays, to obtain color or multi-gradation.

It is equipped with a plurality of memories 3. Here, each memory 3 will be referred to as a "plane 200". 11th
In the figure, n planes 200 are provided. As long as the value of n is 1 or more, it does not matter how many sheets there are. plain 200
The inside of this is the same as the embodiment described in FIG. 9.

According to this embodiment, the effects described in the first embodiment and the second embodiment can be obtained for the memories 3 of a plurality of planes 200 at once.

In other words, the larger the bus width of the data bus 100,
Also, as the number of planes 200 increases, the amount of data that can be turned over at once increases, which increases the burden on the software for processing.

is reduced, and processing time is also reduced accordingly.

Although the present invention has been described above using three embodiments, it is clear that the present invention is a memory system that can be applied to a wide range of applications such as graphic displays, buffer memories for printers, and memories for processing image data. Furthermore, although the embodiments shown in FIGS. 9 and 11 have been explained using the basic configuration of FIG. 1, the configuration of FIG. 3 may be applied to the embodiments of FIGS. 9 and 11. Needless to say.

〔Effect of the invention〕

According to the present invention, by adding simple hardware, the reverse pattern of a given data pattern can be written to the memory 3 at the same processing speed as the conventional technology, which simply writes the data pattern to an arbitrary bit position of the memory 3. This has the effect of improving system response in applications that create reverse data patterns.

[Brief explanation of drawings]

1 and 3 are basic configuration diagrams of the present invention, FIG. 2 is a diagram for explaining a conventional example, and FIG. 4 is a bit position reversing circuit 1.
FIG. 5 is an explanatory diagram of pattern reversal, FIG. 6 is a diagram showing an example of shifter 2's completion, and FIG. 5 is an inverted putter? FIG. 1 is a diagram showing an example of the configuration of the switch means, FIGS. 9 and 11 are diagrams showing an embodiment of the present invention, and FIG. 10 is an explanatory diagram thereof. 1...Bit position reversal circuit, 2...-shifter, 3...
-Memory, 4...control unit, 5...write control unit. 1st/j/7 21st month Riri n Kazu Yoko/〃 4th Sendai S Mi (d) (b) Akira Saioguchi 7th S~1 79th field (k)) 11th field/ρθ

Claims (1)

[Claims] 1. At least a memory element, a data bus that sends data to be written to the memory element, a shifter that can shift data on the data bus by an arbitrary number of bits, and a shifter that can shift data on the data bus by an arbitrary number of bits. What is claimed is: 1. A memory system comprising a write control section for giving a write permission signal to the memory element, the memory system comprising means for converting data to be written into the memory element into an inverted (mirror image) image. 2. The memory system according to claim 1, wherein the conversion means is installed between the data bus and the shifter. 3. Adding means for temporarily storing data read from the memory element, and a bus switch for selecting one of the data stored in the temporary storage means and the data on the data bus; 3. The memory system according to claim 2, wherein the output is input to said converting means.