JPS61124984A - Data transfer apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an information processing device, and particularly to a data transfer device used in the field of high-speed data transfer such as a BITMATSU 1 display device.

BACKGROUND OF THE INVENTION In conventional data transfer, word-based DMA (Direct
ct Memory Access) transfer method is commonly used. However, in the case of data transfer in a bitmap display device, one pixel does not necessarily correspond to one word of data. (For example, in the case of a binarized image, one pixel is one bit.) Therefore, a high-speed data transfer device that can specify the transfer amount in units of bits is required.

Therefore, we have previously proposed a data transfer device that performs pit position alignment between source data and destination data, as shown in FIG. (%Application No. 59-100965) In the same figure, 201 is the second back 7.202 of 1 word (n bits) that stores the read transfer source data.
When storing new transfer source data in the second buffer 201, a 1-word (n-bit) first buffer stores the data previously held in the second buffer 1201;・A barrel shifter that receives 2n consecutive bits of the second buffer 1 as input and outputs consecutive n bits from the bit position selected by the selection signal POINT. For the bits selected by the signal MASK, performs the operation specified by the signal MOD between the output data (sofa 204 and the corresponding transfer destination data) and outputs the result, and for the bits that are not selected, It is an arithmetic unit that outputs data as is.

The operation of the conventional data transfer device configured as described above will be described below with reference to FIG. 3 as well. In the same figure, A) is an example of data at the transfer source, where ■, ■, and ■ are word data, and the shaded portion is the data area to be transferred, and 5ADR indicates the starting bit position of the transfer source. (a) is an example of data at the transfer destination, @+ @ +■ is each word data, the shaded area is the area to which the data in the shaded area in a) is to be transferred, and DADR indicates the position of the first peer at the transfer destination. .

First, the control unit 206 controls the 5ADH of a) and the DADR of
A POINT signal is generated from this point. For example, one word (n bits) of MSB (MostSignify
cant Bit) to the pit position "Q', LSB (L
east 51gn1ficant Bit) as the pit position "n-1", the PINT signal is the pit position 5ADR of the first buffer of 5ADH,; It suffices if it becomes the signal to select. (For example, n=16SADR:=”11
”, DADR="14' and ftLtd, a signal for selecting the pit position "13" of the first buffer. It is shown at position P in FIG. ) Figure 3 C) to E) are PO at the control unit.
Input buffer (1st, 2nd) after INT signal is determined
(buffers 202 and 201 are shown connected) and the state of the output buffer 204 at each step.

) indicates that transfer data ■ has been read into the second buffer 7201, and n bits ( ) consecutive from the pit position of P
1 word) is stored in the output buffer 204 through the barrel shifter 203. The control unit 206 causes the arithmetic unit 206 to
By generating a signal MASK for controlling a desired bit and a desired operation control signal MoDt-, data can be transferred in word units to the word @. The following 2) reads the next data ■ into the second buffer 201 and transfers it to the first buffer 201.
2 shows the state in which the contents of the old second buffer are stored.

(At this time, the data to be transferred to ■ is in the output buffer 7204.) E) is the next data ■ to the second buffer 7201.
is read and ■ is stored in the first buffer 12o2. (At this time, the data to be transferred at ■ is in the output buffer 204.) The conventional method described above is effective if the transfer direction is limited to positive (right to left) on the main scanning line.

However, for certain purposes, it becomes necessary to transfer in the negative direction on the main scanning line. For example, when moving the window (rectangular area on the bitmap memory) shown in Figure 4 (a), if the source data area 1 and the destination data area 2 overlap, conventionally it was only possible to transfer the window in the (a) direction. ,
If the transfer in the sub-scanning direction is positive (top to bottom), the valid destination data may have been rewritten when transferring at point a, making correct transfer impossible, or the area as shown in By dividing the area into smaller areas, data is first transferred from the overlapping area (indicated by diagonal lines), and then other areas are transferred.

Problems to be Solved by the Invention In such conventional devices, the previously read data is
Since processing is performed while fixing it to the SB side, data transfer on the main scanning line is fixed in the positive direction, and transfer in the negative direction cannot be executed.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data transfer device that can transfer data defined by the amount of bits in both directions on a main scanning line with a simple configuration. .

Means for Solving the Problems In order to solve the above problems, the present invention includes a flag indicating the transfer direction on the main scanning line, and changes the order of data input to the barrel shifter according to the contents of the flag. outputs data that matches the transfer in both directions.

Operation According to the above-described configuration, the present invention swaps the read order by the bus switching circuit during transfer in the negative direction on the main scanning line, combines two consecutive words of the transfer source, and selects one word of data from among them that corresponds to one word of the transfer destination data. By selecting data, transfer in the negative direction on the main scanning line can also be performed.

Embodiment FIG. 1 is a block diagram showing an embodiment of a data transfer device of the present invention. In FIG. 1, configurations similar to the conventional one are indicated only by the correspondence of numbers with those in FIG. 2, and their explanations are omitted.

Figure 1 101 is in is2 diagram 201, 102 is in 202,
103 becomes 203, 104 becomes 204, 1o6 becomes 205
correspond to each. In FIG. 1, 107 is a flag indicating the transfer direction on the main scanning line, and 1Q8 indicates that if the output DIR of the flag 107 is a forward transfer signal, the barrel shifter 103 is sent to the first buffer 102 . The contents of the second buffer 101 are output in the same order, and if DIR is a negative transfer signal, the first buffer 102 . This is a bus switching circuit that changes the order of the contents of the second buffer 101 and outputs it.
9 has the functions of the control unit 206 in FIG.
This control unit has a function of changing the order of generated MASK signals when the signal indicates a negative direction transfer.

The operation of the data transfer device according to an embodiment of the present invention configured as described above will be described below with reference to FIG. 5 as well. (Transfer in the forward direction is the same as the conventional one, so only the transfer in the reverse direction will be explained.) In the figure, a) is an example of data from the transfer source, and ■, ■, and ■ are word data, and are shaded with diagonal lines. The indicated part is the data area to be transferred, and 5ADR' indicates the starting bit position of the transfer source. (a) is an example of data at the transfer destination, ■, ■, and ■ are word data, respectively.The shaded area is the area to which the data in the shaded area in a) is to be transferred, and DADR' indicates the first bit position of the transfer destination. .

First, the control unit 109 controls the 5ADH' of a) and the DAD of
A POINT signal is generated from R'.

(This can be done using a method similar to that shown in the conventional example.

In FIG. 6, the input buffers (1st and 2nd buffers 102 and 101) are connected after the POINT signal is determined by the control unit 109. 12 shows the states of the input and output buffers 104 of the barrel shifter 103 at each step, where the order of the contents of the input buffers is changed word by word by the bus switching circuit 108. Han indicates a state in which transfer data ■ has been read into the second buffer 101. However, in this case, since there is no valid transfer data in the n bits consecutive from the bit position of P', no transfer is performed, and the next transfer source data (2) is read. 2) in the same figure transfers the transfer source data ■ to the second buffer 1.
01 indicates the read state, and consecutive n bits from the bit position of P' of the data whose order has been changed by the bus switching circuit 10B are stored in the converter sofa 1o4 through the barrel shifter 103. The control unit 109 causes the arithmetic unit 106 to
By generating a signal MASK for controlling a desired bit and a desired arithmetic control signal MOD, data transfer in word units can be performed in the word . Below (e) is the second buffer 11
A state is shown in which data ■ is read into o1 and the contents ■ of the old second buffer are stored in the first pan 77102. At this time■
There is data in output buffer 104 to be transferred to. e)
is the second because there is valid data in the input buffer.
This shows the state in which the contents of the buffer 11o1 have been transferred to the first buffer 1o2. At this time, the data to be transferred to @ is in the output buffer 71o4.

As described above, according to the present invention, by simply adding a flag indicating the transfer direction to a conventional data transfer device and a bus switching circuit that switches the data reading order depending on the contents of the flag, transfer in not only the positive direction but also the negative direction can be performed. I can do it.

In the case of the example shown in Figure 6, it was necessary to read two words of data at the start of the transfer and to transfer the contents of the second buffer to the first buffer at the end of the transfer. This is because the data to be transferred to the previous ■ spans the transfer source ■ and ■, and the data of the transfer source ■ is
This is because it is necessary when transferring data in the positive direction, and in the case of a bit shift in the source data (I) and destination data (RO) as shown in Figure 6, this processing is necessary when transferring data in the positive direction, and when transferring data in the negative direction. Not necessary.

Effects of the Invention The data transfer device of the present invention has a simple configuration and can transfer data on the main scanning line by providing a flag indicating the transfer direction on the main scanning line and a bus switching circuit that switches the input order of data depending on the contents of this flag. It is possible to transfer data defined in bit units not only in the positive direction but also in the negative direction, and its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data transfer device according to the present invention,
FIG. 2 is a block diagram of a conventional data transfer device, FIG. 3 is a diagram explaining the operation of the conventional data transfer device, FIG. FIG. 6, which is an explanatory diagram of the operation of the embodiment, is a diagram showing an example of bit misalignment between transfer source data and transfer destination data. 101... Second buffer, 102...
・First buffer, 103...barrel shifter,
1o4... Output cover 7.106...
Arithmetic unit, 107...Flag, 108...
・Bus switching circuit, 109-...Control unit 0 Fig. 1 (Rolling brother Abu) (O is mimejishichi 9) (IL Mideni 7) Fig. 2 (# Yomoe yen Fig. 3 5AT ) R to output: 7F Fig. 4 Fig. 5 Competing for the next generation ○-shi Fig. 5 DA D R'

Claims (2)

[Claims] (1) A flag that stores information on the data transfer direction on the main scanning line in a two-dimensional memory space and two consecutive words of data from the transfer source (2n bits if 1 word is n bits)
first and second buffers that hold , in the order in which they are read;
The outputs of the first and second buffers are used as first and second inputs, and when the flag is in a first state, the first input is used as the first output, and the second input is used as the second output. , the flag is the second
In the state of , a bus switching circuit that sets a first input as a second output and a second input as a first output, a control section that outputs a selection signal, and a first and second bus switching circuit of the bus switching circuit. a barrel shifter that receives the output of the controller and outputs n consecutive bits from the bits selected by the selection signal output by the control unit; and a third buffer that holds the output of the barrel shifter, the third buffer A data transfer device characterized in that the output of is used as write data. (2) The third buffer is an arithmetic unit that takes the output of the barrel shifter as a first input and one word of the corresponding transfer destination as a second input, and the control unit outputs a selection signal for the barrel shifter and performs the calculation. 2. The data transfer device according to claim 1, wherein the data transfer device has a structure that outputs a control signal to the arithmetic unit, and uses the output of the arithmetic unit as write data.