JPS62169256A - Microcomputer for vehicle - Google Patents

Abstract

PURPOSE:To improve the precision and the responsiveness of period measurement by providing a timer control circuit with a latch circuit where a relative time of the preceding measured pulse is held in accordance with the inversion of a pulse to be measured. CONSTITUTION:A frequency dividing counter 1 integrates a clock signal according as the time elapses. The first latch circuit 2 holds a relative time for the inversion of the current measured pulse, which is the value of the frequency dividing counter 1, by a latch timing signal synchronized with the inversion of a pulse signal to be measured. The second latch circuit 7 holds the relative time for the inversion of the preceding measured pulse which is the value of the first latch circuit 2. Relative times of latch circuits 2 and 7 are automatically updated for each pulse input signal to be measured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vehicle microcomputer that controls a vehicle such as an automobile.

[Conventional technology]

Automobile control includes engine control, clutch control, transmission control, and vehicle speed control, and the pulse signals detected for each of these applications include engine rotation speed, clutch rotation speed, transmission rotation speed, and vehicle speed. There is. For this reason, many microcomputers for automobiles are generally equipped with a timer control circuit for measuring Noculus signals.

FIG. 2 is a diagram showing the configuration of a conventional vehicle microcomputer. In FIG. 2(a), 101 is a central processing unit (CPU) that calculates and controls the engine speed, clutch speed, transmission speed, or vehicle speed using detection signals necessary for vehicle control, and 102 is a random access CPU. Memory (RAM), 103 is read-on memory (ROM), 1
04 is a communication control circuit that is prepared in advance in a high-end microcomputer and communicates with peripheral control circuits, and 106 and 107 are signal input/output interface circuits (POR) with peripheral control circuits.
T), 108fd data bus, 109 address bus,
110, 111, and 112 are control paths.

Further, FIG. 2(b) is a detailed circuit diagram of the timer control circuit 105 shown in FIG. 2(a). In the figure, l is a branch counter that integrates the Nockles number of the clock signal (CL), and the relative time can be determined by the time change of the integrated value. 2 is a latch circuit that holds the integrated value of branch counter 1 using a latch timing signal (St), and 3 is a CPU I
An intermittent control circuit that controls communication between the latch circuit 2 and the data bus 108 by a read signal (So) controlled by O1, and 4 and 5 are D-type flip frogs, and 6 is an N
These constitute a waveform shaping circuit for the pulse signal to be measured (Si). Furthermore, Sf is an internal detection signal that notifies that there is a pulse input.

Next, the operation will be explained. Pulse signal to be measured (Si)
The latch timing signal (st) and internal detection signal (Sf) are generated by the inversion of . Further, the latch circuit 2 holds the integrated value of the branch counter 1 using the latch timing signal (St), and holds the relative time with respect to the inversion of the signal to be measured (Si).

A program procedure is required to calculate the period of the pulse signal to be measured (Si). For each change in the internal detection signal (Sf), calculate the difference between RAMI O2, which stores the relative time at the time of reversal of the pulse to be measured (Si) last time, and the relative time at the time of reversal of the current pulse to be measured (Si). At the same time, the relative time at the time of inversion of the current pulse to be measured (St) is stored in the RAM 102 as the relative time at the time of inversion of the previously measured pulse (Si).

The resolution of relative time is determined by the period of the clock signal (CL), but in reality, the time required for the program processing procedure is long, so improvement in accuracy and responsiveness cannot be expected.

[Problem that the invention seeks to solve]

Since the conventional vehicle microcomputer is configured as described above, a program processing procedure is required in the timer control circuit 105, and the time required for this GLODARAM processing procedure impairs the accuracy and responsiveness for period measurement. There was a problem with this.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a microcomputer for a vehicle that can improve accuracy and responsiveness for period measurement.

[Means for solving problems]

In the vehicle microcomputer according to the present invention, the timer control circuit is provided with a second latch circuit that holds the relative time of the previous pulse to be measured in accordance with the reversal of the pulse to be measured.

[Effect]

In this invention, since the second latch circuit holds the relative time of the previous pulse to be measured, and the first latch circuit holds the relative time of the pulse to be measured this time, each time the pulse to be measured is reversed, The necessary program processing procedures and processing time are no longer necessary, and Glodarum processing can be performed only when necessary for arithmetic control.

〔Example〕

FIG. 1 is a configuration diagram of a timer control circuit of a vehicle microcomputer according to an embodiment of the present invention. In the figure, 1 is a frequency division counter that integrates the clock signal (CL), and 2 is a latch timing signal (st) that holds the value of the frequency division counter 1 and holds the relative time when the pulse to be measured this time is reversed. 3 is an intermittent control circuit that controls communication between the first latch circuit 2 and the data bus 108 using a read signal (Sol) from the CPU; 4;
Reference numeral 5 indicates a D-type 7-rig frog circuit, and reference numeral 6 indicates a NAND gate, which constitute a waveform shaping circuit for the pulse signal to be measured (Si). Furthermore, Sf is an internal detection signal.

7 is a second latch circuit that holds the value of the first latch circuit 2 using a latch timing signal (st) and holds the relative time at the time of the previous measured pulse reversal; 8 is a readout signal (802) from the CPU; This is an on/off control circuit that controls communication between the second launch circuit 7 and the data bus 108.

Next, the operation will be explained. Since the branch counter 1 integrates the clock signal (CL) over time, the integrated value is a relative time. In addition, the first latch circuit 2 receives the value of the frequency division counter 1, ie, the value to be measured this time, by a latch timing signal (St) synchronized with the inversion of the pulse input signal to be measured (St). It holds the relative time at the time of cis inversion. The second latch circuit 7 receives the same latch timing signal (S
t) is the value of the first latch circuit 2, which is the relative time when the pulse to be measured was previously inverted. Therefore, the measured
The relative time of each latch circuit 2.7 is automatically updated for each signal input signal (St), and conventional grogram processing is not required.

Incidentally, when calculating the engine speed, clutch speed, transmission speed, or vehicle speed, the period can be measured based on the difference in relative time between the latch circuits 2 and 7, if necessary. Further, in the above embodiment, the case of a microcomputer for an automobile was explained, but it goes without saying that the present invention can also be used for detecting the rotation speed in other industrial machines and the like.

〔Effect of the invention〕

As described above, according to the present invention, the timer control circuit is provided with the second latch circuit that holds the relative time of the previous measured notarus in response to the reversal of the measured f pulse. It is also possible to eliminate the time required for the grogram, and it is possible to improve the accuracy and responsiveness for period measurement.

Moreover, there is an effect that the function can be further improved for the same program processing.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a timer control circuit of a vehicle microcomputer according to an embodiment of the present invention, and FIG. 2 (!L)
, (b) are a configuration diagram of a conventional vehicle microcomputer and a configuration diagram of its timer control circuit, respectively. 1... Frequency division counter, 2... First latch circuit, 7
. . . second latch circuit, 101 . . . central processing unit. 102... Random access memory, 103... Read-on memory, 105... Immediate control circuit, 108
...Data bus, 109...Address bus, 110
゜111.112...Control path. Note that the same reference numerals in the figures indicate the same or corresponding parts. 18 108-Tarth Figure 2 (0) Figure 2 (1)

Claims (1)

[Claims] A central processing unit that calculates detection signals such as vehicle engine speed, clutch speed, transmission speed, or vehicle speed, random access memory, lead-on memory, timer control circuit, data bus, address bus, and control. and a first latch circuit, wherein the timer control circuit has at least a frequency dividing counter and a first latch circuit capable of measuring a relative time accompanying a change in the input pulse.
1. A microcomputer for a vehicle, comprising a second latch circuit that holds data of the latch circuit.