JPS62168469A - Digital video processor - Google Patents

Abstract

PURPOSE:To exactly eliminate a periodical noise by applying to a subtracter a read-out signal being not that of a memory which has stored a sudden large amplitude noise but that of a memory which has stored a noise immediately before the large amplitude noise is mixed, when said large amplitude noise but that of a memory which has stored a noise immediately before the large amplitude noise is mixed, when said large amplitude noise has been mixed in. CONSTITUTION:A video signal which is applied to an input terminal 1 is converted to a digital signal by a converter 2, and applied to a subtracting circuit 6 through a processing part 3, a D/A converter 4, and an LPF 5. An output of the LPF 5 is provided to a storing circuit 9, in which a periodical noise is detected and stored alternately at every one line in the first line memory 9d and the second line memory 9e. The periodical noises which have been stored in the first and the second line memories are sent alternately to the subtracting circuit 6, and from the output video signal of the LPF 5, the periodical noise is eliminated. In this state, in case when a sudden large amplitude noise has been detected by a comparing circuit 10, a selective switch 9f is controlled so that the noise is fetched from the memory which has stored the noise immediately before, by avoiding read-out from the memory which has stored the large amplitude noise.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention converts an analog input video signal obtained by reception, playback, etc. into a digital signal and digitally processes it, and also converts the analog input video signal obtained by reception, playback, etc. The present invention relates to a digital video processing device that converts a signal into an analog output video signal and outputs the same.

[Conventional technology]

Conventionally, in the field of video processing, when performing processing such as demodulation on an analog video signal such as an NTSC television signal or a high-definition television broadcast signal obtained by reception, playback, etc., the analog video signal is Signals are converted into digital signals and digitally processed to simplify the circuit configuration, such as adjustment of two circuits.

Digital video processing devices of this type, such as digital television receivers and video discs, which are configured to perform digital processing, convert analog input video signals obtained through reception, playback, etc. into digital signals using digital converters. At the same time, the digital signal is input to a digital processing section and subjected to Type 4 digital processing, and the digitally processed digital signal is converted into an analog output video signal by an analog converter, and the output video signal is For example, the image is output to a display device such as CI'tT and displayed as an image.

Further, the digital converter and the digital processing section.

In order to control the operation of an analog converter, etc., this type of digital video processing device is equipped with a clock pulse generation circuit, which generates clock pulses of various periods shorter than one horizontal scanning period in synchronization with the horizontal synchronization signal of the input video signal. In addition to forming clock pulses, each tarlock pulse is selectively supplied to a digital converter, digital processing section, analog converter, etc.

Incidentally, an analog circuit such as a low-pass filter for removing components due to folding of the signal is provided downstream of the analog converter, and periodic noise derived in synchronization with each of the clock pulses is generated in the analog circuit. Since the periodic noise is easily mixed in, the output video signal output to a display device or the like is mixed with the periodic noise.

When an image is displayed on a display device, since the noise is synchronized with the horizontal synchronization signal, the noise has a strong correlation in the vertical direction on the screen of the display device, and a vertical striped noise pattern appears on the screen. Image quality is significantly impaired.

Therefore, in this type of digital video processing device, general noise reduction processing such as shielding, grounding, decoupling, and two-way separation (isolation) is applied to reduce the output video signal. Efforts are being made to prevent noise from entering.

However, even if the noise reduction processing is performed, noise may be mixed into the output image (Sakae signal).

On the other hand, if the noise mixed in the output video signal is extracted by some method and the extracted noise signal is subtracted from the output video signal, it becomes possible to remove the noise from the output video signal through so-called noise compensation processing. For example, by using noise reduction processing and noise compensation processing together, periodic noise mixed into the output video signal can be almost completely removed.

The mixed noise is a periodic signal synchronized with the horizontal synchronization signal, and also occurs when there is no input video signal.
As described in the publication, the output signal of the digital video processing device when there is no input video signal is regarded as a periodic noise signal and stored, and when there is an input video signal, it is stored and stored from the output video signal. It is conceivable to subtract the stored signal and remove periodic noise from the output video signal.

[Problem that the invention seeks to solve]

Incidentally, the shape of the entire digital video processing device changes from moment to moment, and the state of periodic noise mixed into the output video signal also changes with this change.

Therefore, even if the output signal of the video processing device when there is no input video signal is treated as a periodic noise signal and noise compensation processing is performed as described above, periodic noise cannot be accurately removed from the output video signal. There are problems that cannot be removed.

[Means for solving problems]

This invention was made with the above points in mind,
Vertical blanking of the output video signal in a digital video processing device that converts an analog input video signal into a digital signal and digitally processes the digital signal, and converts the digitally processed digital signal into an analog output video signal. It has a function of comparing the absolute value of the level of the no-signal horizontal video signal portion within the period with the set upper limit of the normal level, and the level is inverted at every leading edge of the vertical blanking period of the output video signal. memory selection signal forming means for forming a memory selection signal and re-inverting the level of the memory selection signal at the trailing edge of the vertical blanking period only when the absolute value exceeds the upper limit value; write control means having a write selection switch for selectively selecting two memories based on the level of the output signal, and storing the output video signal of the no-signal horizontal video signal portion in the memory selected by the switch; and a read selection switch that selectively selects both of the memories in conjunction with the write selection switch based on the level of the memory selection signal.

readout control means for outputting a readout signal for a period substantially other than the vertical blanking of the memory selected by the switch; and subtraction means for subtracting the readout signal of the readout processing means from the output video signal and outputting the result. This is a digital video processing device characterized by:

[For production]

By the way, in the output video signal during the vertical blanking period, there is only a synchronization pulse component and no video signal component, so the output video signal in the no-signal horizontal video signal portion within the vertical blanking period is only mixed noise. becomes the signal.

On the other hand, large amplitude (large Be/L/) noise is suddenly mixed into the input video signal depending on the reception and reproduction conditions.

The level of the memory selection signal output from the memory selection signal forming means is inverted at each leading edge of the vertical blanking period, and the absolute value of the level of the no-signal horizontal video signal portion within the vertical blanking period is normal. When the upper limit of the level is exceeded, that is, when a sudden large-amplitude noise mixes into a portion of the horizontal video signal with no signal, the level is re-inverted at the trailing edge of the vertical blanking period, and the memory selection signal memories are selectively selected, the output video signal of the no-signal horizontal video signal portion is stored in the selected memory, and the stored signal of the selected memory is stored for a period substantially other than the vertical blanking period. Normally, periodic noise is stored alternately in both memories during each vertical blanking period, and the read signals of both memories are alternately stored in the subtraction means during periods other than the vertical blanking period. When a sudden large-amplitude noise mixes in, the subtraction means uses the readout signal of the memory that stores the noise just before the large-amplitude noise is mixed in, instead of the memory that stores the large-amplitude noise along with the periodic noise. is output to.

Then, the subtracting means subtracts the readout signal from the output video signal, so periodic noise is removed from the output video signal without being affected by sudden large-amplitude noise.

〔Example〕

Next, the present invention will be explained in detail with reference to FIGS. 1 to 4 showing one embodiment thereof.

Figure 1 shows a digital video (I) that digitally processes an analog input video signal consisting of an NTSC television signal.
I processing device is shown in the figure, (υ is a video input terminal into which an analog input video signal is input, (2) is a digital converter for video signals connected to the input terminal (1), (3)
) is the digital processing unit connected to the converter (2), (4)
is an analog converter for video signals connected to the processing unit (3), (5) is a low-pass filter for video signals connected to the converter (4), and (6) is a subtraction circuit forming subtraction means; The positive input terminal (+) is connected to the filter (5), and (8) is a clock generation circuit connected to the converter (2), which generates various clock pulses to be described later for operation control. The pulse is converted into a converter (2), a processing section (3), a converter (
4) Selectively output to other sources. (9) Fill (5)
and the negative input terminal of the subtraction circuit (6), (1G is a comparison circuit connected to the filter (5) and forms a memory selection signal forming means, and is indicated by a broken line. A memory selection signal, which will be described later, is output to the storage circuit (9).

In the memory circuit (9), (9a) is a noise digital converter connected to the filter (5), (91 is an averaging converter whose one input terminal is connected to the converter (9a)) The adder circuit (9C) is a write selection switch whose switching piece is connected to the adder circuit (9b), and depending on the level of the memory selection signal of the comparator circuit 00, one contact (a) and the other contact (b) It can be selectively switched to.

(9d), (9(+)) are the first .
It is a second line memory, and the input terminal of the memory (9d) is connected to the contact (a) of the switch (9C),
The input terminal of the memory (9e) is connected to the contact of the switch (9C) (
b), each with l horizontal scanning period, i.e. 1
Memorize line signals.

(9f) is a read selection switch with two contacts <af and <bf, one contact (ar is the memory (9d)
The other contact (bf) is connected to the output terminal of the memory (9e), the switching piece is connected to the other input terminal of the adding circuit (9b), and the comparing circuit ( Depending on the level of the IG memory selection signal,
In conjunction with the switch (9C), the contact is selectively switched between the contact <af and the contact (bf).

(9g) is the noise analog converter connected to the switching piece of the switch (9f), and (9h) is the noise analog converter connected between the converter (9g) and the negative input terminal of the subtraction circuit (6). It is a low-pass filter for

Note that a control circuit such as a microcomputer that controls the operation of the entire device is not shown.
(9B), addition circuit (9b), switch (9C)
and the memory control means form the write control means, and the switch (9f) and the conversion u (9gC
.

A read control means is formed by the filter (9h) and the memory control means.

Then, an analog input video signal obtained by reception, reproduction, etc. is inputted from an input terminal (1) to a converter (2), and the input video signal is converted into a digital signal by the converter (2).

Further, the digital signal of the converter (2) is input to the processing unit (3) and the generation circuit (8), and the generation circuit (8) generates various clock pulses for operation control in synchronization with the horizontal synchronization signal of the input video signal. is formed and each clock pulse is converted # (23, (4) and processing unit (3)
.

The signal is selectively output to the memory circuit (9), the comparison circuit αq, etc., and each circuit in the device operates in synchronization with the input video signal.

Furthermore, the processing section (3) performs various digital calculation processes on the digital signal of the converter (2) based on various input clock pulses, and performs digital processing on the digital signal of the converter (2). Ru.

Then, the digitally processed digital signal is output from the processing unit (3) to the converter (4), and the input digital signal is converted into analog by the converter (4), and then filtered from the converter (4). Subtraction circuit (6) via (5)
An analog output video signal is output to a storage circuit (9) and a comparison circuit αQ.

Note that the filter (5) is provided to remove harmonics and components above the video signal band included in the output signal of the converter (4), for example, harmonic components generated by signal folding. (5) outputs only signals within the video signal band.

By the way, various periodic noises synchronized with each clock pulse are generated by the generation of each clock pulse, and the periodic noise within the video signal band is mixed into the output video signal output from the filter (5).

Also, for example, the input video signal may be a video disc.

In the case of a signal obtained by reproducing a video chip, large-amplitude noise is suddenly mixed into the input video signal due to dropout or the like, and the large-amplitude noise is also mixed into the output video signal output from the filter (5).

On the other hand, in the case of an NTSO television signal, as shown in FIG.
Only the synchronizing pulse components of the horizontal synchronizing pulse and horizontal synchronizing pulse are present, and the horizontal synchronizing pulse component and the video signal component are present in each effective scanning period Tb of one field following the vertical blanking period Ta.

In Fig. 2, Fo and Fe indicate odd and even fields, respectively, Tx within the period Ta indicates an equivalent pulse and an equivalent pulse period in which a vertical synchronization pulse exists, and Tar indicates a period in which a horizontal synchronization pulse exists. Indicates the horizontal sync pulse period.

As is clear from FIG. 2, each horizontal scanning period of the period Ty, that is, each line, is a signalless horizontal video signal portion that has no video signal component and is hardly affected by the synchronization pulse component. It will be a period of

Therefore, the output video signal for each fin in period Ty is:
The signal consists only of mixed noise.

Therefore, the storage circuit (9) rewrites and stores the noise mixed in the output video signal of each one field based on the storage of the output video signal of the period Ty by the operation described below, and stores the noise mixed in the output video signal of each one field. At the same time as extracting the noise, the noise signal of each extracted field is
The signal is read out to the subtraction circuit (6) in synchronization with the output video signal during the period Tb of each one field.

Basically, it is possible to extract periodic noise by storing only the output video signal of one line of period Ty, but the condition of the mixed noise changes for each line and , since random noise and the like are present in the output video signal, the storage circuit (9) averages and stores the output video signal of each line in the period Ty.

By the way, the noise extracted during the period Ty is normally only periodic noise derived from each tallock pulse, but when sudden large amplitude noise is mixed into the input video signal during the period Ty, periodic noise and sudden noise are extracted. This results in large-amplitude noise.

Since sudden large-amplitude noise cannot be suppressed even by averaging processing, the head of the comparison circuit stores the signal stored in the field immediately before the field in which the sudden noise is stored. (9) to prevent the influence of sudden noise.

That is, the comparator circuit αO calculates the period Ty of each field.
It has a comparison function that compares the absolute value of the level of the output video signal with a preset upper limit of the normal level, and
It has a function of forming a memory selection signal whose level is inverted at each leading edge of the period Ta, and when the absolute value of the level of the output video signal during the period Ty does not exceed the upper limit, that is, no sudden large amplitude noise is mixed in. At this time, as shown in FIG. 3(a), a memory selection signal that alternately changes between high level and low level for each field is output to the storage circuit (9).

In addition, FIG. 3(a) (7) Fn-+, Fn,
Fn++, Fn+2, Fn+a are N-1, N
, N+1. N+2. Indicates the N+3rd field.

On the other hand, when the absolute value of the level of the output video signal in the period Ty exceeds the upper limit due to sudden large-amplitude noise, the re-inversion control function of the comparator circuit QG causes the level of the memory selection signal to change at the trailing edge of the period Ta. Re-inversion control is performed.

For example, as shown in FIG. 4(a), if there is a sudden large-amplitude noise in the output video signal at the position tn during the period Ty of the Nth field, then the period T of the Nth field
At the trailing edge of a, the level of the memory selection signal is controlled to be inverted again.

Then, depending on the level of the memory selection signal, a switch (9c
(9f> is switched in conjunction with the memory (9d)
, (90) is alternatively selected, and the selected memo 1.1 (9d) or (9C) is written and read.

)−? -A f Memo II (Qd) (qQ) I+,
The write signal output from the stage Tn'J -E: l al ml -F'', that is, the write signals shown in FIGS. 3(b) and 4(b) causes the signal to go to high level. Writing and reading are controlled during the period TyK of the field, and reading is controlled during a period Tc, which is approximately outside the period Ta, from the trailing edge of the period Ty until the next rise of the write signal.

Now, due to the high level of the memory selection signal, the switches (98) and (9r) are switched to the contacts (a) and (a)' to select the memo IJ (9d), and the memory selection signal LowRepe/IIcJ: Line-f-(9c)
, (9f) If the memory (9e) is selected by replacing the contact (b), (b)'K'a, there will be no sudden large amplitude noise and the level of the memory selection signal will be as shown in Figure 3 (
If it changes for each field as shown in a), for example, the Nth field Fτl has a line f (
90) and (9r) switch to contacts (n) and (a)' to select memory (9d), and switch (9C) and (9f) switch to contact (+3) for the N+1st field Fn+. , (b)', the memory (9C) is selected, and the memories (9d) and (90) are alternately selected for each field.

The selected memory is controlled for writing and reading during the period Ty, and for reading during the period Tc, based on the write signal described above.

Furthermore, the l field in which the memory (9d) is selected.

For example, the Nth field Fn has a switch (9
0) and (9r) are switched to contacts (a) and (a)', the addition circuit (9
One line of the signal output from b) is written to the memory (9d), and one line of the stored signal of the memory (9d) is output to the adder circuit (9b), and the adder circuit (9b)
The output video signal of each line of the period Ty is subjected to averaging processing, and the output of the signal of one line from which random noise etc. have been removed by the averaging processing, that is, the horizontal video signal portion with no signal within the vertical blanking period. The video signal is written to the memory (9d), and the noise of the l line mixed in the output video signal of the Nth field Fn, that is, the periodic noise derived from each clock pulse, is extracted to the memory (9d). are stored digitally.

Further, when the period Ty of the Nth field Fn ends, the memory (9d) is controlled to read, and during the period Tc of the field Fn, the memory (9d) is controlled to read in synchronization with the output video signal. , one line of storage signal in the memory (9d) is synchronized with the output video signal and repeats in the converter (
9g).

Similarly, 1 field in which memory (9e) is selected.

For example, in the N+1st field Fn+r, switches (9C) and (9f) have contacts (b) and (b)'
Therefore, during the period Ty of the field Fn++, the periodic noise mixed in the output video signal of the field Fn++ is extracted and digitally stored in the memory (9e), and during the period Tc, the periodic noise mixed in the output video signal of the field Fn++ is extracted and digitally stored in the memory (9e). One line of the storage signal stored in 9a) is repeatedly read out to the converter (9g) in synchronization with the output video signal.

Then, the converter (9g) converts the memory (9d), (90
) is converted into an analog signal, and
The analog signal of the converter (9g) is output to the subtraction circuit (6) via the filter (9h), and the subtraction circuit (6) receives the output video signal of each field of the filter (5) and the memory (9d). or the readout signal of the memory circuit (9) consisting of the memory signal of (9e), that is, the memory (9d) or (9e);
The periodic noise signal of each field stored in 9e) is input.

Note that the filter (9h) is similar to the filter (5),
It is provided to remove harmonic components above the video signal band.

Then, the subtraction circuit (6) subtracts the readout signal of the storage circuit (9) from the output video signal of the filter (5), and at this time, the readout signal is extracted during the vertical blanking period of each field of the output video signal. Since the periodic noise signal is stored as a periodic noise signal, the periodic noise is accurately removed from the output video signal, and the signal is output from the subtraction circuit (6) to a display device, etc. via the output terminal (7). The output video signal is almost completely free of periodic noise.

In other words, if there is no sudden large-amplitude noise and only periodic noise derived from each clock pulse exists during each field Ty of the output video signal, the memory (
9d), (9() are used alternately for each field to extract the periodic noise of each field into the period Ty of each field, and the period of each period extracted into the period Tc of each field. To accurately remove periodic noise mixed into an output video signal by subtracting periodic noise from the output video signal.

Next, for example, the period Ty of the Nth field Fn
If a sudden large-amplitude noise occurs and the level of the memory selection signal is inverted again at the trailing edge of the period Ta of one field Fn as shown in FIG. During period Ty, memo IJ (9d
) is stored in the output video signal during the period Ty of the relevant l field Fn, and at this time, the large amplitude noise is stored in the adder circuit (
Since the noise is not suppressed by the averaging process in 9b), the noise stored in the memory (9d) becomes periodic noise and large amplitude noise.

Then, in the period Tc of the Nth 1 field Fn, memo 1
, 1 (9d) is input to the subtraction circuit (6), noise in the output video signal after subtraction increases due to the influence of large amplitude noise.

When a sudden large-amplitude noise occurs, the level of the memory selection signal is inverted again at the trailing edge of the period Ta, and the selected memory is changed to the field where the sudden noise occurred, that is, the Nth field. It is switched to the memory (9C) that stores the periodic noise of the N-1th field Fn-1 immediately before Fn, and the N-th field F
During period Tc of n, the signal stored in the memory (9C), that is, the periodic noise signal of the N-1st one field Fn-+ is read out from the storage circuit (9) to the subtraction circuit (6).

Therefore, the subtraction circuit (6) converts the output video signal of the N-1st field Fn from the output video signal of the Nth field Fn mixed with periodic noise and sudden large-amplitude noise.
By subtracting the periodic noise signal extracted from n−t, the periodic noise can be accurately removed even from the output video signal mixed with sudden large-amplitude noise.

Note that since the re-inverted memory selection signal is inverted at the leading edge of the period Ta of the next N1001-th 1-field Fn++, the memory (9d) is selected for the N+1-th 1-field Fn++, and the memory (9d) is selected for the N+1st 1-field Fn++. The periodic noise extracted during the period Ty of one field Fn+r is stored in the memory (9d).

Therefore, the output video signal output from the output terminal (7) to a display device, etc. is always free from periodic noise derived from each clock pulse, regardless of the presence or absence of sudden large-amplitude noise. For example, vertical striped noise patterns based on periodic noise can be removed from the screen of a display device, thereby improving image quality.

In the above embodiment, the memo IJ (9d), (9e) stores one line's worth of signals subjected to averaging processing, but it is also possible to store one line's worth of signals of period Ty without performing averaging processing. You may.

Furthermore, although the above embodiment was applied to digitally processing NT80 television signals, it is of course applicable to digitally processing various analog video signals such as high-definition television broadcasting signals. be.

〔Effect of the invention〕

As described above, according to the digital video processing device of the present invention, two memories are selectively selected by the memory selection signal outputted from the memory selection signal forming means, and the vertical control of the output video signal is performed by the write control means. The horizontal video signal portion with no signal within the blanking period is stored in the selected memory, and the readout control means synchronizes the stored signal in the selected memory with the output video signal during the period other than the vertical blanking period. By causing the subtracting means to read out the signal and subtracting the readout signal from the readout control means from the output video signal by the subtraction means, it is possible to always accurately remove periodic noise mixed into the output video signal. be.

[Brief explanation of drawings]

The drawings show one embodiment of the digital video processing device of the present invention, and FIG. 1 is a block diagram, FIG. 2 is a waveform diagram of the vertical blanking portion of an NTSC video signal, and FIG. 3(a)
, (t)) is a timing chart for explaining the operation when sudden large amplitude noise does not occur, Fig. 4 (a)
, (b) is a timing chart for explaining the operation when sudden large amplitude noise occurs. (1)...Video input terminal, (2)...Video signal digital converter, (3)...Digital processing unit, (4)...
...Video signal analog converter, (6)...Subtraction circuit, (7)...Video output terminal, (9)...Storage circuit,
(9C)...Write selection switch, (9d). (9e)...1st. 2nd line memory, (9f)...
・Reading selection switch, (1G... comparison circuit.

Claims (1)

[Claims] (1) In a digital video processing device that converts an analog input video signal into a digital signal and performs digital processing, and converts the digital signal subjected to the digital processing into an analog output video signal, the output video signal is It has a function to compare the absolute value of the level of the no-signal horizontal video signal portion within the vertical blanking period with the set upper limit of the normal level, and the level is calculated at each leading edge of the vertical blanking period of the output video signal. a memory selection signal forming means for forming a memory selection signal that is inverted, and controlling the level of the memory selection signal to be re-inverted at the trailing edge of the vertical blanking period only when the absolute value exceeds the upper limit value;
It has a write selection switch that selectively selects two memories based on the level of the memory selection signal, and the output video signal of the no-signal horizontal video signal portion is sent to the memory selected by the switch. It has a write control means for storing data, and a read selection switch that selectively selects both of the memories in conjunction with the write selection switch based on the level of the memory selection signal, and the read selection switch selectively selects the memory selected by the switch. A digital device characterized by comprising: readout control means for outputting a readout signal for a period substantially other than the vertical blanking; and subtraction means for subtracting the readout signal of the readout processing means from the output video signal and outputting the result. Video processing device.