JPS63214089A - Digital drop out compensating circuit - Google Patents

Abstract

PURPOSE:To compensate the drop out of a video signal including a chroma signal by shifting in dot the output of a delay circuit, and supplying to a switching circuit at the time of switching the output of the digital delay circuit and an input digital video signal. CONSTITUTION:A reproduced signal transformed to an electric signal by an optical pickup 1 is supplied to an FM demodulation circuit 2, A/D converted and supplied to a digital delay line 11. The output of the delay line 11 is stored in a 1H line memory 13 through a signal switching circuit 12. Under such a state, when the drop out is detected in a drop out detector 5, the signal switching circuit 12 is switched according to the output and switched and selected to the output of a dot shift circuit 17 from the output of the digital output line 11. The video signal before 1H is constantly outputted from the dot shift circuit 17 and the delay of two clocks is executed, so that the drop out including the chroma signal can be compensated.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Industrial Application The present invention relates to a digital dropout compensation circuit used for compensating dropout of a playback signal in an optical video disc playback device.

(2) Conventional technology Conventionally, in optical video disc playback devices,
A dropout compensation circuit was used, and was generally configured as shown in FIG.

In FIG. 3, the reproduced signal converted into an electrical signal by the optical pickup 1 is supplied to the FM demodulation circuit 2, where the FM
demodulated. The video signal obtained by being demodulated by the FM demodulation circuit 2 is delayed by the delay line 3 and then supplied to the signal switching circuit 4. The delay time of the delay line 3 is determined by the dropout detection circuit 5 and the signal switching circuit 4.
It is set according to the time required for the detection switching operation in . The video signal that has passed through the signal switching circuit 4 is outputted from the output terminal 9 as it is when there is no dropout and is supplied to the next stage time axis correction circuit (not shown).

The output video signal via the signal switching circuit 4 is output to the output terminal 9.
At the same time, it is returned to the signal switching circuit 4 via the low-pass filter 8, IH delay line 7, and low-pass filter 6. The low-pass filter 8 is used to remove the chroma signal included in the video signal, and the low-pass filter 6 is used to remove the clock signal of the IH delay line 7, which appears at the output of the IH delay line 7. It is used in The IH delay line 7 is composed of a CCD or the like, and delays the video signal as an analog signal.

The occurrence of dropout is detected by the dropout detection circuit 5. Dropout detection circuit 5
detects a dropout due to a lack of a carrier signal included in the output of the optical pickup l. When a dropout is detected by the dropout detection circuit 5, the signal switching circuit 4 is switched based on its output, and the output of the delay line 3 is switched to the output of the low-pass filter 6, which is output from the output terminal 9. The low pass filter 6 is
Since the video signal before IH is always output, the video signal of 1 horizontal jump where dropout occurred is output from the previous 1
Dropout compensation is performed by substituting the video signal of the horizontal opening phase leap.

(3) Problems to be Solved by the Invention In the dropout compensation circuit shown in FIG. 3, since the chroma signal is removed by the low-pass filter 8, the dropout compensation circuit is only implemented for the luminance signal. . The reason why the chroma signal is removed by the low-pass filter 8 is that in the NTSC video signal, the phase of the chroma signal is inverted for each IH. This is due to the fact that it cannot be replaced with a signal.

For this reason, when a signal that has undergone dropout compensation using the dropout compensation circuit shown in Figure 3 is viewed on a modern high-resolution TV monitor, the lines displayed in monochrome become noticeable and the screen becomes very unsightly. There were drawbacks.

(4) Means for solving the problems The present invention has been made in view of the above points, and aims to compensate for dropouts of video signals including chroma signals.
To achieve this purpose, the input digital video signal is
A digital delay circuit that delays by a horizontal opening period or more, a switching circuit that switches between the output of the digital delay circuit and an input digital video signal, and a dot shift circuit that dot-shifts the output of the digital delay circuit and then supplies it to the switching circuit are provided. It is composed of

(5) Effect In this configuration, the dot shift circuit dot-shifts the output of the digital delay circuit and supplies it to the switching circuit, and the dot-shift circuit delays the chroma signal included in the output of the digital delay circuit by an extra half period before supplying it to the switching circuit. By doing so, it acts to match the phase of the chroma signal included in the input digital video signal with the phase of the chroma signal that is one horizontal synchronization period or more earlier.

(6) Examples Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital dropout compensation circuit according to the present invention.

In FIG. 1, a reproduced signal converted into an electrical signal by an optical pickup 1 is supplied to an FM demodulation circuit 2, where an FM
demodulated. The steps up to this point are the same as the conventional dropout compensation circuit shown in FIG. The video signal obtained by being demodulated by the FM demodulation circuit 2 is sent to the A/D conversion circuit l.
The signal is converted into a digital signal at O, and then supplied to the digital delay line 11. In the delay line 3, a delay is performed in accordance with the time required for detection and switching operations in the dropout detection circuit 5 and the signal switching circuit 12, and then the signal is supplied to the signal switching circuit 12. The digital video signal that has passed through the signal switching circuit 12 is supplied to the IH memory circuit 13, where it is delayed by one horizontal synchronization period, and when there is no dropout and is normal, it is output as is from the output terminal 14, and the shaft is closed at the next stage. The signal is supplied to a correction circuit (not shown).

The digital video signal delayed by the IH memory circuit 13 is output from the output terminal 14 and is also returned to the signal switching circuit 12 via the dot shift circuit 17. The dot shift circuit 17 is constituted by a D-type flip-flop or the like, and performs dot shift according to a clock signal ck, which will be described later, thereby delaying the video signal as a digital signal by two clocks of the clock signal ck.

The occurrence of dropout is detected by the dropout detection circuit 5 as in the conventional case.

The dropout detection circuit 5 detects a dropout based on the lack of a carrier signal included in the output of the optical pickup 1. When a dropout is detected by the dropout detection circuit 5, the signal switching circuit 12 is switched based on its output, and the output of the digital delay line 11 is switched to the output of the dot shift circuit 17. The dot shift circuit 17 always outputs the video signal before IH, and is delayed by two clocks of the clock signal ck. 1 just before an out occurs
Dropout compensation is performed by replacing the video signal with a video signal during the horizontal opening period.

The clock signal ck is generated by the PLL circuit 16 at a horizontal synchronization frequency fH of 91, based on the synchronization signal separated by the synchronization separation circuit 15 from the video signal FM demodulated by the FM demodulation circuit 2.
0 times, thus 4 times the color subcarrier frequency (approximately 14.3MH
2) is produced as a frequency signal. This clock signal ck is used as a time reference for A/D conversion.
The signal is supplied to the conversion circuit 10 and then supplied to the IH memory circuit 13 as a time reference for recording and reading. Furthermore, the chroma signal included in the digital video signal output from the digital delay line 11 is divided into half periods (that is, 2 times the frequency of the clock signal ck, which is four times the color subcarrier frequency).
Dot shift circuit 1
7 is also supplied.

Next, the operation will be explained with reference to FIG.

Although the output of the digital delay line 11 is a digital signal, it is shown as an analog signal A in FIG. 2(a) for ease of understanding. Note that signal A and signal B, which will be described later,
C and E show only the chroma signal and omit the luminance signal in order to show the characteristic parts of the present invention.

When the chroma signal included in the output of the digital delay line 11 is the signal A shown in FIG. 2(a), the output of the IH memory circuit 13 is equal to the signal A before IH, so it is shown in FIG. 2(b). As shown, signal B is obtained by inverting signal A. In a normal state without dropout, this signal B is output from the output terminal 14.

The signal B is supplied to the dot shift circuit 17, where it is dot shifted by two clocks of the clock signal ck and output, so the output of the dot shift circuit 17 is as shown in FIG.
280nsec to the signal like signal C shown in C)
The signal is delayed by (140 nsec×2, that is, twice the period of the clock signal ck). Since this signal C has the same phase as the signal A which is the output of the digital delay line 11, the signal switching circuit 12 can switch and output the signal C instead of the signal. In this way, the dot shift circuit 17 delays the chroma signal included in the output of the lH memory circuit 13 by half a cycle and then supplies it to the switching circuit 12, thereby changing the chroma signal included in the output of the digital delay line 11 to the digital video signal. By matching the phase of the included chroma signal with the phase of the chroma signal one horizontal synchronization period before, the chroma signal can also be replaced with the signal one horizontal synchronization period before.

Even if the video signal output from the optical pickup l contains jitter and the chroma signal component output from the digital delay line 11 has a long wavelength as shown in FIG. Circuit 15 and PLL circuit 1
6, the clock signal ck is created based on a signal containing the same jitter, so the data values stored in the IH memory circuit 13 and dot shift circuit 17 are not affected by jitter. That is, the levels of points PI, P2, P3, . . . of the signal A shown in FIG.
2.3..., if the signal E is stored and read out as shown in FIG. 3(d), the signal E, which has a longer wavelength as shown in FIG. 2(e), is read out in the same way. Point P1
, P2, P3... are set to addresses l, 2.3... of the IH memory circuit 13 and dot shift circuit 17,
Memory extraction is performed as shown in FIG. 3(d). This is because the reference clock signal ck also contains the same jitter.

Although the present invention has been described above with reference to the embodiments, various modifications are possible according to the technical idea of the present invention. for example,
The IH memory circuit 13 is normally used to provide a delay of 1H, but it can also be configured to provide a delay of 3H or 5H, which is greater than IH.

Also, as a reference signal for creating the clock signal ck,
In addition to the synchronization signal described in the above embodiment, a color burst signal or the like may also be used.

(7) Effects of the Invention As explained above, the present invention provides a digital delay circuit that delays an input digital video signal by one horizontal synchronization period or more;
It is configured to include a switching circuit that switches between the output of the digital delay circuit and an input digital video signal, and a dot shift circuit that dot-shifts the output of the digital delay circuit and then supplies the output to the switching circuit.

With this configuration, the dot shift circuit dot shifts the output of the digital delay circuit and then supplies it to the switching circuit.
By delaying the chroma signal included in the output of the digital delay circuit by half a period and then supplying it to the switching circuit,
The phase and 1 of the chroma signal included in the input digital video signal
Since it acts to match the phase of the chroma signal before the horizontal synchronization period, it is possible to perform dropout compensation for the video signal including the chroma signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the digital dropout compensation circuit according to the present invention, FIG. 2 is a waveform diagram explaining the operation of the circuit shown in FIG. 1, and FIG. FIG. 2 is a block diagram showing a compensation circuit. 5... Dropout detection circuit 10... A/D conversion circuit 12... Signal switching circuit 13... IH memory circuit 15... Same gate separation circuit 16... PLL circuit 17... Dot shift circuit Patent Applicant NEC Home Electronics Co., Ltd. Agent Patent Attorney Yama 1) Takeki Figure 3

Claims (1)

[Claims] a digital delay circuit that delays an input digital video signal by one horizontal synchronization period or more; a switching circuit that switches between the output of the digital delay circuit and the input digital video signal; and a switching circuit that dot-shifts the output of the digital delay circuit and then shifts the output of the digital delay circuit. a digital dropout compensation circuit having a dot shift circuit that supplies