JPH0576048A - Drop-out compensation system for video signal - Google Patents

Abstract

PURPOSE:To provide a circuit which enables the drop-out compensation of plural lines, and the compensation of one field. CONSTITUTION:This system is equipped with a line memory 1a which stores and reads out a video signal, sub-carrier inversion circuit 6 which inverts the phase of a color sub-carrier in the video signal from the detected result of the odd/even lines of the pertinent stored video signal, drop-out detecting circuit 3 which detects the deterioration and disturbance of the synchronizing level of the video signal, and inhibits the writing of the line memory 1a from the detected result, and switch 8 which switches the input video signal to the read video signal at the time of detecting the omission of the video signal by the drop-out detecting circuit 3. Thus, the interpolation of the video signal can be operated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dropout compensation system for compensating for signal loss of a video signal. With the recent demand for improvement in the image quality of the image reproducing apparatus and the image processing apparatus, it is required to reduce the noise in the image caused by the loss of the image signal.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a horizontal waveform of a color video signal. NTSC signals for color television are Y and C signals.
It is a video signal formed by signals. The Y signal has a horizontal synchronizing signal and a luminance signal for each line. Further, the C signal has a color synchronization signal (color burst) and a color subcarrier (color subcarrier). When the Y signal and the C signal are individually treated as independent video signals, they are called Y / C separation signals, and when they are treated as a video signal that combines these Y signals and C signals, they are called Y / C composite signals. ..

Conventionally, in order to compensate for the dropout of one line of the Y / C separated signal, the input Y / C separated signal is stored using a line memory having a capacity of one line. Then, when reading out, the color burst in the C signal is uniquely set in the dropout compensation circuit so that the phase difference between the odd line and the even line becomes 180 degrees, and the color burst having the phase difference of 180 degrees is converted into the video signal. It is realized by replacing with color burst.

[0004]

Therefore, in the conventional circuit system, the color burst generated in the dropout compensation circuit needs to be synchronized with the video signal, and the circuit is small because it is an analog circuit. However, there is a problem in that it is not easy to make it easy and is easily affected by external noise, and it is not possible to expect an effect for dropout of a plurality of lines.

An object of the present invention is to provide a circuit which enables dropout compensation of a plurality of lines and compensation of up to one field.

[0006]

In order to achieve the above object, the present invention uses a timing signal generated by a sync separation circuit 2, a PLL circuit 4 and a timing generator 5 to restore a video signal. By the line memory 1a for reading out after storing the video signal and the detection result of the odd / even lines of the stored video signal,
A subcarrier inversion circuit 6 for inverting the phase of a color subcarrier in a video signal, and a dropout for detecting a drop or disturbance of the sync level of the video signal and for inhibiting writing to the line memory 1a according to the detection result. The detection circuit 3 and the switch 8 for switching the input video signal to the read video signal when the dropout detection circuit 3 detects the lack of the video signal are provided to interpolate the video signal.

A / D for digitizing the video signal
A D conversion circuit 9 and a field memory 1b for storing one field of a video signal output from the A / D conversion circuit 9,
A D / A conversion circuit 10 for inversely converting the read data of the field memory 1b into an analog video signal, a drop and a disturbance of the sync level of the video signal are detected, and the line memory 1a is written according to the detection result. A dropout detection circuit 3 for prohibiting and a switch 8 for switching an input video signal to a read video signal when the dropout detection circuit 3 detects a loss of the video signal are provided to interpolate the video signal. To do.

[0008]

According to the present invention, in the configuration shown in FIG. 1, the video signal is stored in the line memory 1a, and the subcarrier inverting circuit 6 detects the color of the video signal based on the detection result of the odd / even lines of the stored video signal. The phase of the subcarrier is inverted and read, and when the dropout detection circuit 3 detects a drop in the synchronization level of the video signal and disturbance, the writing of the line memory 1a is prohibited.

Therefore, the video signal can be interpolated by switching the video signal input by the switch 8 to the read video signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the embodiments shown in FIGS. In FIG. 1, 1a is a line memory, 2
Is a sync separation circuit, 3 is a dropout detection circuit, 4 is a phase locked loop circuit (hereinafter referred to as PLL circuit), 5
Is a timing generator, and 6 is a subcarrier inverting circuit. Reference numeral 7 is an inverter and 8 is a switch.

In FIG. 1, a line memory 1a temporarily stores one line of an input Y / C separation signal for each dot and then reads and restores it. The color burst in the restored Y / C separation signal is based on the carrier inversion signal sent by the timing generator 5 as a detection result as to whether it is an odd line / even line of the video signal, and an even number in the sub carrier inversion circuit 6. The polarity of the phase difference between the line and the odd line is inverted by 180 degrees and output to the switch 8. In addition, writing (WE) and reading (OE) of the line memory 1a
The timings of the dot clock and the dot clock are generated by a logical operation in the timing generator 5.

The sync separation circuit 2 extracts the horizontal sync signal from the input Y / C separation signal, and the PLL circuit 4 generates a timing clock from the horizontal sync signal to synchronize the timing generator 5 internally. Then, the dropout detection circuit 3 detects a decrease or disturbance of the synchronization level, prohibits writing of the Y / C separation signal to the line memory 1a, and adds the detection result of the dropout detection circuit 3 to the timing generator 5. The carrier inversion signal is sent, the compensated restored Y / C separation signal from the subcarrier inversion circuit 6 and the input Y / C separation signal are added to the switch 8, and the output of the dropout detection circuit 3 is inverted by the inverter 7. The video signal is interpolated by applying a selection signal to the switch 8 to switch the video signal, and a required corrected Y / C separation signal is generated.

FIG. 2 shows an A / D conversion circuit for converting an analog signal into a digital signal by using a field memory 1b for storing a Y / C separation signal input for one field instead of the line memory 1a in FIG. 9 and a D / A conversion circuit 10 for inversely converting a digital signal into an analog signal and an AND gate 11 for outputting a write clock.

In FIG. 2, circuits 2, 3, 4, 5 and 8 have the same operation as in FIG. The A / D conversion circuit 9 digitally converts the analog input Y / C separation signal and temporarily stores it in the field memory 1b.
D / A conversion circuit for digital data read from 1b
At 10, an analog reconstructed Y / C separation signal is generated.

Timing signals of the memory address of the field memory 1b, the A / D clock of the A / D conversion circuit 9 and the D / A clock of the D / A conversion circuit 10 are generated in the timing generator 5. Writing to the field memory 1b is performed by the write clock output from the AND gate 11 when the dropout detection circuit 3 is invalid.

The sync separation circuit 2 detects the horizontal sync signal in the input Y / C separated signal, and the PLL circuit 4 generates a timing clock from the horizontal sync signal to synchronize the timing generator 5 internally. Further, the dropout detection circuit 3 detects a drop or disturbance of the synchronization level, adds it to the inverter 12, and inputs it as a restored Y / C separation signal.
The / C separation signal is switched by the selection signal from the inverter 12 to interpolate the video signal to generate a required Y / C separation signal.

When the dropout detection circuit 3 detects the dropout and becomes valid, the AND gate 11 stops sending the write clock and stops writing the Y / C separation signal to the field memory 1b. ..

[0018]

As is apparent from the above description, according to the present invention, it is possible to configure the dropout circuit portion with a digital circuit, which makes it possible to reduce the circuit scale and make it less susceptible to external noise. In addition, it is effective for dropout of a plurality of lines and has an effect of enabling correction up to one field.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a circuit configuration of the present invention.

FIG. 2 is a diagram showing another embodiment of the circuit configuration of the present invention.

FIG. 3 is a diagram showing a horizontal waveform of a color video signal.

[Explanation of symbols]

1a is a line memory 1b is a field memory 2 is a sync separation circuit 3 is a dropout detection circuit 4 is a PLL circuit 5 is a timing generator 6 is a subcarrier inversion circuit 7 is an inverter 8 is a switch 9 is an A / D conversion circuit 10 is D / A conversion circuit 11 is an AND gate

Claims (2)

[Claims] 1. A video signal is restored by a timing signal and the like generated in a sync separation circuit (2), a PLL circuit (4) and a timing generator (5), and the video signal is stored and then read out. Line memory (1a)
A subcarrier inversion circuit (6) for inverting the phase of color subcarriers in the video signal according to the stored detection result of the odd / even lines of the video signal, and reducing and disturbing the synchronization level of the video signal. Detect and
A dropout detection circuit (3) that prohibits writing to the line memory (1a) according to the detection result, and an image that reads the input video signal when the dropout detection circuit (3) detects the loss of the video signal. A video signal dropout compensation method characterized by interpolating the video signal by providing a switch (8) for switching to the signal. 2. A video signal is restored by a timing signal generated by a sync separation circuit (2), a PLL circuit (4) and a timing generator (5), and an A / D circuit for digitizing the video signal. D conversion circuit (9)
And a field memory (1b) for storing one field of the video signal output from the A / D conversion circuit (9), and a digital video signal read from the field memory (1b) into an analog video signal. D / A conversion circuit for conversion
(10), detecting a decrease and disturbance of the synchronization level of the video signal,
A dropout detection circuit (3) that prohibits writing to the field memory (1b) according to the detection result and an input video signal is read when the dropout detection circuit (3) detects a missing video signal. A video signal dropout compensation method that is equipped with a switch (8) that switches to a video signal and interpolates the video signal.