JPS62166543A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To optimize a capacity value necessary for each cell by sharing the noise preventing capacity of reference level generated from a reference level generator in each cell to be arranged. CONSTITUTION:A noise preventing capacity 22 is provided near a noise preventing noise limiter resistor 25 of a vertical stack gates of each cell 21, and the capacitor 22 is connected with a reference level signal Vref from a reference level generator 23. The generator 23 has transistors T01, T02 connected in series between power sources VCC and VEE, and a transistor T03 having a base common to the transistor T02 and connected at its collector with the base of the transistor T01, and the capacity 22 is connected between the collector of the transistor T02 and the power source VCC. The capacity 22 operates to accelerate a current switching operation by suppressing the variation in the reference level signal.

Description

[Detailed Description of the Invention] [Summary] The present invention realizes a current switching type circuit such as a desired ECL circuit or CML circuit, which is composed of a plurality of cells in which transistors and resistors are arranged in advance, and the transistors and resistors are used as desired. In a gate cell array that is wired to
By distributing the capacitance for each cell to prevent fluctuations when the reference level signal generated from the reference level generation circuit for providing the reference level of the current switching type circuit fluctuates. , to provide a semiconductor integrated circuit that can be optimized to the capacitance value required for each cell.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit, and particularly to a current switching type gate array circuit.

[Traditional technique]

It is generally known that noise occurs in the reference level when driving the gates of several cells with one reference level generation circuit. This noise causes the gate speed to slow down. Further, the amount of noise is proportional to the number of drive gates. Therefore, in highly integrated ECL gate cells having a large number of gates, the reference level generation circuit for driving the gate cells has a noise prevention capacitance corresponding to the number of gates of each gate cell driven by each reference level generation circuit. It is set up. Conventionally, when four gate cells 1, 1, 1.1 are driven by one reference level generation circuit 2 as shown in FIG. 7, for example, one capacitor 3 is provided to prevent noise at the reference level. was.

In other words, for each of the four cells 1, 1, and 1.1, one noise prevention capacitor 3 was selected and provided with a size corresponding to the four gate cells. .

[Problem that the invention seeks to solve]

The noise prevention capacitor 3 of the conventional reference level generation circuit 2 has a capacitance corresponding to the total number of gates of four cells, so even when driving only one gate cell, it has a capacitance equivalent to the total number of gates of four gate cells. In addition, since the noise prevention capacitor 3 was provided within the reference level generating circuit 2, its area was large. Therefore, high integration could not be achieved sufficiently.

[Means for solving problems]

According to the present invention, the capacitance for preventing noise of the reference level generated from the reference level generation circuit is distributed and arranged for each cell, and the capacitance provided in each cell is increased in accordance with the number of gates of each cell. It is designed to have a certain value.

[For production]

As a result, the cell area of the reference level generation circuit can be reduced, and since a capacitor is provided for each cell, the capacitance value of the noise prevention capacitor can be adjusted to a desired value according to the number of stages of each cell. Since the capacitance can be selected in a specific manner, the area of the capacitance can be made small, and a large number of gates can be driven by one reference level generation circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows an example of a gate array LSI chip layout. Pads 12 for signal input/output are arranged around the periphery of a chip 11, and a plurality of An internal gate cell region 14 is provided in which gate cells are arranged in a matrix.

Figure 1! 11) shows an embodiment of the semiconductor integrated circuit according to the present invention, in which a capacitor 22 for preventing noise of the reference level signal is separately provided for each cell 21. A reference level generation circuit 23 is provided in an adjacent region via a channel region 24, and four cells 21 are further provided via a channel region 24.
A capacitor 22 is separately provided for each of the capacitors.

By wiring from one reference level generation circuit 23 to the capacitance 22 of each cell as shown in the figure, one reference level generation circuit 23 can individually drive the capacitors 22 of eight cells 21.21. . Note that a large number of cells, for example 16, may be driven by one reference level generation circuit 23.

FIG. 1 (bl is an enlarged view of the arrangement pattern of transistors and resistors in each cell 21, and the noise prevention capacitor 22, which is the main part of the present invention, is It is provided near the noise limiter resistor 25 for prevention.Although not shown, the noise prevention capacitor 22 receives the reference level signal V from the reference level generation circuit 23.
Connected to the ref line. Note that the input gate transistor 26 has a noise limiter resistor 25 in the center of the cell 21.
are arranged at the outer periphery of the cell 21.

FIG. 1C is a circuit diagram showing the reference level generating circuit 23, the noise prevention capacitor 22, and a portion 27 of the ECL gate. In other words, the reference level generation circuit 23 receives the power supply VCC+Vi:. A transistor T connected in series between
It consists of OI, TQ2, and a transistor Toz that has a common base with the transistor TO2 and whose collector is connected to the base of the transistor T[11.
] 2 collector and power supply■. Noise prevention capacitor 2 between
2 are connected.

The noise prevention capacitor M22 functions to speed up the current switching operation by suppressing fluctuations from the reference level signal. Note that if a noise prevention capacitor is wired as a load to the collector of the current switching type circuit, the delay between the gates can be guaranteed. In the present invention, since the noise prevention capacitor is arranged for each cell, it is possible to set the noise prevention capacitor to an optimum value in consideration of the number of gates and the amount of delay for each cell.

In the following, an example of an ECL gate will be described in detail using a single cell consisting of a combination of a transistor and a resistor.

Figures 3+11), (b), and (C) are a circuit diagram, a block diagram, and a semiconductor pattern diagram of a constant current type ECL four-way OR/NOR circuit, respectively.

First, a four-person OR/NOR circuit constituting an ECL gate will be explained using FIGS. 3(a) and 3(b).

The forward voltage drop across the pace emitter is VD (approximately 0.7
V). The transistor T6 generates a constant current, and the emitter current of 1 + = (Vc 5-VD-■! ri/R4 causes a collector current approximately equal to the emitter current to flow.Transistors T1 to T4 are common emitter and common collector transistors. These common emitters and the emitter of transistor T5 become common and form a current switching type OR/NOR gate.That is, for example, when the input IN+ of T1 goes to the ligh level, the voltage changes from vcc to R+.

Constant current flows between R2 and the collector-emitter of transistor T1! += (Vcs-Vo Vgg)/R
a flows, and the common collector terminal of T I-T a is Vcc
-(R1+R2)Xll becomes Low level, and the emitter of emitter follower transistor T7 is
. This results in a lower LO level.

When at least one of the inputs of T1 to T4 is at the old gh level, the emitter of T7 is at the Lo- level, so it is NOR.
Works as a gate. On the other hand, the input I N + of T1 to T4
, I N 2 , I N 3 , I N
Since I5 is off when at least one of 4 is at the old gh level, the collector of Ts is at the old gh level, and the emitter of the emitter follower Ta is at the old gh level, which is lower by vo. Therefore, the emitter output of T8 works as an OR logic.
It is a capacitor for noise prevention of the reference level signal input to the ref terminal, and is selected to have a size for each cell depending on the number of gate stages of that cell.

Figure 3 (C1) shows how the four-person OR/NOR circuit shown in Figures 3 (a) and (b) is realized on gate cells arranged according to the present invention, and each wiring is The transistors, resistors, inputs, and outputs indicated by thick lines correspond to those shown in FIGS. 3(a) and (b), so they are indicated by the same reference numerals and detailed explanations are omitted. VCC power supply lines 31, V, and power supply lines 32 are provided as second-layer wiring superimposed on both sides of the cell 21, and an input gate transistor 26 is formed in the center of the cell 15 between the power supply lines 31 and 32. Transistors T1 to T4 are arranged.A resistor 25 for noise limiter resistance is arranged at the outer periphery of the cell, but is not connected.A noise prevention capacitor ff122 is connected to each cell 2.
1, the periphery of the cell and the noise limiter resistor 2
5 and connected to the V ref line by wiring.

FIGS. 4(a), 4(b), and (cl) are a circuit diagram, a block diagram, and a semiconductor pattern diagram of a constant current type ECL two-manpower NOR circuit, respectively.

First, the two-man powered N0RECL circuit is shown in Figure 4+a), Tb
).

Transistor T4 (T9) creates a constant current and is 1 +
= (Vsc Vo Va a) /R3(1
2" (Vcs Vo Vag)/Rt) causes a collector current approximately equal to the emitter current to flow. Since the transistors TI and T2 (T?, Ta) are common emitter-collector transistors, the common emitter and transistor The emitter of T3 (T8) is common to form a current switching type two-man power NOR gate.In other words, the input IA+ (Ie+) of TI (T6)
When the voltage reaches the ligh level, R1, R2 from Vcc
The constant current It (I2) flows between the collector and emitter of the transistor T+ ('r'G), and TI, T2
The common collector of (T6.TV) becomes Low level,
Emitter follower transistor T 5 (T + o
) emitter is than ■. becomes a low level. T +, T2 (Ta, TV) input I A
＋.

Since the energy of T5 (Tlo) becomes Low level when at least one of IA2 (IB+, IB2) is at Light level, it works as a two-man NOR gate (22 is V r from a reference level generation circuit (not shown).
This is a capacitor for noise prevention of the reference level signal input to the ef terminal.

FIG. 4(C) shows how the two-person NOR circuit shown in FIGS. 4(a) and (b) is realized on gate cells arranged according to the present invention, and each wiring is indicated by a thick line. Since each transistor, resistor, input, and output correspond to those shown in FIGS. 4A and 4B, the same reference numerals are used, and detailed explanation thereof will be omitted.

Note that a CC power line 31° and a 6° power line 32 are provided as second-layer wiring superimposed on both sides of the cell 21, and an input gate is connected to the center of the cell 21 between these power lines 31 and 32. Transistors T+ to T4 forming transistor 26 are arranged. The noise limiter resistor 25 is arranged on the outer periphery of the cell, but is not wired.

The noise prevention capacitor 22 is provided for each cell 21 at the periphery of the cell and near the noise limiter resistor 25,
Connected to the V ref line by wiring.

FIGS. 5A, 5B, and 5C are a circuit diagram, a block diagram, and a semiconductor pattern diagram of a constant current type ECLAND/NAND circuit, respectively.

First, the vertically stacked ECLAND/NAND circuit is shown in Figure 5 (a
) and (b).

The forward voltage drop between base and emitter is vo (approximately 0.7
V). Transistor T? to which inputs IBI, IB2゜IAI, IA2 are added? .

Each pair of T8 and TI, T2 has a common emitter,
It works as an or gate because it is connected by a common collector. For example, with T7 and T8 bare, Ili on the base of T7
If the gh level 8 is input, a current flows between the collector and emitter of T7, and the Illight level of V, -2V0 is input to the base terminal of the transistor T4. In other words, the reference voltage V input to the base of T5
A level higher than the voltage value of ref 2 is input. Therefore, since it forms a current switching type gate with a common emitter with T5, when T4 is in the on state, T5 is in the off state, and a constant current is applied to the collector of T4, that is, I+ = (V
csV. -■5□)/R4 current flows.

In this state, I, which is the base input of transistor T1,
AI is the reference voltage Vr applied to the base input of T3
When the voltage is higher than ef+, T1 is turned on regardless of the state of T2, and T3 is turned off. Therefore, the constant current flows between R1, R2 and the collector of TI.
It flows between the emitters and between the collector and emitter of T4. When an illumination level is input to at least one base of T1 or T2 and an old gh level is applied to at least one base of T7 or Tθ, a current flows through R1, R2 and either T1 or T2. , the current will flow through T4 to the emitter of T6. At this time, the common collector of T1 and T2 is VcC-(R1+R2)XI! The emitter of Too becomes a Low level that is lower by vo than that of Loee, and functions as a NAND gate. That is, for example, T1 or T2 is on and only when T4 is on.
oo becomes Lo% lebel. At this time, T3 is in the off state, so the collector terminal of T3 is in the Hi state of Vcc R+I+.
gh level, and the emitter terminal of T9 becomes v higher than that level.
The old gh level is lower by o. That is, since the logic of the collector terminal of T3 is opposite to the logic of the common collector terminal of TI and T2, it works as an AND, and the transistor Tq
The emitter of is lower than the voltage of the common collector terminal by Vo, but the logic is the same, so it is assumed to be an AND (22 is a capacitor for noise prevention of the reference level signal input to the V ref terminal from a reference level generation circuit (not shown). Further, the noise limiter resistor 25 is connected between the collectors of T4 and T5.

Figure 5(C) shows the 4 shown in Figures 5(a) and (b).
It shows how an AND/NAND circuit is realized on gate cells arranged according to the present invention, each wiring is shown with a bold line, each transistor and resistor, input and output are shown in FIGS. 5(a) and 5(a), respectively. Since it corresponds to that shown in Tb), the same reference numerals are used and detailed explanation will be omitted. In addition, VCC power supply lines 31 and V are superimposed on both sides of the cell 21 as second layer wiring. 6 power line 32
A cell 15 is provided between the power supply lines 31 and 32.
Transistors T1 to T4 forming the input gate transistor 26 are arranged in the center of the gate. The noise limiter resistor 25 is arranged at the outer periphery of the cell.

The noise prevention capacitor 22 is provided in the vicinity of the noise limiter resistor 25 for each cell 21, and is connected to the V ref line by wiring.

FIGS. 6(a), (b), and (c) are a circuit diagram, a block diagram, and a pattern diagram of a constant current type ECLD-latch circuit, respectively.

First, with reference to Figure 6(a) and fb), vertically stack EC
The LD-latch circuit will be explained.

Since the transistors T7 and T8 have a common emitter, they constitute a current switching gate, and the transistor T9 connected to the common emitter causes a constant current of 1-V to be applied to the collector of either transistor T7 or T8.
Current flows between the emitters. For example, when the voltage of the clock CLK input to the base of T1 is at the old gh level of vI, the base of T7 has a voltage of vz-2vo higher than that voltage.
The old gh level is applied, forming a state in which T7 is on and T8 is off. T3 and T4 have a common emitter, and the collector of T& is connected to the emitter of T++ and the base of T3 via R8, and the collector of T3 is connected to the emitter of Too and the base of T4 via R7, so it is a flip-flop. It consists of For example, when T3 is on and T4 is off, a current flows through T3 through R1 and R2, and a current flows through T3 between the collector and emitter of T1 through T7, and V+o- flows through the emitter of Tlo.
(VcC(R1+R2)/II) -V.

A voltage of (transistor T+a base-emitter voltage) is applied. The emitter of Too has I Ia=V+
Since a-V@@/ (R?+R5) flows, the low level of V+ 0-R7XI I O is applied to the base terminal of T4. That is, when the base of T3 is at the 11high level, the base of T4 is at Lo-, the collector of the on-transistor T3 is at the LO- level, and the collector of the off-transistor T4 is at the LO- level.
The collector becomes High level and enters a bistable state. Similarly, when T3 is off and T4 is on, T3 and T4
The respective collectors of are at the H'high and Lo- levels, respectively, forming a bistable state. T3 is on and T
If a low state different from the Hfgh state of the collector terminal of T4 is input to the D input of T2 while T4 is off, the transistor T6, which has a common emitter with T2, is turned on. However, when the clock input is at the old gh level, Te is in the off state, so Te (
7) T2 hole connected to collector. T6 (7) Almost no current flows through the common emitter and the noise limiter resistor 25
Only a small amount of water flows through the Therefore, in this state, the flip-flop remains unchanged, with T3 remaining on and T4 remaining off. After this D input goes low,
When the clock input is dropped to low level, T7 is off and T
o is turned on. Then, since T6 can be turned on, the collector terminal of T6 has a constant current of 1 through R1, R3, between the collector and emitter of T6, and between the collector and emitter of Te. Ts's Kore F2< The lid will be Lo% Lebel. That is, the collector of T4 also becomes LO-level. If this is Lowa, T +
+ The power becomes low level and the base of T3 becomes low level. That is, T3 changes from on to off. When T3 turns off, the collector of T3 becomes the old gh level, that is, Vcc R+I+, and the old gh level, which is lower than this old gh level by the sum of the voltage drop between the base emitter and ivy of Too and the voltage drop flowing through R7, becomes T.
T4 is applied to the base of T4, and T4 changes from OFF to ON state, and its collector terminal becomes Low level. Then, it becomes bistable again, and this bistable state is maintained even if the clock input returns to the old gh level.

Note that the output of the flip-flop is the voltage at the collector terminal of T4 via the emitter farrow TI2.

When the clock is in the old gh state, when the clear input CR is set to the old gh state, the transistor T5 is forcibly turned on, so the collector of Ts, and therefore the collector of T4, is forced to the LO- level, and the collector of T3 is forced to the LO- level. The collector is in the old gh state. That is, the output terminal Q is forced to be at Lo% level.

22 is a capacitor for noise prevention of a reference level signal inputted to the V ref terminal from a reference level generation circuit (not shown).

FIG. 6(C) shows how the four-person OR/NOR circuit shown in FIG. The transistors, resistors, inputs, and outputs shown by thick lines correspond to those shown in FIG. In addition, VCC power supply lines 31, V, and power supply lines 32 are provided as second-layer wiring superimposed on both sides of the cell 15, and an input gate transistor is provided in the center of the cell 15 between the power supply lines 31 and 32. Transistors T1-T4 forming a transistor 26 are arranged. A resistor 25 for noise limiter resistance is arranged on the outer periphery of the cell. The noise prevention capacitor 22 is provided for each cell 21 near the noise limiter resistor 25 at the outer periphery of the cell 21, and is connected to the V ref line by wiring.

〔Effect of the invention〕

According to the present invention, since the noise prevention capacitor is divided and provided for each cell, the size of one capacitor can be optimized according to the number of gates of one cell, and only one cell is driven. In this case, it is only necessary to use a noise prevention capacitor of a size corresponding to the number of gates in that cell, and it is also possible to drive the noise prevention capacitors of many cells with one reference level generation circuit. .

[Brief explanation of drawings]

FIG. 1(a) is a block diagram showing an embodiment of the present invention, FIG. 1(b) is a layout diagram showing an enlarged pattern of one cell according to the present invention, and FIG. 1(C) is a block diagram showing an embodiment of the present invention. A circuit diagram showing an ECL gate, a reference level generation circuit, and a noise prevention capacitor; Fig. 2 is a layout diagram of a gate array LSI chip; Fig. 3 (al, (bl), (C) shows an embodiment of the present invention. 4 (at, (bl, (cl) represent one embodiment of the present invention, respectively, a circuit diagram, a block diagram, a pattern diagram of a semiconductor integrated circuit, and a constant current type ECL 4 manual OR/NOR circuit, respectively. Type ECL2 manual NOR circuit circuit diagram, block diagram, pattern diagram of semiconductor integrated circuit, 5th
Figures (a), (bl, and (c) show one embodiment of the present invention, respectively, a circuit diagram, a block diagram, a pattern diagram of a semiconductor integrated circuit, and a pattern diagram of a constant current type ECLAND/NAND circuit. (b), (C1 is a circuit diagram, a block diagram, and a pattern diagram of a semiconductor integrated circuit, respectively, of a constant current type ECLD latch. Figure 7 is a layout diagram showing the arrangement of a conventional cell, a reference level generation circuit, and a noise prevention capacitor. 21... Cell, 22... Noise prevention capacitor, 23... Reference level generation circuit, 24... Channel region, 25... Noise limiter resistor, 26... Input gate transistor Patent applicant Fujitsu Ltd.
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Claims (1)

[Claims] A cell in which each element of a transistor and a resistor is arranged to constitute a current switching type circuit, a reference level generation circuit that generates a reference level signal for driving each cell, and a reference level generation circuit that prevents the reference level signal from fluctuating. A semiconductor integrated circuit consists of a capacitor provided for each cell.