JPS59214327A - Logical circuit device - Google Patents

Abstract

PURPOSE:To reduce power consumption and also obtain a proper delay time by controlling the amount of a current which flows an emitter follower transistor (TR) through two TRs according to an input logical level which is high or low. CONSTITUTION:When the emitter of an emitter follower TR Q5 or Q6 (i.e. output terminal 01 or 02) is at a high logical level Vh, almost no emitter follower current flows, but when at a logical level V1, an emitter follower current flows. The circuit current is therefore reduced. Further, when an input potential Vin rises from the low logical level V1 to the high logical level Vh, an input TR turns on and a TRQ7 also turns on to draw a charge out of a load capacitor added to the output terminal 01 directly through the TRQ7, so a delay time in an NOR output fall is improved. Similarly, a delay time in an NOR output rise and a delay time in an OR output fall are also improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed logic circuit device, and particularly to one that aims to reduce power consumption.

Currently, emitter-coupled logic circuit devices (ECL) are widely used as high-speed logic circuit devices. FIG. 1 is an equivalent circuit diagram showing a conventional emitter-coupled logic circuit device, in which Ql, Q2. and Q3 are connected in parallel, respectively.
In other words, each collector is connected to each other and each emitter is connected to each other,
Each base is an input transistor connected to input terminals 11, 12 and I3, respectively, and the commonly connected collectors are connected to the collector side power supply voltage Vcc, which is the first power supply, through the first load resistor R1, and the common The connected emitter is connected to a current source C8. Q4 is a reference transistor whose base is connected to the reference potential vbb,
The emitter of the input transistor Q1. Q2. Q3 is connected to the commonly connected emitter of the current source C3.
The collector is connected to the collector side power supply voltage Vcc via the second load resistor R2. Q5 is an emitter follower transistor whose collector, base, and emitter are respectively connected to the collector side power supply voltage Vcc, the input transistor Ql, and the commonly connected collector and emitter follower resistor R3 of Q2 and Q3, and its emitter is the output terminal 01. It is something. Q6 has collector, base and emitter each with collector side power supply voltage V
cc is an emitter follower transistor connected to the collector of the reference transistor Q4 and the emitter follower resistor R4, and whose emitter is the output terminal 02.

In a logic circuit device configured in this manner, the collector side power supply voltage Vcc is usually the ground potential,
The emitter side power supply voltage Vee, which is the terminal voltage of the emitter follower resistors R3 and R4, is a negative potential, and the output terminals 01,
02 is NO for input terminals 11, 12, and I3, respectively.
R output, OR output.

Next, the operation of the logic circuit device having the above configuration will be explained.

First, input transistors Ql, Q2 . The base of Q3, that is, the input terminal 11. , I2. When all the input potentials Vin applied to I3 are at a lower level than the reference potential vbb,
Input transistors Ql, Q2 . Q3 becomes non-conductive, while reference transistor Q4 becomes conductive. Therefore, input transistors Ql, Q2 . The collector potential of Q3 becomes almost Vcc potential, and the collector potential of reference transistor Q4 decreases from Vcc potential by the voltage drop across load resistor R2. Therefore, emitter follower transistor Q5. According to the base potential of Q6, the output terminal 01 becomes high level and the output terminal 02 becomes low level.

Next, input transistors Ql, Q2 . When at least one input potential among the input potentials Vin applied to the bases of Q3 becomes higher than the reference potential vbb, the input transistors Ql, Q2 . Since at least one of the input transistors Q3 becomes conductive, the input transistors Ql, Q2 . The collector potential of Q3 is lowered from the Vcc potential by the voltage drop across the load resistor R1, and the base potential of the emitter follower transistor Q5 is lowered, so the output terminal 01 becomes low level.
On the other hand, the reference transistor Q4 becomes non-conductive, the collector potential of the reference transistor Q4 becomes approximately Vcc, and the emitter followers II, I2 . I3
For this, output terminal 01 is NOR output, output terminal 02 is O
It becomes R output.

By the way, in the ECL circuit device configured in this way, the circuit current flows through the input transistor Ql.

Q2. Q3, reference transistor Q4, load resistors R1, R2 and current source CS, and emitter follower transistor Q5. It consists of an emitter follower current flowing to the emitter follower stage composed of Q6 and emitter follower resistors R3 and R4.Moreover, it has two emitter follower circuits, and the emitter follower current always flows through both emitter follower circuits. There is a drawback that the circuit current of the entire ECL circuit becomes large.

The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and eliminates the NOR and OR output emitter follower resistors, and replaces them with new first and second emitter follower transistors for each emitter follower transistor. the bases of the first and second transistors are connected to the combined emitters of the input transistor and the reference transistor and to a second reference potential, respectively, and the emitters of the transistors are connected to a second current source. The structure is connected to the second power supply via the N0R
(Illll Main emitter follower transistor The potential applied to the base of the first transistor connected to the
Reduce power consumption by controlling the amount of current flowing through the emitter follower transistor depending on the magnitude of the second reference potential applied to the base of the second transistor connected to the R side emitter follower transistor,
Another object of the present invention is to provide a logic circuit device that can improve delay time.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the logic circuit device according to the present invention, and in particular, a three-person N circuit.

1 shows a logic circuit device with an R output and an OR output. In the figure, Ql, Q2, and Q3 are input transistors whose bases are connected to input terminals II and 12.13, respectively, and Q4 is an input transistor whose base is connected to the first reference potential V bb.
a reference transistor connected to R1, R1 is the first
power supply Vcc and input transistors Ql, Q2 . A first load resistor, R2, connected between the common collector of Q3 and the first power supply Vcc and a reference transistor Q4.
A second load resistor C3I connected between the collectors of the input transistors Ql, Q2 . Q3 and a first current source for supplying switching current to which the emitters of reference transistor Q4 are connected in common; Q5 and Q6 have their bases connected to input transistors Ql, Q2 . First and second emitter follower transistors, Ql and Q8, connected to the collector of Q3 and the collector of reference transistor Q4, have their bases connected to input transistors Ql, Q2 . Q3. Reference transistor Q
4 and the second reference potential V bb2 for controlling the lower current. The second transistor is the emitter of the first emitter follower transistor Q5 and the first emitter follower current control transistor Q7.
The collector of the second emitter follower transistor Q6 and the collector of the second emitter follower current control transistor Q8 are connected to the NOR output terminal 01.
They are respectively connected to the R output terminal 02.

That is, in this embodiment, the emitter follower resistors R3 and R4 in the conventional ECL circuit device shown in FIG. Two transistors Q7. connected to Vbb2. Q8, their emitters are commonly connected to a current source C32 for supplying emitter follower current, and their collectors are connected to the emitter of the emitter follower transistor, and the emitter follower current is supplied by one current source. C
32 will be supplied.

Next, the operation of the logic circuit device configured as described above will be explained.

First, input terminal 11. I2. When the input potentials Vin applied to R3 are all at a low logic level V1 lower than the reference potential Vbbl, the input transistors QL Q2 . Q
3 becomes non-conductive, and the reference transistor Q4
becomes conductive. Therefore, the input transistors Ql, Q
2. The collector potential of Q3 is approximately Vcc potential, and the collector potential of reference transistor Q4 is equal to the load resistor R.
The potential is lowered from the Vcc potential by the voltage drop at 2. Therefore, according to the base potentials of the emitter follower transistors Q5 and Q6, the output terminal 01 becomes a high logic level vh, and the output terminal 02 becomes a low logic level Vl. Also at this time, input transistors Ql, Q2 . Point 1 where the respective emitters and terminals of Q3 and reference transistor Q4 are commonly connected
The potential becomes a potential Vbb1-Vbe which is lower than the reference potential Vbbl by the forward direction Vbe between the base emitter and the ivy of the reference transistor Q4.

On the other hand, input terminals If, T2. The input potential Vin applied to at least one input terminal of I3 is the reference potential V
When the high logic level vh becomes higher than bbl, the input transistor to which vh is applied becomes conductive, and the reference transistor Q4 becomes non-conductive. Therefore, the input transistor Ql.

Q2. The collector potential of Q3 is lowered from the Vcc potential by the voltage drop across the load resistor R1, and the collector potential of the reference transistor Q4 becomes approximately the VCC potential. Therefore, according to the base potentials of the emitter follower transistors Q5 and Q6, the output terminal 01 becomes a low logic level Vl and the output terminal 02 becomes a high logic level vh. Also at this time, the input transistor QL Q2. The potential at point 1, where the emitters of Q3 and reference transistor Q4 are commonly connected, becomes a potential lower than the high logic level vh by the base-emitter forward voltage Vbe of the input transistor, that is, Vh - Vbe.

As described above, input transistors Ql, Q2 . The potential at point 1, where the emitters of Q3 and reference transistor Q4 are commonly connected, that is, the base potential of transistor Q7 connected to emitter follower transistor Q5, changes relatively high and low in phase with the change in the input logic level. do. Therefore, the value of the reference potential Vbb2 applied to the base of the transistor Q8 connected to the emitter follower transistor Q6 is appropriately set (Vh + Vb
b1)/2-Vbe), when the input potential Vin is at the high logic level vh, the transistor Q
7 can be in a conductive state and transistor Q8 can be in a non-conductive state, and when the logic level is low (1), the transistor Q7 can be in a non-conductive state and the transistor Q8 can be in a conductive state. As a result, the following effects can be expected.

That is, input transistors Ql, Q2 . When all Q3 are non-conducting, the NOR output (then high logic level vh
Since the transistor Q7 is in a non-conducting state, almost no current flows through the emitter follower transistor Q5, which has an OR output (at this time, the low logic level V1
), current flows through transistor Q8. In addition, input transistors Ql, Q2 . When one of Q3 is in a conductive state, NOR output (at this time, low logic level Vl
) with an emitter follower transistor Q5
, current flows through transistor Q7, which is conducting, and almost no current flows through emitter follower transistor Q6, which has an OR output (now at a high logic level vh), since transistor Q8 is non-conducting.

In other words, according to the circuit configuration of this embodiment, when the emitter of the emitter follower transistor Q5 or C6 (i.e., output terminal 01 or 02) is at the high logic level vh, almost no emitter follower current flows, and when the emitter follower transistor Q5 or C6 is at the low logic level V1, the emitter follower current does not flow. Follower current flows. Therefore, as in the ECU circuit device shown in FIG.
Compared to a circuit configuration in which an emitter follower current always flows regardless of the output level, the circuit current can be reduced.

Further, in the logic circuit of the above embodiment, the input potential Vin
When transitions from the low logic level V1 to the high logic level vh, the input transistor becomes conductive and the transistor Q7 connected to the emitter follower transistor Q5 becomes conductive, causing the load capacitance added to the output terminal 01 to become conductive. Since the charge stored in the transistor Q7 is directly extracted through the transistor Q7, the delay time when the NOR output falls is improved. At this time, the reference transistor Q
4 and transistor Q8 are rendered non-conductive, and all of the current supplied from emitter follower transistor Q6 flows into the load capacitance added to output terminal 02, thereby improving the delay time when the OR output rises. Similarly, when the input potential Vin transitions from the high logic level vh to the low logic level Vl, 1. The transistor Q8 connected to the reference transistor Q4 and the emitter follower transistor Q6 becomes conductive, and the transistor Q7 connected to the input transistor and emitter follower transistor Q5 becomes non-conductive, thereby reducing the delay time when the NOR output rises and the OR output rise. This improves downlink delay time. The larger the load capacity, the more remarkable the above improvement effect becomes.

In the above embodiment, the case where both NOR and 08 outputs are taken out is explained, but only NOR output or OR output is taken out.
It is also possible to take out only the output, in which case the emitter follower transistor of the unused output is removed (and the collector of the transistor to be connected to the emitter of the emitter follower transistor is connected to the first power supply Vcc). The same effect as in the above embodiment can be achieved in terms of delay time improvement.

That is, in FIG. 2, the first output transistor and the first output terminal are removed, and this is the second invention of the present application. The third invention of the present application is one in which the output terminal is removed, and this is shown in FIG.

As described above, according to the present invention, the emitter follower transistor in the ECL circuit device is removed, and instead, the collector is connected to the emitter of the emitter follower transistor, and the base is connected to the emitters of the input transistor and the reference transistor in common. A transistor connected to the second reference potential is newly provided, and these two transistors can reduce the amount of current flowing through the emitter follower transistor depending on the level of the input logic level, thereby reducing power consumption. This has the effect of reducing the delay time and improving the delay time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional EMI-TSUTA coupled logic circuit device, FIG. 2 is a circuit diagram showing an embodiment of a logic circuit device based on the first invention G of the present application, and FIG. It is a circuit diagram showing an implementation/example of the third invention of the present application. Ql, C2, C3...input transistor, C4...
Reference transistor, Vbbl...first reference potential, C5, C6...first. Second emitter follower 1 to transistor (first and second output transistors), C81... current source for supplying current notching (first
current source), C7, C8... emitter follower current control transistors (first and second transistors),
Vbb2...second reference potential, C32...emitter follower current supply current source (second current source), Il, 1
2. I3...Input terminal, Ql, 02...1st゜2nd
Output terminal, Vcc - Collector side power supply (11 power supply), Vee... Emisoku side power supply (second power supply)
, R1, R2...first. A second resistive element. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3

Claims (3)

[Claims] (1) at least one input transistor whose base is connected to each input signal terminal and whose collector and emitter are commonly connected; a first reference potential is applied to the base and whose emitter is a common emitter of the input transistors; a first resistive element connected between a common collector of the transistor and a first power source; a first resistive element connected between a collector of the reference transistor and the first power source; a second resistive element; a first current source connected between the common emitter and the second power source; a base connected to the common collector; a collector connected to the first power source; and an emitter connected to the first output terminal. A first output transistor connected, a second output transistor whose base is connected to the collector of the reference transistor, whose collector is connected to the first power supply, and whose emitter is connected to the second output terminal, whose base is common to the above. A first transistor having an emitter and a collector connected to the first output terminal and an emitter connected to the second power supply via a second current source, and a base having a second reference potential and a collector connected to the first output terminal. 2. A logic circuit device comprising: a second transistor connected to the second output terminal via the second current source and the second transistor connected to the second power source via the second current source. (2) At least one input transistor whose base is connected to each input signal terminal and whose collector and emitter are commonly connected, and whose base is applied with a first reference potential and whose emitter is connected to the common emitter of the input transistors. a first resistive element connected between the common collector of the input transistor and the first power source; a second resistive element connected between the collector of the reference transistor and the first power source; a resistive element, a first current source connected between the common emitter and a second power source, a base of which is connected to the collector of the reference transistor, a collector of which is connected to the first power source, and an emitter of which is connected to the output terminal. a first transistor having a base connected to the common emitter, a collector connected to the first power supply, and an emitter connected to the second power supply via a second current source; A logic circuit device comprising: a second transistor having a collector connected to a second reference potential, a collector connected to the output terminal, and an emitter connected to the second power source via the second current source. (3) at least one input transistor whose base is connected to each input signal terminal and whose collector and emitter are each commonly connected; a first reference potential is applied to the base and whose emitter is coupled to the common emitter of the input transistor; a first resistive element connected between the common collector of the input transistor and the first power supply; and a second resistive element connected between the collector of the reference transistor and the first power supply.
a first current source connected between the common emitter and a second power source; a tenth current source having a base connected to the common collector, a collector connected to the first power source and an emitter connected to the output terminal; a first transistor whose base is connected to the common emitter, whose collector is connected to the output terminal, and whose emitter is connected to the second power supply via a second current source; and whose base is connected to the second reference potential. and a second transistor having a collector connected to the first power source and an emitter connected to the second power source via the second current source.