JPS594231A - High-speed logical circuit - Google Patents

Abstract

PURPOSE:To decrease remarkably the circuit delay time, the rising and falling time, by providing a differentiating circuit at the base of a transistor(TR), connecting the circuit to a reference power supply via a resistive element and applying a signal inverting the input signal via a capacitive element. CONSTITUTION:The delay time of the circuit is defined as a time from the 50% value of an input signal amplitude to the 50% value of an output signal amplitude, and a delay time from an input signal 21 to an output signal 25 in a conventional circuit is denoted by tpdout. The base voltage of the TR1 is a common mode input signal voltage 21 itself, but the base voltage of a TR2 is a differentiating signal 23 of an inverted input signal voltage 22, then the operation starting point of the circuit is changed from the conventional point B to a point A, the operation is started earlier by DELTAt, and the delay time t'p'dout from the input signal 21 to the output signal 24 is almost tpdout-DELTAt. Further, the circuit is operated equally with the case that a signal having a half the falling and rising time is applied to the input of a conventional circuit, the rising and falling time of an output signal 24 is smaller than the output signal 25.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to digital logic circuits, and more particularly to a high-speed logic circuit suitable for fields such as computers that require ultra-high-speed logic operations.

In recent years, there has been an increasing desire for faster logic circuits.

Conventional methods for speeding up logic circuits include reducing the signal amplitude to quickly complete charging and discharging of parasitic capacitance, increasing the current flowing through active elements, or making each element smaller to reduce parasitic capacitance. Although attempts have been made to reduce the capacitance and propagation time, the above-mentioned methods naturally have limitations due to securing margins, limiting power consumption, or limiting microfabrication technology. Conventionally, so-called emitter-coupled logic circuits (E
CL circuit) has been widely used. FIG. 1 shows a current switching section (referred to as a current switch) which is the main part of this circuit. The output voltage is determined by comparing the voltages applied to the two input terminals 12.13. Normally, a reference voltage VBB is applied to one input terminal, and an input signal is applied only to the other input terminal. Therefore, when the input is switched,
The current is not switched during the time until the input signal voltage reaches the reference voltage, and the switching operation of the circuit is delayed. In order to reduce such a delay, it is also possible to adopt a so-called differential input method in which mutually inverted input signals are added to the input terminals 12 and 13 without applying VBB. However, differential human power alone cannot perform logic other than negation, and requires mixed use with logic circuits that can perform other logics. Furthermore, since the differential input generally reduces the signal amplitude, it cannot be directly coupled to other logic circuits.

The purpose of the present invention is to
An object of the present invention is to provide a logic circuit that can significantly reduce circuit delay time and rise and fall times.

The present invention is based on the conventional current switch circuit 1 shown in FIG.
In step 6, a new differentiating circuit is installed on the base side of transistor 2, which was simply connected to the reference power supply VBH, and connected to the reference power supply via a resistive element, and a signal obtained by inverting the input signal is applied via a capacitive element. By doing so, in addition to the reference voltage, a differential signal of the opposite phase of the input signal is superimposed and applied to the base of the transistor. As a result, in terms of AC, the operation is essentially the same as when the input signal rise and fall times are halved, so the output signal rise and fall times can be shortened. , Furthermore, the delay time of the circuit can be shortened.

Embodiments of the present invention will be described in detail below with reference to the drawings.

A first embodiment of the invention is shown in FIG. This is comprised of a differentiating circuit consisting of a current switch 16, a resistive element 17, and a capacitive element 18 in FIG.

Next, the operation of this embodiment will be explained. FIG. 3 is a diagram showing the operation and effect of the high-speed logic argument of the present invention. In the same figure, 21, 22, 23.24 are respectively VBl, VB2°VB3. VO2 (7) is the voltage waveform, and 25 is the negative phase output voltage waveform in the m1 diagram. VH, VL.

The high level, low level and reference E pressure of VB B u logic are shown respectively. Now, in Figure 3, the delay time of the circuit is calculated from 50% of the input signal amplitude to 50% of the output signal amplitude.
% value, and the delay time from the input signal 21 to the output signal 25 in the conventional circuit configuration shown in FIG. 1 is defined as t pd out . At this time,
In the circuit of the present invention shown in FIG. 2, the base voltage of the transistor is the in-phase input signal voltage 21 itself, but the base voltage of the transistor 20 is the differential signal 23 of the negative-phase input signal voltage 22, so the circuit starts operating. The conventional point B is now the point A, and the operation starts earlier by the time Δt. Therefore, according to this embodiment, the delay time tpdout from the input signal 21 to the output signal 24 is approximately t pd
out - Δt.

Also, make the time constant of the differentiating circuit sufficiently thick (, VBB to VH
If the value is set to an intermediate value between VL and VL, the rise of the input signal and the delay time of the circuit can be made equal to the rise of the human input signal. In addition, since the operation is the same as when applying 0 to the input of a conventional circuit, the waveform shaping effect is not as thick, and the rising and falling edges of the output signal 24 of this embodiment are longer than those of the conventional circuit. can be made smaller than the output signal 25 of . Furthermore, if you do not particularly want to speed up the circuit, it can be treated as a conventional logic circuit without using reverse phase input, and since the signal amplitude does not change, it can be used in combination with other logic circuits. It is.

Next, another embodiment according to the present invention will be described.

FIG. 4 shows a case where the present invention is applied to a multi-input logic circuit. In FIG. 4, capacitive element 34 corresponds to input 26.27.
．． 35 is added, and the inverted signals of the signals applied to inputs 26 and 27 are applied to inputs 37 and 38, respectively. The operation of the circuit is the second
It is similar to the figure.

As described above, according to the present invention, without increasing power consumption or reducing signal amplitude, it is possible to achieve the same result as when inputting a signal with half the rise and fall times in a conventional circuit. The rise and fall times and circuit delay times can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventionally used current switch circuit, Fig. 2 is a block diagram of a high-speed logic circuit according to an embodiment of the present invention, and Fig. 3 is a diagram showing the operation and effects of the high-speed logic circuit. , FIG. 4 is a block diagram of a high-speed logic circuit having multiple inputs. 1.2, 26.27...transistor, 5.8°17
．． 31... Resistance element, 18.33-35... Capacity element, 10... Constant current circuit, 16.30... Current YJ 3 Port 'f' J4- Figure ■

Claims (1)

[Claims] 1. Two groups of transistors/diss, each consisting of a plurality of transistors whose emitters and collectors are connected in common and input signals applied to each pace, and a transistor whose emitters are connected to the emitters of the above transistor groups and which are referenced to the pace. A first transistor to which a voltage is applied and the commonly connected collectors of the transistor group; a load resistor connected between the collector of the first transistor and a high potential power supply; and a load resistor connected between the commonly connected emitter and the low potential. In an emitter-coupled logic circuit consisting of a constant current circuit connected between a power source and a constant current circuit, a reference voltage is supplied to the base of a first transistor via a resistor element, and an inverted signal of each input signal is supplied to a plurality of A high-speed logic circuit characterized in that a voltage is applied to the base of a first transistor via a capacitive element.